JP2011119987A - Semiconductor integrated circuit device - Google Patents

Abstract

An object of the present invention is to reduce fluctuations in the input capacitance value of an input terminal at the time of circuit gain switching and to greatly improve the frequency dependence.
ON / OFF operation control of switches 22 ( ₀ to _N ), 23 ( ₀ to _N ), 24 ( ₀ to _N ) is performed by control signals Ctrl0 to Ctrln, CtrlB0 to CtrlBn output from a logic controller. Each is controlled. Switch 24 ₍₀ ~ _N), the switch 22 ₍₀ ~ _N) is ON when (transistors 19 ₍₀ ~ _N) is biased off) to, ON becomes at the same timing, the switch 22 ₍₀ ~ _N) is OFF ( When the transistor 19 ( ₀ to _N ) is biased on, it is turned off at the same timing. Capacitance element 25 ( ₀ to _N ) is effective when transistor 24 ( ₁ to _N ) is biased off, and prevents large fluctuations in input capacitance value Cin viewed from input terminal IN when the circuit gain is switched. can do.
[Selection] Figure 2

Description

  The present invention relates to a transmission power adjustment technique in wireless communication, and more particularly to a technique effective for controlling transmission power over a wide range with high accuracy.

  In recent years, a safe driving support system using inter-vehicle communication has been widely studied. Inter-vehicle communication is a communication technique in which vehicles and vehicles exchange vehicle information such as speed by wireless communication. A semiconductor integrated circuit device for high frequency processing used in this type of wireless communication system is required to perform output power adjustment with high accuracy over a wide power adjustment range in order to perform communication more reliably.

  FIG. 11 is a block diagram showing a configuration example of the driver unit 100 used in the transmitter of the semiconductor integrated circuit device examined by the present inventors.

  As illustrated, the driver unit 100 includes a driver amplifier 101 and a driver amplifier 102, and adjusts the transmission output power by performing gain adjustment in each amplifier.

  FIG. 12 is a circuit diagram showing an example of the driver amplifier 101 (102) of FIG.

  As shown in FIG. 12, the driver amplifier 101 (102) is composed of an L load cascode amplifier circuit having a gain switching switch, and includes an inductor LD, a transistor MCAS, transistors M0 to Mn, resistors R0 to Rn, electrostatic Capacitance elements C0 to Cn, switches SWa0 to SWan, and switches SWb0 to SWbn are provided. In FIG. 12, IN represents an input terminal, OUT represents an output terminal, and VB represents a gate bias voltage.

  In this case, as shown in FIG. 13, the gain switching function turns on the gate bias of the MOS (Metal Oxide Semiconductor) transistors M0 to Mn by the switches SWa0 to SWan and the switches SWb0 to SWbn that are exclusively turned on / off. Realized by / OFF control.

  These switches SWa0 to SWan and SWb0 to SWbn use MOS transistors of the same size from the viewpoint of characteristic deviation due to parasitics. The bias ON / OFF control of the transistors M0 to Mn is individually performed according to a desired gain adjustment value. The state in which all the transistors M0 to Mn are ON is the maximum transmission power, and conversely, the state in which all the transistors M0 to Mn are OFF is the circuit shutdown state.

The subscript “n” is the number of amplifier stages, and is determined by the adjustment resolution of the amplifier gain. For example, if a resolution of 3 bits is required, n = 2 ³ −1 = 7. The gain is changed stepwise by adjusting the bias of the plurality of transistors M0 to Mn whose number is determined by the resolution.

In FIG. 12, the sizes of the transistors M0 to Mn are different from each other, and the step size for adjusting the amplifier gain is determined by adjusting the MOS size of the transistors. Here, regarding the relationship between the MOS sizes of the transistors, Mn has the maximum size and M0 has the minimum size. When the minimum adjustment step value of the amplifier gain is G _min [dB], the MOS size of each transistor and the relational expression can be expressed as follows.

For example, in a 3-bit (n = 7) adjustment resolution amplifier circuit, if gain adjustment is performed in 6 dB steps, the maximum size transistor M7 is M7 = M0 × 2 ⁶ = 64M0. It becomes.

   In order to perform gain adjustment step by step with a predetermined gain adjustment resolution, if the maximum power (all transistors are enabled) is the default, it can be realized by turning off transistor Mn to transistor M1 in order. is there.

  As a technique for varying the transmission power gain in this type of semiconductor integrated circuit device, for example, transmission power correction data for each carrier frequency is stored in an internal or external memory, and the correction data is read each time the carrier frequency changes. Thus, there is known a technique for improving the transmission power accuracy (see, for example, Patent Document 1). This correction data is obtained separately by preparing a test mode.

JP 2002-185341 A

  However, the present inventors have found that the transmission power control technique in the semiconductor integrated circuit device as described above has the following problems.

  When adjusting the transmission output power, it is desirable that the step value at the time of gain switching is uniform, but when the carrier frequency is high (for example, about 5 GHz or more) and the frequency band is wide (for example, Channel BW = 1 GHz), this There is a possibility that a phenomenon occurs in which the gain step value has frequency dependence and fluctuates depending on the channel used. This phenomenon has a problem of hindering highly accurate transmission power adjustment.

        FIG. 14 is an explanatory diagram showing frequency characteristics of transmission output power of the output terminal OUT when gain switching is performed in FIG.

  The parameter 'ATT' is a parameter for performing gain switching. As shown in FIG. 14, it can be seen that the frequency value at which the transmission power reaches a peak fluctuates by changing the gain setting.

  Further, in the characteristics of FIG. 14, difference data of the absolute value of the output power before and after the parameter “ATT” (for example, “ATT-01” is the difference of the absolute value transmission output power of “ATT0” and “ATT1” of FIG. 14). FIG. 15 shows the frequency characteristics of the gain switching value calculated from FIG.

  As shown in FIG. 15, it can be seen that each gain switching value varies depending on the frequency. This is because, as shown in FIG. 16, the parasitic capacitance values of the transistors M0 to Mn whose sources are grounded fluctuate with the gain switching.

  FIG. 16 is a diagram in which elements that cause the gain switching value to have frequency characteristics are added to FIG. 'Load Inductor Driver amp' shown in FIG. 16 represents a load inductor of the driver amplifier 101 in FIG. 11, and 'Cp0 to Cpn' mainly represents a parasitic parasitic between the gate sources of the transistors M0 to Mn. It is electric capacity.

The peak frequency of the output power at this time can be expressed by the following equation, where L _{L is} the load inductor of the driver amplifier 101, C _L is the parasitic capacitance value of the load inductor, and CP is the parasitic capacitance of the transistor. .

Here, it is generally known that the capacitance value changes depending on the bias condition of the gate of the transistor. The channel width of the transistor is W, the channel length is L, the oxide film capacitance is C _OX , and the overlap capacitance is C _OV .

The gate-source capacitance C _{GS (sat)} when the transistor is in the saturation region is

The gate-source capacitance C _{GS (off)} when the transistor is in the cutoff region is

From Equations (2) and (3), the gate-source capacitance difference when the transistor transitions from the ON state to the OFF state, or when the transistor transitions from the OFF state to the ON state is as follows.

In FIG. 16, when the gain is switched, the parasitic capacitance Cp changes according to the equation (4), so that the peak frequency of the transmission output power changes according to the equation (1). Therefore, when the transistors are turned off one by one in order to reduce the circuit gain shown in FIG. 16, ΣCP _n becomes small, and the transmission output power peaks as shown in FIGS. The frequency shifts to the high frequency side.

  In the technique according to Patent Document 1, as described above, in the test mode, a built-in or external memory for storing transmission power correction data for each carrier frequency separately acquired is newly required, which increases costs. There is a problem of end.

  Furthermore, since it is necessary to separately provide a test mode for acquiring correction data, there is a problem that the implementation of the control system of the transmission unit becomes complicated.

  An object of the present invention is to provide a technique capable of reducing the fluctuation of the input capacitance value of the input terminal at the time of switching the circuit gain and greatly improving the frequency dependency.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention provides a control unit that outputs a gain adjustment control signal based on a control signal output from a baseband unit, and a signal that is up-converted in a mixer circuit based on the control signal output from the control unit A first amplifier for adjusting the transmission power level, and a signal output from the first amplifier based on a control signal output from the control unit and connected to a subsequent stage of the first amplifier And a second amplifier that adjusts the transmission power level, wherein the first and second amplifiers include a first amplifying transistor having one connecting portion connected to the power supply voltage and the output terminal, and n Each of the amplifying sections, one connecting section of which is connected to the other connecting section of the first amplifying transistor, the other connecting section is connected to the reference potential, and the gate is connected to the input terminal. Contact A bias voltage is supplied to the gate of the second amplifying transistor based on the control signal based on the second amplifying transistor and the control signal output from the control unit; The first switch to be operated, the second switch for stopping the operation of the second amplifying transistor based on the control signal, and one connection portion connected to the gate of the second amplifying transistor, and the control signal And a compensation capacitance element connected between the other connection part of the third switch and the reference potential, and the control part comprises: When the second switch stops the operation of the second amplifying transistor, the third switch is turned on to control the compensation capacitive element.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the present invention, the compensation capacitive element is composed of a MOS capacitor.

  In the present invention, the size of the transistor constituting the compensating capacitance element is about 2/3 of the second amplifying transistor.

  Further, according to the present invention, the compensation capacitance element has a capacitance value such that the input capacitance value at the input terminal is substantially constant when the second switch stops the operation of the second amplification transistor. It is what has.

  According to the present invention, the compensation capacitive element is laid out in the vicinity of the second amplifying transistor.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the fluctuation of the parasitic capacitance value due to gain switching can be greatly reduced, the transmission power can be output with high accuracy and stability.

  (2) The reliability in the semiconductor integrated circuit device for high frequency processing can be improved by the above (1).

It is a block diagram which shows an example of the transmission power control system by one embodiment of this invention. FIG. 2 is a circuit diagram showing an example of a configuration of an amplifier of a semiconductor integrated circuit device that constitutes the transmission power control system of FIG. 1. It is explanatory drawing which shows the example of a combination of the structure of the switch and electrostatic capacitance element in the first stage amplification unit provided in the amplifier of FIG. FIG. 3 is an explanatory diagram illustrating an example of switch timing at the time of gain switching in the amplifier of FIG. 2. It is explanatory drawing which showed an example of the frequency characteristic of the transmission output power output from the output terminal in the amplifier of FIG. FIG. 3 is an explanatory diagram illustrating an example of frequency characteristics of difference values before and after gain switching in the amplifier of FIG. 2. It is explanatory drawing which showed an example of the frequency characteristic of the transmission power gain adjustment value obtained from the transmission power control system of FIG. FIG. 3 is an explanatory diagram showing an example of a partial layout in the amplifier of FIG. 2. It is explanatory drawing which shows an example of the AB cross section of FIG. It is explanatory drawing which showed the application example of the amplifier of FIG. It is a block diagram which shows the structural example of the driver part used for the transmitter of the semiconductor integrated circuit device which this inventor examined. FIG. 12 is a circuit diagram illustrating an example of the driver amplifier of FIG. 11. FIG. 13 is an explanatory diagram illustrating an example of switch timing at the time of gain switching in the driver amplifier of FIG. 12. It is explanatory drawing which showed the frequency characteristic of the transmission output power of the output terminal OUT when gain switching is implemented in FIG. It is explanatory drawing which shows the frequency characteristic of the transmission output power adjustment value at the time of performing power control of the driver amplifier of FIG. FIG. 13 is a circuit diagram when a parasitic capacitance of a transistor is taken into consideration in the driver amplifier of FIG. 12.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of a transmission power control system according to an embodiment of the present invention, and FIG. 2 is a circuit showing an example of a configuration of an amplifier of a semiconductor integrated circuit device constituting the transmission power control system of FIG. FIGS. 3 and 3 are explanatory diagrams showing examples of combinations of configurations of switches and capacitance elements in the first-stage amplification unit provided in the amplifier of FIG. 2, and FIG. 4 is a diagram illustrating gain switching in the amplifier of FIG. FIG. 5 is an explanatory diagram showing an example of switch timing, FIG. 5 is an explanatory diagram showing an example of frequency characteristics of transmission output power output from the output terminal in the amplifier of FIG. 2, and FIG. 6 is a diagram before and after gain switching in the amplifier of FIG. FIG. 7 shows an example of the frequency characteristic of the transmission power gain adjustment value obtained from the transmission power control system of FIG. FIG. 8 is an explanatory diagram showing an example of a partial layout in the amplifier of FIG. 2, FIG. 9 is an explanatory diagram showing an example of a cross section taken along line AB of FIG. 8, and FIG. 10 is an application of the amplifier of FIG. It is explanatory drawing which showed the example.

  In the present embodiment, the transmission power control system 1 is provided, for example, in a radio communication system used for inter-vehicle communication and controls output power at the time of transmitting a radio signal.

  As shown in FIG. 1, the transmission power control system 1 includes a baseband IC 2 that is a baseband unit, a semiconductor integrated circuit device 3, and the like. The baseband IC 2 performs conversion of transmission data into an I signal and a Q signal, output of a control signal CC, control of the semiconductor integrated circuit device 3, and the like. The baseband IC 2 and the semiconductor integrated circuit device 3 are respectively formed on different semiconductor chips.

  The baseband IC 2 includes a digital baseband unit (DBB) 4, a D / A converter 5, a logic controller 6, and the like. The semiconductor integrated circuit device 3 includes a logic controller 7 as a control unit, a low-pass filter 8, a gain control amplifier 9, an I / Q mixer 10, an I / Q phase generator 11, an adder 13, a VCO / synthesizer 14, An amplifier 15 serving as one amplifier and an amplifier 16 serving as a second amplifier are provided.

  The baseband IC 2 creates digital baseband signal data in the digital baseband unit 4, converts the digital baseband signal data into an analog baseband signal by the D / A converter 5, and sends it to the semiconductor integrated circuit device 3. . The logic controller 6 is used as an interface with the logic controller 7 of the semiconductor integrated circuit device 3.

  The semiconductor integrated circuit device 3 mainly performs up-conversion of the analog baseband signal output from the baseband IC 2 to the RF signal band and adjustment of the transmission output power level.

  The alias signal is removed from the baseband signal output from the baseband IC 2 by the low-pass filter 8, and the I / Q modulation and up-conversion (5.9 GHz) to the RF signal band is performed by the I / Q mixer 10 at the subsequent stage. I do.

  The up-converted signal is amplified to a desired transmission power by subsequent amplifiers 15 and 16. For mixer amplifier conversion, the oscillation signal of about 11.8 GHz generated by the VCO / synthesizer 14 is divided by the I / Q face generator 11 (11.8 GHz → 5.9 GHz) and the I / Q signal is converted. Generated and supplied to the I / Q mixer 10 as I / Q local signals (LO_I, LO_Q).

  In order to control the transmission power, a control signal from the baseband IC 2 is output from the logic controller 6 to the logic controller 7 of the semiconductor integrated circuit device 3, and an amplifier according to the power control decoder provided in the semiconductor integrated circuit device 3 Switches the gain between 15 and 16.

  FIG. 2 is a circuit diagram showing an example of the configuration of the amplifier 15 of the semiconductor integrated circuit device 3. Although FIG. 2 shows a configuration example of the amplifier 15, the amplifier 16 has the same configuration as that of FIG.

As illustrated, the amplifier 15 includes an inductor 17, a transistor 18 that is a first amplifying transistor, transistors 19 _{0 to} 19 _N that are second amplifying transistors, resistors 20 _{0 to} 20 _N , and a capacitance element 21. _{0 to} 21 _N , second switches 22 _{0 to} 22 _N , first switches 23 ₀ to 23 _N , third switches 24 _{0 to} 24 _N , and compensation capacitance Capacitance elements 25 _{0 to} 25 _{N serving as} elements are formed. Further, the switches 22 _{0 to} 22 _N , 23 ₀ to 23 _N , 24 _{0 to} 24 _N are composed of N channel MOS transistors, for example.

  One connection portion of the inductor 17 is connected so that the power supply voltage VDD is supplied, and one connection portion of the transistor 18 is connected to the other connection portion of the inductor 17. Further, a connection portion between the inductor 17 and the transistor 18 is an output terminal OUT of the amplifier 15.

The other end of the transistor 18, one end of the transistor 19 ₀ and is connected to the gate of the transistor 18, the bias voltage BIAS is connected to be supplied.

The one connection portion of the capacitive element 21 ₀ is connected with an input terminal IN of the amplifier 15, to the other connecting part of the electrostatic capacitance element 21 ₀ While the connection portion of the resistor 20 _0, transistor 19 ₀ gate, and one of connection portions of the switch 24 ₀ is connected.

One connection portion of the switches 22 ₀ and 23 ₀ is connected to the other connection portion of the resistor 20 ₀ . The other end of the transistor 19 _0, and the other connection portion of the switch 22 _0, the reference potential VSS is connected.

To the other connecting part of the switch 23 _0, the gate bias voltage VB is connected. To the other connecting part of the switch 24 _0, one connection portion of the capacitive element 25 ₀ is connected to the other connecting part of the electrostatic capacitance element 25 _0, the reference potential VSS is connected Yes.

The control terminal of the switch 22 _0, 24 _0, are respectively connected to control signal Ctrl0 is input to the control terminal of the switch 23 _0, is connected to the control signal CtrlB0 is input Yes.

These transistors 19 _0, resistors 20 _0, the capacitance elements 21 _0, the switch 22 _0, switch 23 _0, switch 24 _0, and the amplification unit 15 ₁ is constituted by capacitive elements 25 _0.

Amplifier 15 is made from those constituting the N number of amplifying units 15 ₁ to 15 _N in N stages, the following, configuration of the amplifier unit 15 ₂ to 15 _N, and the connection is the same as the amplifier unit 15 _1.

For example, the amplification unit 15 ₂ includes a transistor 19 ₁ , a resistor 20 ₁ , a capacitance element 21 ₁ , a switch 22 ₁ , a switch 23 ₁ , a switch 24 ₁ , and a capacitance element 25 ₁ , and the amplification unit 15 _N. Includes a transistor 19 _N , a resistor 20 _N , a capacitance element 21 _N , a switch 22 _N , a switch 23 _N , a switch 24 _N , and a capacitance element 25 _N.

As described above, the amplifier 15 has the configuration of FIG. 12 described in the background art, and the switches 24 _{0 to} 24 _N and the capacitance elements 25 _{0 to} 25 _N for frequency characteristic compensation are transistors 19 ₀ for amplification. in conjunction with ~ 19 _N has a configuration obtained by adding the respective amplifying units 15 ₁ to 15 _N.

Also, the amplification unit 15 _1, the switch 22 _0, 23 _0, 24 _0, and with respect to the electrostatic capacitance element 25 _0, when the transistor 19 ₀ is OFF, since it is when the amplifier 15 is shut down, the gain switching Is not necessarily required because is considered to be not directly related.

However, in order to maintain the symmetry of the circuit layout, as shown in FIG. 3, the amplifier unit 15 ₁ of the first stage, the switch 22 _0, 23 _0, there is no one and 24 ₀ and the capacitance element 25 ₀ configuration (A), the switch 22 _0, 23 _0, configuration 24 ₀ capacitance element 25 ₀ without is provided (configuration B), or the switch 22 _0, 23 _0, 24 ₀ and the capacitance element 25 ₀ and it is conceivable that patterns such as configuration (C) are both provided.

  The circuit operation will be described below based on the configuration A in FIG.

FIG. 4 is an explanatory diagram showing ON / OFF timings of the switches 22 _{0 to} 22 _N , 23 ₀ to 23 _N , and 24 _{0 to} 24 _N for gain switching in FIG.

The ON / OFF operation control in these switches 22 ( ₀ to _N ), 23 ( ₀ to _N ), and 24 ( ₀ to _N ) is performed by control signals Ctrl0 to Ctrln, CtrlB0 to CtrlB0 output from the logic controller 7 (FIG. 1). Each is controlled by CtrlBn. In this case, the control timing of the switches 22 ( ₀ to _N ) and 23 ( ₀ to _N ) is the same as that in FIG. 13, but the switch 24 ( ₀ to _N ) is the switch 22 as shown in FIG. ON / OFF operation is performed at the same timing as ( ₀ to _N ).

When the transistor 24 ( ₀ to _N ) is in the bias-off state, the capacitance element 25 ( ₀ to _N ) becomes effective, so that the input capacitance value Cin viewed from the input terminal IN when the circuit gain is switched is It does not fluctuate greatly.

Here, the electrostatic capacitance elements 25 _{0 to} 25 _N are composed of, for example, MOS capacitors. By using MOS capacitors for the capacitance elements 25 _{0 to} 25 _N , the area efficiency can be improved and the device mismatch with the MOS transistors constituting the transistors 19 _{0 to} 19 _N can be reduced.

  In general, in a state where a MOS capacitor gate is biased and a channel is formed under the gate, the capacitance value viewed from the gate end is as follows.

Here, W is the gate width of the MOS capacitor, L is the gate length of the MOS capacitor, C _OX is the oxide film capacitance, and C _OV is the overlap unit capacitance between the gate and drain and between the source and drain. Here, regarding the relationship between the first term determined by the oxide film capacity and the second term determined by the overlap capacity in Equation (5), the first term is sufficiently large and the second term can be almost ignored.

The size of the gate width W / gate length L of the MOS capacitors used for the capacitance elements 25 _{0 to} 25 _N shown in FIG. 2 depends on the relationship between the equations (4) and (5). If C _OX is sufficiently larger than the overlap C _OV , the gate width W / gate length L of the transistors 19 _{0 to} 19 _N is 3/2.

Now, _assuming that the gate widths of the transistors 19 _{0 to} 19 _N are W _n , the gate length is L _n , the gate widths of the capacitance elements 25 _{0 to} 25 _N are Wc _n , and the gate length is Lc _n , Thus, the size of W / L is determined.

When the switch 24 ₍₀ ~ _N) is enabled, the gate of the electrostatic capacitance element 25 ₍₀ ~ _N), since the bias voltage is applied, the channel under the gate of the electrostatic capacitance element 25 ₍₀ ~ _N) is The capacitance value at this time can be expressed by the equation shown in equation (5).

On the other hand, when the switch 24 ( ₀ to _N ) transitions from ON to OFF, the changing capacitance value of the transistors 19 _{0 to} 19 _N is expressed by Equation (4). At this time, when the overlap capacitance C _ov in the equation (5) is sufficiently smaller than the oxide film capacitance C _ox , the frequency characteristic is compensated by setting the size of the MOS capacitance (electrostatic element 25) to 2/3. Is possible.

  FIG. 5 is an explanatory diagram showing an example of frequency characteristics of the transmission output power output from the output terminal OUT in the amplifier 15 of FIG.

  In this case, as shown in FIG. 5, unlike the frequency characteristic diagram of FIG. 14, it can be seen that the peak of the transmission power hardly fluctuates due to gain switching. Further, FIG. 6 shows the frequency characteristics of the difference values before and after the gain switching as in FIG. Also in FIG. 6, it can be seen that there is almost no change depending on the frequency.

  Therefore, it is possible to reduce the frequency dependence of the gain switching value by making the input capacitance value Cin constant or reducing its fluctuation.

  FIG. 7 is an explanatory diagram showing an example of the frequency characteristic of the transmission power gain adjustment value obtained from the transmission power control system 1 of FIG. As can be seen from FIG. 7, even if the gains of the amplifiers 15 and 16 serving as transmission drivers are switched, the adjustment value has almost no frequency dependence, and high-accuracy power adjustment can be expected.

FIG. 8 is an explanatory diagram showing an example of a partial layout of FIG. 8, layout examples of the transistors 19 ₀ , 19 ₁ , the capacitive element 25 ₁ , the switches 22 ₀ , 23 ₀ , 22 ₁ , 23 ₁ , 24 ₁ , and the resistors 20 ₀ , 20 ₁ of FIG. It shall be shown.

The upper left of FIG. 8, the transistor 19 ₁ are laid on the right side of the transistor 19 _1, transistor 19 ₀ is laid. Under the transistors 19 ₁ and 19 ₀ , a ground wiring GND formed in the first wiring layer and connected to the reference potential VSS is laid out.

Across the ground line GND, the lower transistor 19 _1, from left to right, the electrostatic capacitance element 25 _1, and has switches 24 ₁ is laid respectively, the lower the switch 24 _1, the resistance 20 ₁ Is laid out.

Then, the downwardly resistor 20 _1, and the switch 23 ₁ is laid on the right side of the switch 23 _1, the switch 23 ₀ is laid. Below the switch 23 _0, the switch 22 ₀ is laid. Switch 22 ₁ is laid on the left side of the switch 22 _0. Further, a resistor 20 ₀ is laid out above the switch 23 ₀ .

A ground wiring GND formed in the first wiring layer is connected to _one source / drain terminal of the transistors 19 ₁ and 19 ₀ and the other connection portion of the capacitance element 25 ₁ , respectively.

The other of the source / drain terminal of the transistor 19 _1, 19 ₀ are respectively connected to metal interconnect H1 of the transistor 19 _1, 19 ₀ second wiring layer formed above the.

The transistor 19 ₁ of the gate, the transistor 19 ₀ gate, one connection portion of the switch 24 _1, and the one connection portion of the resistor 20 _1, the metal wiring H2 formed in the third wiring layer are connected ing.

Other connection portion of the resistor 20 _1, one connection portion of the switch 23 _1, and to the other connection of the switch 22 _1, the metal wiring H3 formed in the third wiring layer are connected respectively, electrostatic The metal wiring H3 formed in the third wiring layer is connected to _one connection portion of the capacitive element 25 _{1 and} the other connection portion of the switch 24 ₁ .

A bias voltage VB is supplied to the other connection portion of the switch 23 ₁ through a metal wiring H5 formed in the third wiring layer. The transistor 19 ₀ gate, and the one connection portion of the resistor 20 _0, the metal wiring H6-formed in the third wiring layer are connected.

Other connection portion of the resistor 20 _0, one connection portion of the switch 23 _0, as well as one connection of the switch 22 _0, the metal wiring H7 formed in the third wiring layer are connected, the switch 23 _The bias voltage VB is supplied to the other connection portion of ₀ through the metal wiring H8 formed in the third wiring layer.

The control signal CtrlB1 is input to the control terminal of the switch 23 ₁ through the metal wiring H9 formed in the fourth wiring layer. The control signal Ctrl1 is input to the control terminal of the switch 22 ₁ via the metal wiring H10 formed in the fourth wiring layer, and the metal wiring H13 formed in the fourth wiring layer is input to the control terminal of the switch 24 _1. The control signal Ctrl1 is input via the.

Similarly, the control terminal of the switch 23 _0, the control signal CtrlB0 through the metal wiring H11 formed in the fourth wiring layer is input to the control terminal of the switch 22 _0, which is formed on the fourth wiring layer A control signal Ctrl0 is input through the metal wiring H12. The other connecting part of the switch 22 _1, and the other connection portion of the switch 22 _0, the ground line GND are connected.

Thus, by arranging the capacitance element 25 ₀ (, 25 _{1 to} 25 _N ) and the transistor 19 ₀ (, 19 _{1 to} 19 _N ) close to each other, the wiring resistance is reduced as much as possible, and the electrical characteristics of the MOS The layout is made so that there is no big difference.

  Moreover, FIG. 9 is explanatory drawing which shows an example of the AB cross section of FIG.

9, in the center of the P-type semiconductor substrate 26, an insulating film 27 made of an element isolation region is formed, a transistor 19 ₀ located in the transistor 19 ₁ and the right side on the left side is separated It has a structure.

In the transistor 19 ₁ , semiconductor regions 28 to 31 of an N-type diffusion layer functioning as a source / drain are formed at arbitrary intervals from the left side to the right side, and between the semiconductor region 28 and the semiconductor region 29, Gates 32, 33 and 34 are formed above the semiconductor region 29 and the semiconductor region 30 and above the semiconductor region 29 and the semiconductor region 30.

  The semiconductor regions 28 and 30 are connected to the first layer metal wirings 37 and 38 through the through holes 35 and 36, respectively. The semiconductor regions 29 and 31 are the through holes 39 and 40, the first layer metal wirings. 41 and 42 and through-holes 43 and 44, respectively, are connected to the second level metal wirings 45 and 46, respectively.

  The gates 32 to 34 are connected to the third-layer metal wiring 50 via through holes 47 to 49, respectively. Note that the through holes 47 to 49 and the metal wiring 50 are not actually formed on the AB cross section of FIG. 8 but are shifted from the AB cross section (A- of FIG. 8). (Above the B section), it is indicated by a dotted line in the drawing.

Also in transistor 19 ₀ positioned on the right side, the semiconductor region of the N-type diffusion layer serving as a source / drain 51 to 54, consists of the gate 55, 56, 57, made of the same cross section as the transistor 19 _1.

  The semiconductor regions 51 and 53 are connected to the first layer metal wirings 60 and 61 through the through holes 58 and 59, respectively. The semiconductor regions 52 and 54 are connected to the through holes 62 and 63 and the first layer metal wirings. 64 and 65 and through-holes 66 and 67, respectively, are connected to the second level metal wirings 68 and 69, respectively. The gates 55 to 57 are connected to the third-layer metal wiring 73 through through holes 70 to 72, respectively.

  Note that the through holes 47 to 49 and 70 to 72 and the metal wirings 50 and 73 are not actually formed on the AB cross section of FIG. 8, but are shifted from the AB cross section. Since it is formed (above the AB cross section in FIG. 8), it is indicated by a dotted line in the drawing.

  FIG. 10 is an explanatory diagram showing an application example of the amplifier 15 (16) of FIG.

  In this case, the amplifier 15 (, 16) has a pseudo differential amplifier configuration using two amplifiers shown in FIG.

In FIG. 10, an amplifier 15 (, 16) includes an inductor 17, a transistor 18, transistors 19 _{0 to} 19 _N , resistors 20 _{0 to} 20 _N , capacitance elements 21 _{0 to} 21 _N , switches 22 _{0 to} 22 _N , switches 23 ₀ ~ 23 _N, a first amplifying part consisting of the switch 24 ₀ to 24 _N, and the electrostatic capacitance element 25 ₀ to 25 _N, the inductor 17a, the transistor 18a, the transistor 19a ₀ through 19a _N, resistors 20a ₀ through 20a _N , Capacitance elements 21a _{0 to} 21a _N , switches 22a _{0 to} 22a _N , switches 23a _{0 to} 23a _N , switches 24a _{0 to} 24a _N , and second amplifying units composed of capacitance elements 25a _{0 to} 25a _N. Become.

  The connection configuration of the first amplification unit is the same as that in FIG. 2, and the connection configuration of the second amplification unit is the same as that of the first amplification unit. The input terminal of the first amplifying unit is INX, the output terminal is OUTX, the input terminal of the second amplifying unit is INY, and the output terminal is OUTY.

  Then, RF signals are respectively input from the input terminals INX and INY that are differential inputs, and the differential output signals are output from the output terminals OUTX and OUTY that are differential outputs.

In this case, the circuit gain becomes maximum when the transistors 19 _{0 to} 19 _N and 19a _{0 to} 19a _N which are common source MOSs are operating in a saturated state. Further, the amplifier 15 of FIG. 10 (16), the switch _{24 0 ~24 N, 24a 0 ~24a} N, and capacitive element 25 ₀ to 25 _N, since the provided respectively 25a ₀ ~25a _N, amplifier It is possible to correct the influence of the parasitic capacitance generated when the transistors 19 _{0 to} 19 _N and 19a _{0 to} 19a _N are turned on / off in order to switch the circuit gain of 15 (, 16), thereby improving the frequency dependency. it can.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a technique for adjusting transmission power over a wide range and with high accuracy in wireless communication.

1 Transmission power control system 2 Baseband IC
3 Semiconductor Integrated Circuit Device 4 Digital Baseband Unit 5 D / A Converter 6 Logic Controller 7 Logic Controller 8 Low Pass Filter 9 Gain Control Amplifier 10 I / Q Mixer 11 I / Q Face Generator 13 Adder 14 VCO / Synthesizer 15 Amplifier 15 ₁ to 15 _N amplification unit 16 amplifier 17 inductor 17a inductor 18 transistor 18a transistor 19 _{0 to} 19 _N transistor 20 _{0 to} 20 _N resistor 21 _{0 to} 21 _N capacitance element 22 _{0 to} 22 _N switch 23 ₀ to 23 _N switch 24 _{0 to} 24 _N switch 25 _{0 to} 25 _N capacitance element 26 P-type semiconductor substrate 27 Insulating films 28 to 31 Semiconductor regions 32 to 34 Gate 35 Through hole 36 Through hole 37 Metal wiring 38 Metal wiring 39, 40 Through hole 41, 42 Metal wiring 43, 44 Through hole 45, 46 Metal wiring 47-49 Through hole 50 Metal wiring 51-54 Semiconductor region 55-57 Gate 58, 59 Through hole 60, 61 Metal wiring 62, 63 Through hole 64, 65 Metal wiring 66 , 67 Through hole 68, 69 Metal wiring 70-72 Through hole 73 Metal wiring H1-H13 Metal wiring 100 Driver unit 101, 102 Driver amplifier LD Inductor MCAS Transistor M0-Mn Transistor R0-Rn Resistance C0-Cn Capacitance element SWa0 ~ SWan switch SWb0-SWbn switch

Claims (5)

A control unit that outputs a gain adjustment control signal based on a control signal output from the baseband unit;
A first amplifier that amplifies the signal up-converted in the mixer circuit and adjusts the transmission power level based on the control signal output from the control unit;
A second amplifier connected to a subsequent stage of the first amplifier and amplifying a signal output from the first amplifier based on a control signal output from the control unit and adjusting a transmission power level; Prepared,
The first and second amplifiers are:
A first amplifying transistor having one connecting portion connected to the power supply voltage and the output terminal;
each including n amplification units,
The amplification unit is
A second amplifying transistor having one connecting portion connected to the other connecting portion of the first amplifying transistor, the other connecting portion connected to a reference potential, and a gate connected to the input terminal;
A first switch for supplying a bias voltage to the gate of the second amplifying transistor based on a control signal output from the control unit, and operating the second amplifying transistor;
A second switch for stopping the operation of the second amplifying transistor based on a control signal output from the control unit;
A third switch having one connecting portion connected to the gate of the second amplifying transistor, and switching on / off based on a control signal output from the control portion;
A compensation capacitance element connected between the other connection portion of the third switch and a reference potential;
The controller is
When the second switch stops the operation of the second amplifying transistor, the third switch is turned on to control the compensation capacitance element to be effective. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1.
2. The semiconductor integrated circuit device according to claim 1, wherein the compensation capacitance element is composed of a MOS capacitor. The semiconductor integrated circuit device according to claim 1 or 2,
2. A semiconductor integrated circuit device according to claim 1, wherein a size of a transistor constituting the compensating capacitance element is about 2/3 of the second amplifying transistor. The semiconductor integrated circuit device according to any one of claims 1 to 3,
The compensation capacitance element is:
A semiconductor integrated circuit device having a capacitance value such that an input capacitance value at the input terminal becomes substantially constant when the second switch stops the operation of the second amplification transistor. The semiconductor integrated circuit device according to any one of claims 1 to 4,
2. The semiconductor integrated circuit device according to claim 1, wherein the compensation capacitance element is laid out in the vicinity of the second amplification transistor.

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