JP2011114299A - Graphene transistor - Google Patents

Abstract

The present invention provides a graphene transistor having a large gate capacity, which has not been obtained conventionally, and a method for manufacturing the same.
In order to solve the above problems, a graphene transistor is a graphene transistor in which an insulating film is disposed between graphene and a low-resistance substrate, and the entire insulating film is configured with a homogeneous composition, and the ratio thereof The dielectric constant is 4 or more, the basic element of the insulating film is different from the basic element of the substrate, and the insulating film has a thickness having an interference contrast in the visible light region where graphene can be observed with an optical microscope. A means characterized by being adopted.
[Selection] Figure 1

Description

  The present invention relates to a graphene transistor in which an insulating film is provided between graphene and a low resistance substrate.

Graphene having a sheet structure of one atomic layer in which carbon atoms are arranged in a honeycomb shape has attracted attention as a channel material candidate for a transistor because of its high mobility.
A conventional transistor uses low-resistance Si doped with a high concentration of dopant as a substrate, and uses SiO ₂ as an insulating film (FIG. 1). The purpose of this graphene / SiO ₂ / low resistance Si substrate structure is to control the electron or hole concentration in the graphene by applying an electric field to the graphene via the SiO ₂ from the substrate Si side. The principle is, two-dimensional electron concentration in the graphene (n) or 2-dimensional hole concentration (p) is SiO ₂ capacitance _{C SiO2 (= ε SiO2 · ε} 0 / d) and the applied voltage V and the elementary charge Since it is equal to the product of the reciprocal 1 / q, n or p can be varied in proportion to the gate voltage. Here, ε _SiO2 is the relative dielectric constant of SiO ₂ , ε ₀ is the vacuum dielectric constant, and d is the SiO ₂ film thickness. However, the value of epsilon _SiO2 small as about 3.9, there is a disadvantage that a large gate voltage is required to control the electron-hole concentration of 1 digit or more.
In order to efficiently control the carrier concentration in graphene as a transistor, it is necessary to increase the gate capacitance _Cg . Since the gate capacitance _{C g = ε SiO2 × ε 0} / d SiO2 (ε SiO2 dielectric constant of SiO _2, epsilon ₀ is the vacuum dielectric _{constant, d SiO2} indicates the thickness of SiO ₂₎ is given by, SiO _{Although the} thickness d _{2 SiO 2} was made as thin as possible, it was impossible to increase the relative dielectric constant.
Since the film thickness naturally has a limit, it has been desired to increase the relative dielectric constant in order to obtain a larger gate capacitance.

  In view of such circumstances, the present invention provides a graphene transistor having a large gate capacity, which has not been obtained in the past, and a method for manufacturing the same.

The graphene transistor of the invention 1 is a graphene transistor in which an insulating film is arranged between graphene and a low-resistance substrate, and the insulating film as a whole has a homogeneous composition and has a relative dielectric constant of 4 or more. Features.
Invention 2 is characterized in that, in the graphene transistor of Invention 1, the basic element of the insulating film is different from the basic element of the substrate.
A third aspect of the present invention is the graphene transistor of the first or second aspect, wherein the insulating film has a thickness having an interference contrast in a visible light region where the graphene can be observed with an optical microscope.

  Unlike a natural oxide film, since the film quality and film thickness can be controlled, there is an advantage that an insulating film can be formed with good reproducibility. Further, according to the invention 3, a transistor having characteristics such that graphene can be observed with an optical microscope when an element is manufactured can be provided.

Schematic diagram of a top contact / bottom gate graphene transistor structure. The conventional structure uses SiO ₂ as an insulating layer. Example 1 has a structure in which a high dielectric layer (relative dielectric constant of 4 or more) is formed between graphene and a substrate. Intensity distribution diagram of contrast for the Al ₂ O ₃ film thickness and the wavelength. (A) Structural drawing. n is a refractive index. (B) Contrast intensity distribution diagram. The intensity increases from black to white. FIG. 3 is a schematic diagram of an element manufacturing process of Example 1. (A) Highly doped Si substrate. (B) An Al ₂ O ₃ thin film formed by an atomic layer deposition apparatus. (C) Graphene transfer. (D) Graphene etching. (E) Preparation of source / drain electrodes. FIG. 3 is a timing diagram of gas injection in the atomic layer deposition apparatus according to the first embodiment. _{2 is} an optical microscope image of a graphene transistor produced on the Al ₂ O ₃ thin film of Example 1. FIG. Graphene is processed into a hole bar shape and connected to a Ti / Au electrode. The rate of change in conductivity with respect to the change in gate voltage between Example 1 and the conventional SiO ₂ insulating layer. It shows that Al ₂ O _{3 has} a higher rate of change than SiO ₂ . Intensity distribution diagram of the contrast with respect to the HfO ₂ film thickness and wavelength. (A) Structural drawing. n is a refractive index. (B) Contrast intensity distribution diagram. The intensity increases from black to white.

The present invention provides a technique for solving the above drawbacks by using a dielectric thin film (high dielectric thin film or ferroelectric thin film) having a high dielectric constant larger than that of SiO ₂ . That is, a wide range of electron / hole (carrier) concentrations can be controlled even with a gate voltage lower than that of SiO ₂ .
In the example, it was shown that the carrier concentration in the graphene can be largely controlled by using Al ₂ O ₃ as the insulating film and having a higher dielectric constant. For reference, Tables 1 and 2 show the calculated gate capacitance values for various dielectrics.
It is presumed that high dielectric materials other than Al ₂ O ₃ (Si ₃ N ₄ , HfO ₂ , SrTiO ₃ , BaTiO ₃ , PbZrTiO ₃ ) are also effective for controlling the carrier concentration in graphene. In principle, the larger the relative dielectric constant, the higher the concentration of electrons or holes in graphene can be controlled. For example, when HfO ₂ is considered, the contrast can be calculated as shown in FIG. It can be seen that the thickness can be reduced to 70 nm. In addition, since the dielectric constant is about 6 times that of SiO ₂ (about 3 times that of Al ₂ O ₃ ), the charge induced by the gate voltage from C = εS / d (C: capacitance S: area, d: film thickness) is It is expected to be about 8 times (about 3 times that of Al ₂ O ₃ ).

In the embodiment, one kind of high dielectric material is used as the insulating film, but it is also possible to form an insulating film by laminating several high dielectric materials.
For example, an insulating film can be stacked such as an Al ₂ O ₃ / HfO ₂ / Si substrate, and a specific example thereof is described in Example 2.

In the examples, quiche graphite was used when taking out graphene. However, if graphene has a multilayer structure such as natural graphite or HOPG (Highly Oriented Pyrolytic Graphite), it can be taken out in the same manner. . In addition to the mechanical cleavage method, graphene grown by CVD (Chemical Vapor Deposition) or the like may be used.
Furthermore, in the examples, diatomic graphene is used, but the number of layers is not limited and can be used as a channel material from a single layer to a multilayer or even graphite.

In the examples, the atomic layer deposition method is used for the film formation of Al ₂ O _3. However, as described above, a conventionally known film formation method such as a vacuum evaporation method, a sputtering method, or a CVD method can be used. And may be appropriately selected depending on the material used.

In the examples, chemical reactive etching using O ₂ was used for etching graphene. However, since graphene is a single atomic layer, it can be easily etched by a physical method using Ar, and therefore physical etching using Ar is used. You may do it. An etching effect can also be obtained with a mixed gas of Ar and oxygen. Etching by FIB (Focused Ion Beam) may be used.

In the embodiment, Ti / Au is used as the source / drain electrode material. However, other known metals (Ni, Cr, Pt, Cu, Al, Ag, Pd, ITO or the like) , A structure in which a plurality of such layers are stacked) has no difficulty.
In the example, Ar + 3% H ₂ was used as the annealing gas. However, Non-Patent Document 3 shows that the function as the annealing gas is not impaired regardless of how the mixing ratio of H ₂ changes. From the above facts, it is clear (the etching is performed using a mixed gas having a different ratio of Ar and H ₂ , so that the ratio of Ar is considered to be no problem), so H ₂ alone may be used. For the same reason, any mixed gas of an inert gas and H ₂ may be used. For example, a mixed gas of N ₂ and H ₂ can be used.

FIG. 1 shows a top contact / bottom gate type field effect transistor structure using graphene or graphite as a channel.
In this example, Al ₂ O ₃ was selected as an insulating film 2.2 times larger than the relative dielectric constant 3.9 of SiO ₂ , and an element using a graphene / Al ₂ O ₃ / low resistance Si substrate structure was selected. Produced. The manufacturing method is shown below, and the characteristics of the device using the high dielectric material are shown by comparing the characteristics with the SiO ₂ (thickness 90 nm) device.
When Si is used as the substrate and Al ₂ O ₃ is used as the insulating film, the calculation formula (Formula 1) of Non-Patent Document 1 is used as shown in FIG. It can be seen that the strongest and the thinnest condition of the Al ₂ O ₃ film is about 80 nm.
<Formula 1>

An Al ₂ O ₃ thin film is formed by using an atomic layer deposition apparatus on a low resistance Si substrate having a thickness of 380 μm and a resistivity of 0.02 Ω · cm or less, and good quality Al ₂ O ₃ with excellent in-plane uniformity. A thin film having a thickness of 80 nm was formed (FIG. 3B).
Liquid TMA (trimethylaluminum) and H ₂ O kept at room temperature were used as raw materials, and TMA and H ₂ O were supplied to the growth chamber by bubbling nitrogen gas as a carrier gas.
TMA and H ₂ O were supplied intermittently (pulsed) each independently for 0.1 second and alternately with a waiting time of 4 seconds (FIG. 4). In one cycle, an Al ₂ O ₃ layer is formed as a single molecular layer (about 0.1 nm). The film forming conditions are as follows. Nitrogen gas flow rate: chamber line (300 sccm) / TMA line (150 sccm) / H ₂ O line (150 sccm), raw material temperature: TMA (room temperature) / H ₂ O (room temperature), substrate temperature: 300 ° C., number of pulse cycles: 800 Cycle (80 nm), substrate: low resistance Si substrate.

The insulating film thus obtained is composed only of Al ₂ O ₃ , and the presence of Al alone or aluminum oxide having another structure is not recognized.
Non-patent document 9 shows that 1 molecule of Al ₂ O ₃ can be deposited in 1 cycle. Experimentally, non-patent document 10 shows data supporting the film formation mechanism of Al ₂ O _3. Based on conventionally known technical information, it was determined as described above.

Next, a thin film obtained by attaching quiche graphite to an adhesive tape was transferred onto Al ₂ O ₃ on which the film was formed (FIG. 3C).
The number of graphene layers was determined by optical microscope observation and Raman scattering spectroscopy, and in this case, it was found that the graphene was a diatomic graphene having a structure in which two layers of graphene were stacked. In order to process diatomic graphene into an arbitrary shape, after patterning the resist into a hole bar shape using electron beam lithography, the reactive ion etching apparatus is used to etch the graphene using the resist as a mask (FIG. 3). (D)).
Etching conditions for graphene are: apparatus: reactive ion etching apparatus, etching gas: O ₂ , pressure during etching: 10 Pa, microwave power: 100 W, etching time: 15 sec. Further, source and drain electrodes were formed using laser lithography and electron beam lithography (FIG. 3E), and a top contact / bottom gate type field effect transistor structure was fabricated (FIG. 5). The metal electrode was formed into a film of Ti / Au = 10 nm / 50 nm using a vacuum deposition apparatus. Finally, annealing treatment was performed to remove residual impurities such as resist. The annealing conditions are gas: Ar + 3% H ₂ , gas flow rate: 1 L / min, annealing temperature: 300 ° C., and annealing time: 5 min.

FIG. 6 shows the gate voltage dependence of the conductivity obtained from the drain current flowing in the diatomic graphene on the Al ₂ O ₃ film, and the experimental value when formed on the SiO ₂ film is also shown for comparison. It is shown.
Here, the value of the conductivity is _{normalized by} the conductivity at zero time of the gate voltage V _g -V _dirac (referred to as Dirac point). On both the Al ₂ O ₃ film and the SiO ₂ film, the absolute value of the gate voltage is increased and the conductivity is increased. Bipolarity due to electrons at the positive gate voltage and holes at the negative gate voltage characteristic of graphene It shows sexual conduction. When comparing the Al ₂ O ₃ film and the SiO ₂ film, Al ₂ O ₃ has a sharper peak than SiO ₂ , and the sensitivity to the gate voltage change is good and the carrier concentration in graphene is efficiently increased. You can see that it is controlled. As described above, this is because the relative permittivity of the Al ₂ O ₃ film is larger than that of the SiO ₂ film and the capacitance is correspondingly increased. As a result, electrons generated in the graphene on the Al ₂ O ₃ film or positive This is because the holes have a higher concentration for the same gate voltage. Thus, it was shown that the higher the dielectric material, the greater the control of the carrier concentration in graphene.

This example illustrates the formation of an insulating film by stacking.
For example, a method for manufacturing an Al ₂ O ₃ / HfO ₂ / Si substrate is described. In the same way as Al ₂ O ₃ , an atomic layer deposition apparatus is used to form the HfO ₂ thin film, and the in-plane uniformity is obtained on a low resistance Si substrate having a thickness of 380 μm and a resistivity of 0.02 Ω · cm or less. An excellent high-quality HfO ₂ thin film was formed to a thickness of 70 nm.
Solid TEMAHf (tetrakis [ethylmethylamino] hafnium) heated to 130 ° C. and H ₂ O were used as raw materials, and TEMAHf and H ₂ O were supplied to the growth chamber by bubbling nitrogen gas as a carrier gas. .
The supply of TEMAHf and H ₂ O were each intermittently (pulsed) including 0.1 seconds each, alternately including a waiting time of 5 seconds. A single molecular layer (about 0.085 nm) of HfO ₂ layer is formed in one cycle. The film forming conditions are as follows. Nitrogen gas flow rate: chamber line (200 sccm) / TEMAHf line (100 sccm) / H ₂ O line (100 sccm), raw material temperature: TEMAHf (130 ° C.) / H ₂ O (room temperature), substrate temperature: 300 ° C., number of pulse cycles: 825 cycles (70 nm), substrate: low resistance Si substrate.
Subsequently, liquid TMA (trimethylaluminum) and H ₂ O kept at room temperature were used as raw materials, and TMA and H ₂ O were supplied to the growth chamber by bubbling nitrogen gas as a carrier gas.
The supply of TMA and H ₂ O was each intermittently (pulsed) including 0.1 seconds each, alternately including a waiting time of 4 seconds. In one cycle, an Al ₂ O ₃ layer is formed as a single molecular layer (about 0.1 nm). The film forming conditions are as follows. Nitrogen gas flow rate: chamber line (300 sccm) / TMA line (150 sccm) / H ₂ O line (150 sccm), raw material temperature: TMA (room temperature) / H ₂ O (room temperature), substrate temperature: 300 ° C., number of pulse cycles: 20 Cycle (2 nm), substrate: HfO ₂ / low resistance Si substrate.
As described above, any material that can be formed by an atomic layer deposition method can be formed continuously in the same chamber.

JP2007-258223A JP2009-111377A

Applied Physics Letters 91, 063124 (2007). Applied Physics Express 2, 025003 (2009). Nano Letters 7, 1643 (2007). Journal of the Electrochemical Society 127, 2222 (1980). Journal of the Electrochemical Society 119, 945 (1972). Applied Physics Letters 92, 222903 (2008). Japan Journal of Applied Physics 32, 4118 (1993). Electrochemical and Solid-State Letters, 2 (10), 504 (1999). Reference "Surface Science 322, 230 (1995). The Journal of Physical Chemistry 100, 13121 (1996).

Claims (3)

  A graphene transistor having an insulating film disposed between a graphene and a low-resistance substrate, wherein the entire insulating film has a homogeneous composition and a relative dielectric constant of 4 or more.   2. The graphene transistor according to claim 1, wherein a basic element of the insulating film is different from a basic element of the substrate. 3. The graphene transistor according to claim 1, wherein the insulating film has a thickness having an interference contrast in a visible light region where the graphene can be observed with an optical microscope.