JP2011110935A - Capacitive load driving circuit - Google Patents

Abstract

An object of the present invention is to suppress variation in operation among loads while driving a plurality of loads with a single voltage waveform.
Each capacitive load is driven by connecting the output of the voltage waveform output means to a plurality of capacitive loads. Here, when the voltage of the output voltage waveform exceeds the voltage range determined for each capacitive load, the connection of the capacitive load is released, and when the voltage of the voltage waveform returns to the voltage range, the released connection By reconnecting, a different voltage waveform is applied for each capacitive load. In this way, by setting each voltage range according to the characteristics of each capacitive load, an appropriate voltage waveform according to the characteristics of each capacitive load can be applied to each capacitive load. Therefore, it is possible to appropriately operate each capacitive load and suppress the variation in operation between the capacitive loads.
[Selection] Figure 5

Description

  The present invention relates to a technique for driving a capacitive load by applying a voltage.

  A technique for driving a load of an electronic element such as a semiconductor element or a dielectric element by applying a voltage is widely used in various apparatuses. For example, in a fluid ejecting apparatus such as an ink jet printer, a fluid is pushed out and ejected from an ejecting nozzle by applying a voltage to a piezo element that expands and contracts according to the voltage. In a display device such as a liquid crystal display or an organic EL display, an image is displayed by applying a voltage to the liquid crystal to align liquid crystal molecules, or applying a voltage to the organic EL element to emit light. Moreover, not only an electronic element but the technique which drives a load by applying a voltage to various loads, such as a motor and an electromagnet, is also used widely.

  In such a technology for driving a load, the voltage applied to the load is formed into a predetermined waveform and then applied to the load, and the operation of the load is controlled by controlling the voltage waveform (voltage waveform) applied to the load. is doing. In addition, a plurality of loads are also driven. For example, in an ink jet printer, a plurality of ink nozzles are driven to eject a plurality of ink droplets, so that an image can be printed at high speed. When driving a plurality of loads in this way, the plurality of loads to be driven are connected in parallel, and the voltage waveform generated by one voltage waveform generation circuit is applied to each of the loads. Is used (for example, Patent Document 1).

JP 2008-260225 A

  However, when a voltage waveform generated by a single voltage waveform generation circuit is applied to a plurality of loads, there is a problem that the operation of the load varies due to the non-uniform characteristics of the individual loads. It was. For example, in an inkjet printer, it is difficult to completely uniform the nozzle diameter and flow path resistance across a plurality of ejection nozzles, so even if the same voltage waveform is applied, the size of the ejected ink droplets and the ink droplets The speed will vary from spray nozzle to spray nozzle. In general, since it is difficult to make the characteristics of multiple loads completely uniform, the variations in the operation of these loads are not limited to inkjet printers, and voltage waveforms generated by a single voltage waveform generation circuit are applied to multiple loads. This is generally possible with devices that do this. Of course, if a voltage waveform that takes into account the characteristics of each load is generated for each load, variations in operation can be suppressed, but this requires a large number of voltage waveform generation circuits, so the circuit scale is simplified. I can't keep it.

  The present invention has been made in order to solve the above-described problems of the prior art, and the operation of each load is maintained while keeping the circuit scale simple by applying one voltage waveform to a plurality of loads. It is an object of the present invention to provide a technique capable of uniformly operating a plurality of loads while suppressing the variation of the load.

In order to solve at least a part of the problems described above, the capacitive load driving circuit of the present invention employs the following configuration. That is, the capacitive load drive circuit of the present invention is
Voltage waveform output means for outputting a voltage waveform used for driving a plurality of capacitive loads;
Voltage waveform applying means for applying the voltage waveform to each of the plurality of capacitive loads by connecting each of the plurality of capacitive loads to the output of the voltage waveform output means; and
The voltage waveform application means connects the capacitive load and the output of the voltage waveform output means when the voltage waveform voltage is outside the voltage range defined for each of the plurality of capacitive loads. The voltage waveform different from each of the plurality of capacitive loads by connecting the capacitive load to the output of the voltage waveform output means when the voltage waveform voltage is within the voltage range. It is a gist that it is a means for applying.

  In the capacitive load driving circuit of the present invention, each capacitive load is driven by connecting the output of the voltage waveform output means to a plurality of capacitive loads. Here, when the voltage of the voltage waveform output from the voltage waveform output means exceeds the voltage range determined for each capacitive load, the connection between the capacitive load and the voltage waveform output means is released, When the voltage waveform voltage returns to the voltage range, the disconnected connection is reconnected to apply a different voltage waveform for each capacitive load.

  When a voltage is applied, the capacitive load can hold the voltage by accumulating charges therein. Therefore, when the connection between the capacitive load and the output of the voltage waveform output means is released, the capacitive load is not connected. The voltage applied at the time of release is kept as it is. If the capacitive load is reconnected to the output of the voltage waveform output means after the voltage waveform voltage returns to the voltage range, then the voltage waveform output by the voltage waveform output means can be applied to the capacitive load. . As a result, a voltage waveform different from the voltage waveform output by the voltage waveform output means can be applied to each capacitive load. In this way, even when the voltage waveform output from one voltage waveform output means is applied to a plurality of capacitive loads, a different voltage waveform can be applied to each capacitive load. By determining the voltage range of each capacitive load according to the characteristics of the load, it is possible to apply an appropriate voltage waveform according to the characteristics of each capacitive load. As a result, even when the output of one voltage waveform output means is applied to a plurality of capacitive loads, an appropriate voltage waveform corresponding to the characteristics of each capacitive load is applied to operate each capacitive load appropriately. As a result, it is possible to suppress variations in operation between the capacitive loads.

  When disconnecting the capacitive load from the voltage waveform output means, any method can be used as long as the capacitive load is disconnected when the voltage range defined for the capacitive load is exceeded. May be. For example, the voltage of the voltage waveform output by the voltage waveform output means may be measured, and the connection may be released when it is detected that the measured voltage exceeds the voltage range. Alternatively, the timing at which the voltage of the voltage waveform exceeds the voltage range is acquired in advance, and the connection may be released when this timing is reached. Similarly, when connecting the capacitive load and the voltage waveform output means, any method may be used as long as the capacitive load is connected when the voltage of the voltage waveform returns to the voltage range. It may be connected when the voltage of the waveform is measured and it is detected that the voltage has returned to the voltage range, or the timing at which the voltage of the voltage waveform returns to the voltage range is acquired in advance and connected when the timing is reached. It is good.

  In the capacitive load driving circuit of the present invention described above, when the capacitive load disconnected from the output of the voltage waveform output means is reconnected to the output of the voltage waveform output means, the connection is made as follows. It is good also as what to do. That is, when the voltage of the voltage waveform rises after the connection is released, the voltage waveform output means and the capacitor are connected via the rectifier element in a state where the rectifier element is connected in a direction that prevents current from flowing into the capacitive load. Connect the load. Conversely, if the voltage waveform voltage drops after the capacitive load is disconnected, the rectifier is connected with the rectifying element connected in a direction that prevents current from flowing out of the capacitive load. The voltage waveform output means and the capacitive load are connected through the element.

  When the voltage waveform voltage rises after the capacitive load is disconnected, the voltage waveform voltage is higher than the voltage held by the capacitive load. Therefore, if the capacitive load and the output of the voltage waveform output means are connected via a rectifying element provided in a direction that prevents current from flowing into the capacitive load, the voltage waveform output by the voltage waveform output means Until the voltage drops to the voltage of the capacitive load, the voltage change of the capacitive load can be prevented by blocking the current flowing from the voltage waveform output means to the capacitive load. Furthermore, when the voltage waveform voltage drops to the capacitive load voltage, current begins to flow between the capacitive load and the output of the voltage waveform output means, thereby matching the voltage waveform voltage and the capacitive load voltage. It is possible to connect the capacitive load to the output of the voltage waveform output means at the timing to do so. As a result, when the capacitive load is connected to the output of the voltage waveform output means and the voltage of the capacitive load is changed, the voltage of the capacitive load can be changed smoothly. It becomes possible to apply to the sexual load.

  Similarly, if the voltage waveform voltage drops after the capacitive load is disconnected, connecting the rectifier element in a direction that prevents current from flowing out of the capacitive load will reduce the voltage waveform voltage drop. Until the voltage rises to the voltage of the capacitive load, the voltage change of the capacitive load can be prevented by blocking the current flowing from the capacitive load to the voltage waveform output means. And when the voltage of the voltage waveform rises to the voltage of the capacitive load, the voltage waveform output means and the capacitive load can be connected at the timing when the voltage waveform voltage and the capacitive load voltage match. An appropriate voltage waveform in which the voltage changes smoothly can be applied to the capacitive load.

  Note that the rectifying element is not limited to a so-called diode, and any element may be used as long as the element prevents the reverse current through the forward current. For example, the rectifier element may be used between the base terminal and the emitter terminal of the transistor. Also in such a case, since the capacitive load can be connected to the output of the voltage waveform output means at an appropriate timing by controlling the current, it is possible to apply an accurate voltage waveform to the capacitive load.

Further, the above-described capacitive load driving circuit of the present invention can be grasped as the following mode. That is,
Voltage waveform output means for outputting a voltage waveform used for driving the first capacitive load and the second capacitive load;
Voltage waveform applying means for applying the voltage waveform to the first capacitive load and the second capacitive load;
The voltage waveform applying means connects the first capacitive load and the output of the voltage waveform output means when the voltage waveform voltage is outside the first voltage range defined for the first capacitive load. When the voltage waveform voltage is within the first voltage range, the first capacitive load is connected to the output of the voltage waveform output means, while the voltage waveform voltage is When the load is determined as a capacitive load and is outside the range of the second voltage range in which at least part of the voltage range is different from the first voltage range, the second capacitive load and the output of the voltage waveform output means Disconnecting and connecting the second capacitive load to the output of the voltage waveform output means when the voltage waveform voltage is within the second voltage range; A capacitive load driving circuit which is means for applying different voltage waveforms to the second capacitive load; It is possible to grasp.

Further, the capacitive load driving method of the present invention corresponding to the capacitive load driving circuit of such an aspect is as follows.
Outputting a voltage waveform used to drive the first capacitive load and the second capacitive load;
Applying the voltage waveform to the first capacitive load and the second capacitive load;
The step of applying the voltage waveform includes the step of applying the first capacitive load and the voltage waveform output means when the voltage of the voltage waveform is outside the first voltage range defined for the first capacitive load. When the connection with the output is released and the voltage waveform voltage is within the first voltage range, the first capacitive load is connected to the output of the voltage waveform output means, while the voltage waveform voltage is The second capacitive load and the voltage waveform output means when the second capacitive load is outside the second voltage range that is different from the first voltage range and is at least partly different from the first voltage range. When the voltage waveform voltage is within the second voltage range, the second capacitive load is connected to the output of the voltage waveform output means to disconnect the first capacitor. Capacitive negative, which is a step of applying different voltage waveforms to the capacitive load and the second capacitive load Driving method.
It is possible to grasp as.

  In the capacitive load driving circuit and the capacitive load driving method of such an aspect, each capacitive load is driven by connecting the output of the voltage waveform output means to the first capacitive load and the second capacitive load. When the voltage waveform voltage output from the voltage waveform output means exceeds the voltage range (first voltage range and second voltage range) determined for each capacitive load, the capacitive load and the voltage waveform output. The connection with the means is released, and when the voltage waveform voltage returns to the voltage range, the released connection is reconnected to apply different voltage waveforms to the first capacitive load and the second capacitive load.

  Since the first capacitive load and the second capacitive load are capacitive elements, when the connection with the output of the voltage waveform output means is released, the voltage applied when the connection is released is held. When the voltage of the voltage waveform returns to the voltage range and the capacitive load is connected again to the output of the voltage waveform output means, the voltage waveform output by the voltage waveform output means is applied thereafter. As a result, a voltage waveform different from the voltage waveform output by the voltage waveform output means can be applied to each capacitive load. In addition, the voltage waveform applied to each capacitive load is determined by the voltage range determined for each capacitive load. Therefore, if the first voltage range and the second voltage range are different, the first voltage range is the first voltage range. Different voltage waveforms can be applied to the capacitive load and the second capacitive load. As a result, even when the output of one voltage waveform output means is applied to the first capacitive load and the second capacitive load, it is possible to apply the appropriate voltage waveform according to the characteristics of each capacitive load. It is possible to suppress variation in operation between loads.

  In addition, if the capacitive load driving circuit of the present invention described above is used, fluid can be appropriately ejected from the ejection nozzle by driving an actuator provided in the ejection nozzle. It is also possible to grasp as a fluid ejection device comprising

  In the fluid ejecting apparatus of the present invention, the above-described load drive circuit can suppress the variation in operation between the actuators, and as a result, the variation in the amount of fluid to be ejected, the size of the fluid droplet, the fluid ejection speed, and the like is reduced. Thus, the fluid can be ejected appropriately.

  In addition, since the above-described fluid ejecting apparatus of the present invention can be mounted on a printing apparatus, the present invention can also be grasped as a printing apparatus equipped with the above-described fluid ejecting apparatus.

  In such a printing apparatus of the present invention, the above-described capacitive load driving circuit suppresses the variation in the operation between the actuators, thereby suppressing the variation in the amount of fluid such as ink and the size of the fluid droplet, thereby appropriately applying the fluid droplet. Therefore, it is possible to print a high quality image.

It is explanatory drawing which showed the rough structure of the inkjet printer carrying the piezoelectric element drive circuit of a present Example. It is explanatory drawing which showed the mechanism inside an ejection head in detail. It is explanatory drawing which illustrated the voltage waveform (drive voltage waveform) applied to a piezo element. It is explanatory drawing which showed the piezoelectric element drive circuit with which the inkjet printer of the present Example was equipped, and its peripheral circuit structure. It is explanatory drawing which showed notionally the mode that the drive voltage waveform which the drive voltage waveform generation circuit produced | generated in the inkjet printer of a present Example was applied to a piezo element. It is explanatory drawing which showed the gate unit of the modification which provided separately the path | route through which the electric current which goes to a piezo element from a drive voltage waveform generation circuit and the electric current which flows from a piezo element to a drive voltage waveform generation circuit were provided. It is explanatory drawing which showed a mode that a drive voltage waveform was applied to a piezo element using the gate unit of a modification. It is explanatory drawing which showed a mode that a drive voltage waveform was applied to a piezo element using the gate unit of a modification. It is explanatory drawing which showed a mode that a voltage waveform was applied to a piezoelectric element using the gate unit of the 3rd modification which carries out exclusive operation of two gate elements. It is explanatory drawing which showed the gate unit of the 4th modification which operates a gate element according to the data by which the output voltage of the drive voltage waveform at the time of operating a gate element was described. It is explanatory drawing which illustrated a mode that the gate element of the ejection opening which does not eject an ink drop is operated according to gate timing data.

Hereinafter, in order to clarify the contents of the present invention described above, examples will be described in the following order.
A. Inkjet printer configuration:
B. Driving voltage waveform application method of this embodiment:
C. Variations:
C-1. First modification:
C-2. Second modification:
C-3. Third modification:
C-4. Fourth modification:
C-5. Fifth modification:

A. Inkjet printer device configuration:
FIG. 1 is an explanatory diagram showing a rough configuration of an ink jet printer (corresponding to a printing apparatus) equipped with a piezo element driving circuit (corresponding to a capacitive load driving circuit) of this embodiment. As shown in the drawing, the inkjet printer 10 includes a carriage 20 that forms ink dots on the print medium 2 while reciprocating in the main scanning direction, a drive mechanism 30 that reciprocates the carriage 20, and paper of the print medium 2. The platen roller 40 is used for feeding. In the carriage 20, an ink cartridge 26 that contains ink, a carriage case 22 in which the ink cartridge 26 is mounted, and an ejection head that is mounted on the bottom surface side (side facing the print medium 2) of the carriage case 22 and ejects ink. 24 (corresponding to a liquid ejecting apparatus) is provided, and the ink in the ink cartridge 26 is guided to the ejecting head 24 so that an accurate amount of ink can be ejected from the ejecting head 24 toward the print medium 2. It has become.

  The drive mechanism 30 that reciprocates the carriage 20 includes a guide rail 38 that extends in the main scanning direction, a timing belt 32 that has a plurality of teeth formed therein, a drive pulley 34 that drives the timing belt 32, and a step motor. 36 or the like. A part of the timing belt 32 is fixed to the carriage case 22, and by driving the timing belt 32, the carriage case 22 can be accurately moved along the guide rail 38.

  Further, the platen roller 40 is driven by a drive motor or a gear mechanism (not shown), and can feed the print medium 2 by a predetermined amount in the sub-scanning direction. Each of these mechanisms is controlled by a printer control circuit 50 mounted on the inkjet printer 10. Under the control of the printer control circuit 50, the platen roller 40 feeds the print medium 2 and the carriage case 22 An image is printed on the print medium 2 by ejecting ink from the ejection head 24 while moving in the main operation direction.

  FIG. 2 is an explanatory view showing in detail the mechanism inside the ejection head. As shown in the drawing, the bottom surface of the ejection head 24 (the surface facing the print medium 2) is provided with a plurality of ejection ports 200, and ink droplets can be ejected from the respective ejection ports 200. It has become. Each ejection port 200 is connected to an ink chamber 202, and the ink chamber 202 is filled with ink supplied from the ink cartridge 26. A piezo element 204 (corresponding to a capacitive load) is provided on the ink chamber 202, and when a voltage is applied to the piezo element 204, the piezo element 204 is deformed to pressurize the ink chamber 202, thereby Ink droplets can be ejected from 200. In addition, since the deformation amount of the piezo element 204 changes according to the voltage value of the applied voltage, if the voltage applied to the piezo element 204 is appropriately controlled, the pressing force and the pressing timing of the ink chamber 202 are adjusted. It is possible to control the size of the ejected ink droplet. For this reason, the inkjet printer 10 applies the following voltage waveform to the piezo element 204.

  FIG. 3 is an explanatory diagram illustrating a voltage waveform (drive voltage waveform) applied to the piezo element. As shown in the figure, the drive voltage waveform has a trapezoidal waveform in which the voltage rises with time and then falls back to the original voltage value. Further, the drawing shows how the piezo element 204 expands and contracts according to the drive voltage waveform. As shown in the figure, when the voltage value of the drive voltage waveform increases, the piezo element 204 gradually contracts accordingly. At this time, since the ink chamber 202 is expanded by being pulled by the piezo element 204, ink can be supplied from the ink cartridge 26 into the ink chamber 202. When the voltage value decreases after the voltage value increases and reaches a peak, this time, the piezo element 204 expands, thereby compressing the ink chamber 202 and ejecting ink from the ejection port 200. At this time, the drive voltage waveform is lowered to a voltage value lower than the original voltage value (the voltage value indicated as “initial voltage” in the drawing), and the piezo element 204 is expanded from the initial state so as to expand the ink. Can be fully extruded. Thereafter, the drive voltage waveform returns to the initial voltage, and correspondingly, the piezo element 204 also returns to the initial state.

  As described above, the inkjet printer 10 includes the piezo element 204 in the ink chamber 202, and can apply ink droplets from the ejection head 24 by applying an appropriate drive voltage waveform to the piezo element 204. It has become. For this reason, the ink jet printer 10 includes a piezo element drive circuit 100 that generates a drive voltage waveform and applies it to the piezo element 204 in addition to the printer control circuit 50 that controls the operation of each mechanism.

  FIG. 4 is an explanatory diagram showing a piezo element driving circuit provided in the ink jet printer of the present embodiment and its peripheral circuit configuration. As shown in the figure, the piezo element driving circuit 100 includes a driving voltage waveform generating circuit 110 (corresponding to a voltage waveform output means) that generates a driving voltage waveform, and a driving voltage waveform generated by the driving voltage waveform generating circuit 110. A gate unit 300 (corresponding to voltage waveform applying means) leading to the element 204 is configured. The drive voltage waveform generation circuit 110 includes a power source that generates a voltage, a waveform generation circuit that generates a voltage waveform by changing the voltage from the power source, and the like, and a predetermined drive voltage waveform according to an instruction from the printer control circuit 50. Can be generated.

  The drive voltage waveform generated by the drive voltage waveform generation circuit 110 is output to the gate unit 300 as shown. The gate unit 300 includes a plurality of gate elements 302 connected in parallel, and a piezo element 204 is connected to the tip of each gate element 302. Each gate element 302 can be individually turned on or off, and if only the gate element 302 of the ejection port to which ink is to be ejected is turned on, only the corresponding piezoelectric element 204 can be turned on. An ink droplet can be ejected from the ejection port 200 by applying a drive voltage waveform. Each of these gate elements 302 is operated by a gate element control circuit 150, and the gate element control circuit 150 operates each gate element 302 in accordance with a command from the printer control circuit 50.

  The printer control circuit 50 prints an image as follows using such a circuit configuration. First, based on the image data to be printed, the ejection port 200 that ejects ink droplets and the waveform of the drive voltage waveform for ejecting ink droplets are determined. Then, a command is sent to the gate element control circuit 150 so that the gate element 302 of the ejection port 200 that ejects ink droplets is in a conductive state, and the drive voltage waveform generation circuit 110 is operated to generate a drive voltage waveform. The drive voltage waveform thus generated is applied to the piezo element 204 of the target ejection port 200 via the gate element 302, and as a result, ink droplets are ejected from the target ejection port 200.

  Here, in the ink jet printer of the present embodiment, as shown in the drawing, the gate elements 302 are connected to the drive voltage waveform generation circuit 110 in a state of being connected in parallel. Can be applied to the plurality of piezo elements 204 by making the continuity state. In this way, since it is possible to eject ink droplets from the plurality of ejection ports 200 only by generating one drive voltage waveform, it is possible to print an image at high speed.

  However, when a single drive voltage waveform is applied to the plurality of piezo elements 204 in this way, as described above, due to variations in the diameters of the respective injection openings 200 and variations in the operating characteristics of the piezo elements 204, the injection is performed. The size and speed of ink droplets to be dispersed may vary from one ejection port 200 to another. In such a case, it is difficult to improve the quality of the printed image because the ink droplets cannot be ejected with a uniform size. Of course, such variations include, for example, a driving voltage waveform that matches the characteristics of the individual ejection ports 200, such as applying a driving voltage waveform with a slightly smaller amplitude at the ejection port 200 in which the size of the ejected ink droplet increases. Can be reduced by generating and applying. However, if a drive voltage waveform is to be generated for each injection port 200, a large number of drive voltage waveform generation circuits 110 are required, resulting in an increase in the size of the apparatus. Therefore, in the inkjet printer 10 of the present embodiment, the drive voltage waveform generated by one drive voltage waveform generation circuit 110 is applied to the piezo element 204 as follows to increase the number of drive voltage waveform generation circuits 110. Rather, different drive voltage waveforms can be applied to the piezo elements 204 of the individual injection ports 200.

B. Driving voltage waveform application method of this embodiment:
FIG. 5 is an explanatory diagram conceptually showing a state in which the drive voltage waveform generated by the drive voltage waveform generation circuit is applied to the piezo element in the ink jet printer of this embodiment. FIG. 5A illustrates the drive voltage waveform generated by the drive voltage waveform generation circuit 110. As described above, in the inkjet printer 10 of the present embodiment, such a driving voltage waveform is sent to the gate element 302 connected to each piezo element 204 (see FIG. 4). A drive voltage waveform can be applied to the piezo element 204 of the target injection port 200 by bringing the gate element 302 of the target injection port 200 into a conductive state.

  However, if the gate element 302 is simply made conductive, the drive voltage waveform generated by the drive voltage waveform generation circuit 110 is simply applied to the piezo element 204 as it is. A matching drive voltage waveform cannot be applied. Therefore, in the inkjet printer 10 of the present embodiment, when the printer control circuit 50 designates the ejection port 200 that ejects ink droplets, the gate element control circuit 150 simply sets the gate element 302 of the ejection port 200 to a conductive state. Instead, the gate element 302 is operated according to the gate timing data described below.

  FIG. 5B is an explanatory diagram illustrating gate timing data used when operating the gate element 302. As shown in the drawing, the gate timing data indicates that the gate element 302 is in a conductive state (a state indicated as “ON” in FIG. 5B) along the time axis (lateral direction in FIG. 5B). Alternatively, it is data describing the timing of the cut state (the state indicated as “OFF” in FIG. 5B). In the inkjet printer 10 of the present embodiment, such gate timing data is stored in advance in the ROM in the gate element control circuit 150 for each gate element 302, and the ejection port 200 from which the printer control circuit 50 ejects ink droplets is stored. Is determined, the gate element control circuit 150 can read out and acquire the gate timing data of the gate element 302 corresponding to the ejection port 200 from the ROM.

  Here, as shown in FIG. 5B, in the gate timing data, not only the timing at which the gate element 302 is turned on (“ON” state) but also the gate element 302 is in a disconnected state (“OFF”). ) State) is also specified. For this reason, when the gate element 302 is operated in accordance with the gate timing data, the piezo element 204 and the drive voltage waveform generation circuit 110 are not always connected to each other, but the piezo element 204 and the drive voltage waveform are generated in a certain period. The circuit 110 is disconnected from the circuit 110 (in the example of FIG. 5B), the period from the timing indicated by “t1” to the timing indicated by “t2” and the timing indicated by “t3” is “t4”. Period until the timing shown). However, while the piezo element 204 and the drive voltage waveform generation circuit 110 are disconnected, the drive voltage waveform generation circuit 110 continues to output the drive voltage waveform without stopping the output of the drive voltage waveform. As described above, the drive voltage waveform generation circuit 110 outputs the drive voltage waveform, but the drive voltage waveform generation circuit 110 and the piezo element 204 are disconnected, so that the inkjet printer 10 of this embodiment As will be described next, a voltage waveform different from the drive voltage waveform output by the drive voltage waveform generation circuit 110 can be applied to the piezo element 204.

  FIG. 5C shows a state in which the drive voltage waveform is applied to the piezo element 204 by the gate element control circuit 150 operating the gate element 302 according to the gate timing data shown in FIG. 5B. Yes. In the gate timing data illustrated in FIG. 5B, the gate element 302 is first instructed to be in a conductive state (“ON” state) (“0” on the horizontal axis in FIG. 5B). The gate element control circuit 150 makes the gate element 302 conductive (“ON” state) accordingly. As a result, the drive voltage waveform output from the drive voltage waveform generation circuit 110 is applied to the piezo element 204, and the voltage of the piezo element 204 rises ("t1" from the timing indicated by "0" in FIG. 5C). Until the timing shown.)

  Next, when the timing indicated by “t1” in FIG. 5B is reached, the gate timing data instructs the gate element 302 to be in an OFF state (disconnected state). The circuit 150 turns off the gate element 302. As a result, the piezo element 204 is disconnected from the drive voltage waveform generation circuit 110, and the drive voltage waveform is not applied to the piezo element 204. Here, since the piezo element 204 is a so-called capacitive load capable of storing the applied voltage therein, even if the drive voltage waveform is not applied, the voltage is not lost completely and is applied until immediately before. The voltage that has been kept can be kept as it is. For this reason, when the gate element 302 is in a disconnected state, as shown in FIG. 5C from the timing indicated by “t1” to the timing indicated by “t2”, the piezo element 204 is The voltage applied immediately before (the voltage at the timing indicated by “t1” in FIG. 5C) is kept as it is. As a result, a voltage different from the voltage of the drive voltage waveform (see the voltage indicated by the broken line in FIG. 5C) is applied to the piezo element 204 (shown by the solid line in FIG. 5C). Voltage).

  When the timing indicated by “t2” in FIG. 5B is reached after a lapse of time, the gate element control circuit 150 makes the gate element 302 conductive again in accordance with the instruction of the gate timing data, and generates a drive voltage waveform. The circuit 110 and the piezo element 204 are connected. When the piezo element 204 and the drive voltage waveform generation circuit 110 are thus connected, the voltage of the drive voltage waveform output from the drive voltage waveform generation circuit 110 is applied to the piezo element 204 as it is, so that the voltage of the drive voltage waveform drops. As a result, the voltage of the piezo element 204 is lowered and a drive voltage waveform can be applied to the piezo element 204 (shown as “t3” from the timing indicated as “t2” in FIG. 5C). See until the timing).

  When the drive voltage waveform generation circuit 110 and the piezo element 204 are connected, the voltage of the piezo element 204 and the voltage of the drive voltage waveform generation circuit 110 are prevented from preventing the voltage of the piezo element 204 from changing suddenly. It is preferable to connect the piezo element 204 and the drive voltage waveform generation circuit 110 in a state where the difference between is small. Here, as described above, since the piezo element 204 is a capacitive load, even after being disconnected from the drive voltage waveform generation circuit 110, the voltage at the time of disconnection (indicated as “t1” in FIG. 5C). It is considered that the timing voltage is maintained as it is. Therefore, the output voltage of the drive voltage waveform generation circuit 110 (voltage of the drive voltage waveform) is the voltage of the drive voltage waveform when the piezo element 204 and the drive voltage waveform generation circuit are disconnected ("t1" in FIG. 5C). If the drive voltage waveform generation circuit 110 and the piezo element 204 are connected again at the timing when the voltage is lowered to the voltage at the timing indicated by), the voltage of the piezo element 204 and the voltage of the drive voltage waveform generation circuit 110 are substantially equal. It becomes possible to connect both. For this reason, when setting the gate timing data, the voltage of the drive voltage waveform (the voltage at the timing indicated by “t1” in FIG. 5C) when the gate element 302 is turned off, and the gate The gate timing data is set so that the voltage of the driving voltage waveform (the voltage of the driving voltage waveform at the timing indicated by “t2” in FIG. 5C) when the element 302 is turned on matches. It is preferable.

  When the timing indicated by “t3” in FIG. 5B is reached after the gate element 302 is turned on, this time the gate timing data instructs the gate element 302 to be in the OFF state (disconnected state) again. Therefore, the gate element control circuit 150 cuts the gate element 302 in accordance with this. As a result, the drive voltage waveform output from the drive voltage waveform generation circuit 110 is not applied to the piezo element 204. At this time, since the piezo element 204 is a capacitive load as described above, when it is disconnected from the drive voltage waveform generation circuit 110, the voltage applied until immediately before is continuously applied to the piezo element 204 as it is. As a result, as shown in FIG. 5C, a voltage higher than the voltage of the drive voltage waveform (see the voltage indicated by the broken line in FIG. 5C) is continuously applied to the piezo element 204. (See the period from the timing indicated as “t3” to the timing indicated as “t4” in FIG. 5C).

  Thereafter, when the timing indicated by “t4” in the drawing is reached, the gate element control circuit 150 sets the gate element 302 to the “ON” state (conductive state) again according to the gate timing data. At this time, as described above, the gate element 302 is turned on at the timing when the voltage of the drive voltage waveform and the voltage of the piezo element 204 are substantially the same, so that the piezo element 204 and the drive voltage waveform generation circuit 110 are turned on. It is possible to suppress the voltage change of the piezo element 204 when connected to each other. After the drive voltage waveform generation circuit 110 and the piezo element 204 are connected in this way, the drive voltage waveform generated by the drive voltage waveform generation circuit 110 is applied as it is to the piezo element 204, so that the voltage of the piezo element 204 according to the drive voltage waveform. Rises. As described above, by operating the gate element 302 according to the gate timing data of FIG. 5B, the voltage waveform indicated by the solid line in FIG. 5C is applied to the piezo element 204.

  As described above, in the piezo element drive circuit 100 according to the present embodiment, the piezo element 204 and the drive voltage waveform generation circuit 110 are always connected while the drive voltage waveform generation circuit 110 outputs the drive voltage waveform. Rather than leave, both are cut off during some period. In this way, since the entire drive voltage waveform output from the drive voltage waveform generation circuit 110 is not applied to the piezo element 204, only a part of the drive voltage waveform can be applied. A voltage waveform different from the voltage waveform can be applied to the piezo element 204. In this embodiment, the piezo element 204 and the drive voltage waveform generation circuit 110 are disconnected while the voltage of the drive voltage waveform is above a certain voltage value and below the certain voltage value. In this way, only a part of the amplitude of the drive voltage waveform can be applied to the piezo element 204, so that the drive voltage waveform output by the drive voltage waveform generation circuit 110 is output as shown in FIG. A voltage waveform (a waveform shown by a solid line in FIG. 5C) having a different amplitude from that of the waveform shown by a broken line in FIG. 5C can be applied to the piezo element 204.

  Therefore, when the drive voltage waveform output from the drive voltage waveform generation circuit 110 is applied to the plurality of piezo elements 204, gate timing data corresponding to each piezo element 204 is read out, and each piezo element 204 is read according to each gate timing data. If the gate elements 302 corresponding to the above are respectively operated, voltage waveforms having different amplitudes can be applied to the piezoelectric elements 204. And if the gate timing data of each injection port 200 is preset according to the characteristic of each injection port 200, the drive voltage waveform of the appropriate amplitude according to the characteristic of each injection port 200 can be applied. Therefore, it is possible to suppress variations among the plurality of injection ports 200. For example, in the ejection port 200 that ejects ink droplets larger in size than the other ejection ports 200 when the same voltage waveform is applied, the gate timing data is set to drive voltage so that the amplitude of the applied voltage waveform is reduced. The timing at which the waveform generation circuit 110 and the piezo element 204 are disconnected (the timing indicated by “t1” and the timing indicated by “t3” in FIG. 5B) is set earlier. Conversely, the timing at which the drive voltage waveform generation circuit 110 and the piezo element 204 are connected (the timing indicated by “t2” and the timing indicated by “t4” in FIG. 5B) is set later. Keep it. In this way, the amount of expansion and contraction of the piezo element 204 can be reduced by reducing the amplitude of the applied voltage waveform (see FIG. 3). It is possible to eject ink droplets of approximately the same size as 200 ink droplets. If the gate timing data of each injection port 200 is set in advance according to the characteristics of the injection port 200 and the piezo element 204 in this way, variation between the plurality of injection ports 200 can be suppressed and each injection port 200 can be controlled. It becomes possible to eject ink droplets of a uniform size from the mouth 200.

  As described above, in the inkjet printer 10 of the present embodiment, the drive voltage waveform generation circuit 110 and the piezo element 204 are temporarily disconnected while the drive voltage waveform generation circuit 110 outputs the drive voltage waveform. As a result, a voltage waveform different from the drive voltage waveform output from the drive voltage waveform generation circuit can be applied to the piezo element 204. Therefore, even when a drive voltage waveform output from one drive voltage waveform generation circuit 110 is applied to a plurality of piezo elements 204, it is possible to apply different drive voltage waveforms to each piezo element 204. In addition, the period during which the piezo element 204 and the drive voltage waveform generation circuit 110 are disconnected is provided in a period in which the drive voltage waveform output from the drive voltage waveform generation circuit 110 exceeds a certain voltage and a period that falls below a certain voltage. A voltage waveform having an amplitude different from that of the drive voltage waveform output from the drive voltage waveform generation circuit 110 can be applied to the piezo element 204. In this way, by setting the gate timing data according to the characteristics of each injection port 200 and the piezoelectric element 204, the amplitude of the voltage waveform applied to the piezoelectric element 204 of each injection port 200 is adjusted, and each injection port. It is possible to suppress variations such as the size of the ink droplets ejected from 200. Accordingly, by applying the drive voltage waveform generated by one drive voltage waveform generation circuit 110 to the plurality of piezo elements 204, the number of drive voltage waveform generation circuits 110 can be reduced and the apparatus configuration can be kept simple. High-quality images can be printed while suppressing variations in the size of ink droplets ejected from the ejection port 200.

  In the above description, in a state where the gate element 302 is disconnected (see the period from the timing indicated by “t1” to the timing indicated by “t2” in FIG. 5C), the piezoelectric element 204 It has been described that the voltage is kept constant. However, strictly speaking, since the electric charge stored in the piezo element 204 is discharged with time, the voltage of the piezo element 204 gradually decreases as the electric charge is discharged. However, even in such a case, if the gate element 302 is subsequently turned on, the output voltage of the drive voltage waveform generation circuit 110 is applied to the piezo element 204 so that the voltage of the piezo element 204 is immediately recovered. Even if the voltage of the piezo element 204 slightly drops, it is possible to apply a substantially accurate voltage waveform to the piezo element 204. Therefore, the piezo element 204 is not necessarily required to have a large capacitance enough to keep the voltage, and if the piezoelectric device 204 has a certain amount of capacitance that the voltage does not extremely decrease. Good.

  In the present embodiment, the gate timing data is read and acquired from the ROM of the ink jet printer 10. However, the gate timing data is not necessarily acquired from the ROM of the ink jet printer 10, and may be acquired from another device. . For example, when the inkjet printer 10 is connected to a computer and used, it may be acquired from the computer.

  Further, in the drive voltage waveform illustrated in FIG. 5A, it has been described that the voltage continuously changes when the voltage rises or falls. However, not only the driving voltage waveform in which the voltage continuously changes, but also a driving voltage waveform in which the voltage changes stepwise may be used. Even with such a drive voltage waveform, if the gate element is operated in accordance with the gate timing data, only a part of the drive voltage waveform can be applied to the piezo element 204. Therefore, a voltage waveform different from the drive voltage waveform is generated. It becomes possible to apply to. Thereby, it is possible to apply an appropriate voltage waveform to the piezo element 204 of each ejection port 200 to suppress variations in the size of ink droplets between the ejection ports 200.

  In addition, when the drive voltage waveform generation circuit 110 and the piezo element 204 are disconnected, the voltage of the piezo element 204 is maintained as described above, so that the drive voltage waveform generation circuit 110 does not output a voltage during that time. May be. Therefore, the drive voltage waveform generation circuit 110 does not keep the voltage constant after increasing the voltage (from the timing indicated by “t1” in FIG. 5C to the timing indicated by “t2”). The voltage may be lowered by referring to the voltage indicated by a broken line between them). Then, when the timing for reconnecting to the piezo element 204 (the timing indicated by “t2” in FIG. 5C) approaches, the voltage may be increased again. Even when such a so-called saw-shaped voltage waveform is output, since the voltage of the piezo element 204 is maintained while the piezo element 204 and the drive voltage waveform generation circuit 110 are disconnected, the piezo element 204 has high accuracy. A voltage waveform can be applied. In addition, since the period during which the drive voltage waveform generation circuit 110 outputs voltage can be reduced in this way, it is possible to reduce power consumption.

C. Modified example:
Below, the modification of the Example mentioned above is demonstrated. In the following modified example, the same components as those in the above-described embodiment are denoted by the same reference numerals as those in the embodiment and detailed description thereof is omitted.

C-1. First modification:
When driving by applying a drive voltage waveform to the piezo element 204, when the voltage of the piezo element 204 rises, a current flows from the drive voltage waveform generation circuit 110 toward the piezo element 204, and conversely, the piezo element 204. Current drops from the piezo element 204 toward the drive voltage waveform generation circuit 110. Therefore, a path through which current flows from the drive voltage waveform generation circuit 110 to the piezoelectric element 204 and a current from the piezoelectric element 204 to the drive voltage waveform generation circuit 110 flow between the drive voltage waveform generation circuit 110 and the piezoelectric element 204. If a path is provided separately and a gate element is provided for each path, it is possible to select and flow a current in either direction. When such a configuration is used, as described below, it is possible to apply a drive voltage waveform with high accuracy to the piezo element 204 even when the timing for operating the gate element 302 is shifted for some reason.

  FIG. 6 shows a modified gate unit in which a path through which a current from the drive voltage waveform generation circuit 110 flows to the piezo element 204 and a path through which a current from the piezo element 204 travels to the drive voltage waveform generation circuit 110 are separately provided. It is explanatory drawing shown. As shown in FIG. 6A, in the gate unit 300 of the modified example, each piezo element 204 is connected to the drive voltage waveform generation circuit 110 by two gate elements of the gate element A and the gate element B. Further, a diode Da is connected between the gate element A and the piezo element 204, and a diode Db is connected between the gate element B and the piezo element 204. The diode Da is provided so that a current flowing in the direction from the drive voltage waveform generation circuit 110 side to the piezo element 204 side flows. The diode Db is driven from the piezo element 204 side, contrary to the diode Da. It is provided so that a current flowing in the direction toward the voltage waveform generation circuit 110 flows. Therefore, when the gate element A is turned on, a current can flow from the drive voltage waveform generation circuit 110 side to the piezo element 204 side. Conversely, the gate element B is turned on. In this case, a current can flow from the piezo element 204 side toward the drive voltage waveform generation circuit 110 side.

  Further, in the inkjet printer 10 according to the modification, corresponding to the provision of two gate elements for each piezoelectric element 204, as shown in FIG. On the other hand, two gate timing data, that is, gate timing data of the gate element A and gate timing data of the gate element B are stored in the ROM. The inkjet printer 10 according to the modified example applies a drive voltage waveform to the piezo element 204 using the above configuration as follows.

  7 and 8 are explanatory views showing a state in which a drive voltage waveform is applied to the piezo element using the gate unit of the modification. 7A shows the gate timing data of the gate element A and the gate element B, respectively, and the lower stage of FIG. 7A shows the gate element according to the gate timing data of FIG. 7A. The voltage applied to the piezo element 204 by operating is shown.

  When the drive voltage waveform shown in FIG. 7A is applied, first, in order to increase the voltage of the piezo element 204, it is necessary to pass a current from the drive voltage waveform generation circuit 110 toward the piezo element 204. Accordingly, corresponding to this, in the gate timing data shown in FIG. 7A, the gate element A provided in the path from the drive voltage waveform generation circuit 110 to the piezo element 204 is in a conductive state (“ON ")"). When the gate element A is turned on, a current can flow from the drive voltage waveform generation circuit 110 to the piezo element 204 as the output voltage of the drive voltage waveform generation circuit 110 (voltage of the drive voltage waveform) increases. As a result, the voltage of the piezo element 204 can be raised following the output voltage of the drive voltage waveform generation circuit 110. Thereafter, when the timing indicated by “t1” in the drawing is reached, the gate element A is turned off (“OFF” state) according to the gate timing data. As described above, since the piezo element 204 is a capacitive load, the voltage of the piezo element 204 can be kept constant by turning off the gate element A (shown as “t1” in FIG. 7A). Until the timing indicated by “t2”).

  Next, the drive voltage waveform generation circuit 110 and the piezo element 204 are connected to drop the voltage of the piezo element 204. In order to decrease the voltage of the piezo element 204, it is only necessary to pass a current from the piezo element 204 toward the drive voltage waveform generation circuit 110. Therefore, this time, a current in a direction from the piezo element 204 toward the drive voltage waveform generation circuit 110 is generated. The gate element (gate element B) in the flowing path (path to which the gate element B and the diode Db are connected) is turned on ("ON" state).

  Here, as shown in FIG. 7A, the timing for operating the gate element is shifted for some reason, and the timing at which the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezoelectric element 204 coincide ( When the gate element B is made conductive at a timing earlier than the timing indicated by “A” in FIG. 7A (see the timing indicated by “t2” in FIG. 7A), The gate element B becomes conductive when the voltage of the drive voltage waveform generation circuit 110 is higher than the voltage of the piezo element 204. In such a state where there is a difference in voltage, when a current flows from the drive voltage waveform generation circuit 110 to the piezo element 204, the voltage of the piezo element 204 may change abruptly. In this regard, in the modified gate unit 300, the path in which the gate element B is provided passes a current from the piezo element 204 to the drive voltage waveform generation circuit 110, and as shown in FIG. Even if a current flows from the drive voltage waveform generation circuit 110 having a high voltage toward the piezoelectric element 204 having a low voltage, the current can be blocked by the diode Db. For this reason, even if the gate element B is turned on while the voltage of the drive voltage waveform generation circuit 110 is higher than the voltage of the piezo element 204, the voltage of the piezo element 204 does not change abruptly.

  In addition, when time elapses thereafter and the voltage of the drive voltage waveform generation circuit 110 decreases and the voltage of the drive voltage waveform generation circuit 110 becomes lower than the voltage of the piezo element 204, this time, as shown in FIG. As shown, current can flow from the piezo element 204 toward the drive voltage waveform generation circuit 110, so the voltage waveform is applied by dropping the voltage of the piezo element 204 together with the voltage of the drive voltage waveform generation circuit 110. It becomes possible to do. As described above, in the inkjet printer 10 according to the modified example, even when the timing at which the gate element B is turned on is deviated from the timing at which the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 are equal, The voltage of the piezo element 204 does not change abruptly. Further, when the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 become equal, the voltage of the piezo element 204 can be immediately dropped. Accordingly, it is possible to drive the piezo element 204 with high accuracy by applying a voltage waveform with high accuracy to the piezo element 204.

  Further, in the gate unit 300 according to the modified example, not only when the voltage of the piezo element 204 is decreased, but also when the voltage of the piezo element 204 is increased, it is possible to avoid the possibility that the voltage of the piezo element 204 changes suddenly. Is possible. For example, as shown in FIG. 8A, from the timing at which the voltage of the drive voltage waveform generation circuit 110 becomes equal to the voltage of the piezo element 204 (the timing indicated as “B” in FIG. 8A). When the gate element A is turned on at the earliest timing (timing indicated by “t4” in FIG. 8A), the piezoelectric element 204 having a high voltage is indicated by the broken line in FIG. 8B. Current tends to flow toward the drive voltage waveform generation circuit 110 having a low voltage. However, this current can be blocked by the diode Da. When the output voltage of the drive voltage waveform generation circuit 110 rises with time and becomes higher than the voltage of the piezo element 204, as shown in FIG. 8C, the drive voltage waveform generation circuit 110 The voltage of the piezo element 204 can be increased by passing a current through the piezo element 204. In this way, even when the timing at which the gate element A is turned on is shifted, it is possible to avoid the possibility that the voltage of the piezo element 204 changes suddenly, and to increase the voltage of the piezo element 204 at an appropriate timing. Thus, it is possible to apply a voltage waveform with high accuracy to the piezo element 204.

  In this manner, a path through which a current from the drive voltage waveform generation circuit 110 flows to the piezo element 204 and a path through which a current from the piezo element 204 travels to the drive voltage waveform generation circuit 110 are separately provided, and a gate element is provided in each path. , It is possible to select and flow only the current that flows in either direction. As described above, the voltage of the piezo element 204 rises when a current flows toward the piezo element 204, and conversely, when the current flows out of the piezo element 204, the voltage drops when the current direction is controlled in this way. It becomes possible to control the direction of change (rise or fall) of the voltage of the element 204. As a result, it is possible to prevent the voltage of the piezo element 204 from changing in a direction opposite to the direction in which the voltage of the piezo element 204 is to be changed. As a result, the voltage of the piezo element 204 can be accurately controlled. Therefore, it is possible to apply a voltage waveform with high accuracy.

C-2. Second modification:
In the gate unit 300 of the first modified example, as described above, even when the gate element is turned on earlier than the timing at which the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 match, the drive voltage waveform The current can be blocked until the voltage of the generation circuit 110 and the voltage of the piezo element 204 match. In addition, it is possible to start flowing a current at a precise timing at which the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 match. Therefore, when the gate element is turned on, the gate element is not turned on at the timing when the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 coincide with each other, but is intentionally turned on early. It is good also as what makes it a state. In this way, the current is prevented until the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 coincide with each other, and the drive voltage waveform generation circuit 110 moves toward the piezo element 204 at the timing when both voltages coincide. Since a current can flow, an accurate voltage waveform can be reliably applied to the piezo element 204. Also, if the timing for turning on the gate element is set in advance, there is a time until the current actually starts flowing, so the timing at which the gate element is actually turned on is higher than the set timing. Even if it is somewhat delayed, it is possible to apply an accurate voltage waveform to the piezo element 204 by supplying a current at an appropriate timing.

C-3. Third modification:
Moreover, in the gate unit 300 of the first modified example described above, the gate element A and the gate element B are individually operated. However, both the gate element A and the gate element B are operated, and when the gate element A is turned on, the gate element B is turned off, and when the gate element A is turned off, the gate is turned off. A so-called exclusive operation for bringing the element B into a conductive state may be performed.

  FIG. 9 is an explanatory diagram showing a state in which a voltage waveform is applied to the piezo element using the gate unit of the third modified example in which two gate elements are exclusively operated. As shown in FIG. 9A, in the gate timing data used in the gate unit of the third modified example, when the gate element A is set to the “ON” state, the gate element is set to the “OFF” state. When the element A is set to the “OFF” state, a so-called exclusive operation for setting the gate element B to the “ON” state is set. When a drive voltage waveform is applied to the piezo element 204 using such gate timing data, first, as in the first modification described above, first, a path through which a current flows from the drive voltage waveform generation circuit 110 to the piezo element 204 flows. The gate element (gate element A) is turned on (“ON” state). As a result, a current flows from the drive voltage waveform generation circuit 110 toward the piezo element 204, so that the voltage of the piezo element 204 can be increased with the output voltage of the drive voltage waveform generation circuit 110. Next, when the timing indicated by “t1” in FIG. 9A is reached, the gate element A is turned off according to the gate timing data.

  Here, since the gate element A and the gate element B are exclusively operated in the third modified example, when the gate element A is turned off, the gate element B is made conductive instead. For this reason, the period during which the voltage of the drive voltage waveform generation circuit 110 is not applied to the piezo element 204 (the period from the timing indicated as “t1” to the timing indicated as “A” in the graph of FIG. 9A). ), One of the gate elements (gate element B) is in a conductive state without being cut off. However, even when the gate element B is in a conductive state, the time until the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 coincide (from the timing indicated by “t1” in FIG. 9A). Since the voltage of the drive voltage waveform generation circuit 110 is higher than the voltage of the piezo element 204, the current is generated by the diode Db as shown in FIG. 9B. Can be prevented. Therefore, even when one gate element (gate element B) is in a conductive state, current is prevented from flowing between the piezo element 204 and the drive voltage waveform generation circuit 110, and the voltage of the piezo element 204 is kept constant. It is possible.

  Then, after reaching the timing at which the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 coincide (the timing indicated by “A” in FIG. 9A), as described above, the piezo element 204 is reached. Therefore, it is possible to apply a voltage waveform with high accuracy by dropping the voltage of the piezo element 204 at an appropriate timing.

  Further, when the timing indicated by “t2” in FIG. 9A is reached, the gate element B is changed from the conductive state to the disconnected state, and the gate element A is changed to the conductive state instead. At this time, one gate element (gate element A) is in a conductive state even though the voltage of the drive voltage waveform generation circuit 110 is not applied to the piezo element 204, but this time, the drive voltage waveform generation circuit 110 FIG. 9C shows the period until the voltage of the piezoelectric element 204 coincides with the voltage of the piezoelectric element 204 (between the timing indicated by “t2” in FIG. 9A and the timing indicated by “B”). As shown, the current can be blocked by the diode Da. Thereby, the voltage of the piezo element 204 can be kept constant. After the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 match (see the timing indicated by “B” in FIG. 9A), the drive voltage waveform generation circuit is connected via the diode Da. Since a current can flow from 110 to the piezo element 204, the voltage of the piezo element 204 can be increased to apply a voltage waveform to the piezo element 204.

  In this way, a path for flowing current in the direction from the drive voltage waveform generation circuit 110 toward the piezo element 204 (path where the gate element A and the diode Da are connected) and a path for flowing current in the opposite direction (gate element B). And a path to which the diode Db is connected), in a state where a current flows through one path, the current is a reverse current for the other path. For this reason, if the gate element of one path (for example, gate element A) is cut off, even if the gate element of the other path (for example, gate element B) is turned on, the current is opposite for the other path. Current does not flow. Therefore, if one gate element is turned off and the other gate element is turned on, the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 coincide with each other until the direction of the current is changed. Until the current is prevented, and the voltage of the piezoelectric element 204 can be kept constant. Then, after the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 match, the direction of the current changes, so that a current can flow between the drive voltage waveform generation circuit 110 and the piezo element 204. It becomes. As a result, a current can be passed between the drive voltage waveform generation circuit 110 and the piezo element 204 at an appropriate timing, and an accurate voltage waveform can be applied to the piezo element 204.

  In this so-called exclusive operation, if there is gate timing data of one of the gate elements, the other gate element can also be operated in accordance with the gate timing data. Data is not always necessary, and any one of the gate timing data is sufficient. Therefore, if one gate timing data is used, the storage capacity of the ROM for storing the gate timing data can be saved, and the gate element control circuit 150 can acquire the gate timing data. It is also possible to shorten the time required.

  In the gate unit 300 of the third modified example, when the voltage of the drive voltage waveform generation circuit 110 is applied to the piezo element 204, the timing at which the voltage of the drive voltage waveform generation circuit 110 and the voltage of the piezo element 204 become equal. After passing (the timing indicated by “A” and the timing indicated by “B” in FIG. 9A), the current starts to flow naturally by reversing the direction of the current. At this timing, the gate element is operated. You don't have to. Therefore, it is possible to reduce the number of operations of the gate element, and it is possible to simplify the configuration of the gate element control circuit 150 that operates the gate element. It is also possible to suppress the amount of gate timing data.

C-4. Fourth modification:
In the above-described embodiments and modifications, the description has been given on the assumption that the gate element is operated according to the gate timing data describing the timing of operating the gate element. However, the gate element may be operated according to data in which the voltage of the drive voltage waveform generation circuit 110 is described not at the timing at which the gate element is operated but at the timing at which the gate element is operated.

  FIG. 10 is an explanatory diagram showing a gate unit 300 of a fourth modification example in which the gate element is operated according to the data describing the output voltage of the drive voltage waveform when the gate element is operated. As shown in FIG. 10A, in the gate unit 300 of the fourth modified example, two comparators (voltage comparators) of a comparator Cd and a comparator Cu are connected to each gate element 302. In addition to the gate element control circuit 150, the gate element 302 can be operated by these comparators. Further, the comparator Cd and the comparator Cu are respectively connected to the comparison voltage generation circuit 120, and the output voltage of the comparison voltage generation circuit 120 can be compared with the output voltage of the drive voltage waveform generation circuit 110. It has become.

  Here, in the inkjet printer 10 of the fourth modified example, the printer control circuit 50 (see FIG. 4) associates two voltage values of “upper limit voltage value” and “lower limit voltage value” with each ejection port 200. Stored in advance in the ROM. When the printer control circuit 50 determines the ejection port 200 that ejects ink droplets based on the image data to be printed, the comparison voltage generation circuit 120 acquires the upper limit voltage value and the lower limit voltage value corresponding to the ejection port 200. At the same time, the lower limit voltage value (voltage value “Vd” in the example of FIG. 10A) is output from the terminal connected to the comparator Cd, and the upper limit voltage value (FIG. 10A) is output from the terminal connected to the comparator Cu. In the example of), the voltage value “Vu”) is output.

  In this way, the comparator Cu can compare the output voltage of the drive voltage waveform generation circuit 110 with the upper limit voltage value “Vu”, so that the output voltage of the drive voltage waveform generation circuit 110 exceeds the upper limit voltage value. The gate element 302 can be cut off. On the other hand, since the comparator Cd can compare the output voltage of the drive voltage waveform generation circuit 110 with the lower limit voltage value “Vd”, the output voltage of the drive voltage waveform generation circuit 110 falls below the lower limit voltage value “Vd”. If so, the gate element 302 is turned off. Accordingly, as shown in FIG. 10B, when the voltage of the drive voltage waveform is higher than the upper limit voltage value “Vu”, the gate element 302 is cut by the comparator Cu. On the other hand, when the voltage of the drive voltage waveform is lower than the lower limit voltage value “Vd”, the gate element 302 is disconnected by the comparator Cd. Therefore, the drive voltage waveform can be applied to the piezo element while the voltage of the drive voltage waveform is between the upper limit voltage value “Vu” and the lower limit voltage value “Vd”. As a result, as shown in FIG. 10B, a voltage waveform having a different amplitude from the drive voltage waveform output from the drive voltage waveform generation circuit 110 can be applied to the piezo element 204.

  Thus, if the drive voltage waveform generation circuit 110 and the piezo element 204 are disconnected when the output voltage of the drive voltage waveform generation circuit 110 is higher than the upper limit voltage value or lower than the lower limit voltage value, the upper limit voltage is reached. Since a voltage higher than the value or a voltage lower than the lower limit voltage value is not applied, as a result, a voltage waveform having a smaller amplitude than the drive voltage waveform can be applied to the piezo element 204. Therefore, if an upper limit voltage value and a lower limit voltage value are determined for each ejection port 200, a voltage waveform having an appropriate amplitude is applied to the piezoelectric element 204 of each ejection port 200 according to the characteristics of each ejection port 200. Therefore, it is possible to eject ink droplets of a uniform size while suppressing variations such as the size of the ink droplets due to the characteristics of each ejection port 200.

  Further, in the gate unit 300 of the fourth modification, when the voltage of the drive voltage waveform generation circuit 110 exceeds the upper limit voltage value or falls below the lower limit voltage value, the gate element 302 is immediately disconnected by the comparator Cu or the comparator Cd. Is done. For this reason, since the gate element control circuit 150 does not need to operate the gate element 302 at an accurate timing, the configuration of the gate element control circuit 150 can be simplified and the apparatus configuration of the inkjet printer 10 can be simplified. .

C-5. Fifth modification:
In the inkjet printer 10 of the above-described embodiment and the modified example, the gate element 302 of the ejection port 200 that ejects ink droplets is operated based on the gate timing data (or the upper limit voltage value and the lower limit voltage value) of the ejection port 200. Explained as a thing. However, not only the ejection port 200 that ejects ink droplets but also the ejection port 200 that does not eject ink droplets, the gate element may be operated based on the gate timing data (or the upper limit voltage value and the lower limit voltage value). .

  FIG. 11 is an explanatory diagram illustrating a state in which the gate element of the ejection port that does not eject ink droplets is operated according to the gate timing data. FIG. 11A illustrates gate timing data for an ejection port that does not eject ink droplets. At the ejection port 200, the ink in the ink chamber 202 is exposed to the outside air at the opening of the ejection port 200 (see FIG. 2), so that the ink near the opening is little by little while ejecting ink droplets. It may dry and increase the viscosity of the ink (thickening). For this reason, in the ejection port 200 that does not eject ink droplets, it is preferable to suppress the increase in the viscosity of the ink by moving the piezo element slightly to vibrate the ink in the ink chamber. Correspondingly, in the gate timing data for the ejection port that does not eject ink droplets, as shown in FIG. 11A, the gate element is in a conductive state ("ON" state) for a short time. (From the timing indicated as “t1” to the timing indicated as “t2” in FIG. 11A and from the timing indicated as “t3” to “t4”. Until the indicated timing).

  When the gate element is operated in accordance with such gate timing data, as shown in FIG. 11B, a voltage waveform in which the voltage slightly fluctuates in response to the gate element being in a conductive state for a short time. Since it can be applied to the piezo element 204, it is possible to slightly move the piezo element 204 to vibrate the ink in the ink chamber 202, thereby suppressing ink thickening. In this way, the nozzle 200 that does not eject ink droplets also obtains an appropriate voltage waveform to the piezo element 204 by acquiring gate timing data and operating the gate element in the same manner as the nozzle 200 that ejects ink droplets. Therefore, it is possible to apply a voltage waveform in the same manner to any of the ejection ports 200 without distinguishing between the ejection ports 200 that eject ink droplets and the ejection ports 200 that do not eject ink droplets. . Therefore, in order to drive the piezo element 204 of the ejection port 200 that does not eject ink droplets, there is no need to separately generate a dedicated drive voltage waveform, and the process performed by the drive voltage waveform generation circuit 110 and the printer control circuit 50. Can be simplified. In addition, since it is not necessary to provide a dedicated circuit for generating a voltage waveform for the ejection port 200 that does not eject ink droplets, the circuit configuration of the piezo element driving circuit 100 can be simplified. In addition, since the piezo element 204 of the ejection port 200 that ejects ink droplets and the piezo element 204 of the ejection port 200 that does not eject ink droplets can be driven by one drive voltage waveform, ejection that does not eject ink droplets Since it is not necessary to separately provide time for applying the voltage waveform to the piezo element 204 of the mouth 200, it is possible to shorten the time required for printing the image and print the image at high speed.

  Instead of acquiring the gate timing data, the upper limit voltage value and the lower limit voltage value are acquired as in the fourth embodiment (see FIG. 10), and the voltage of the drive voltage waveform is changed to the upper limit voltage value and the lower limit voltage. A drive voltage waveform may be applied to the ejection port 200 that does not eject ink droplets for a certain period between the voltage value. Even in such a case, if the upper limit voltage value and the lower limit voltage value are set so that the difference between the upper limit voltage value and the lower limit voltage value is small, a voltage with a small amplitude is applied to the piezo element 204 of the ejection port 200 that does not eject ink droplets. Since the waveform can be applied, it is possible to suppress the thickening of the ink in the ejection port 200 by slightly moving the piezo element 204. Of course, even in such a case, since the ejection port 200 that ejects ink droplets and the ejection port 200 that does not eject ink droplets can be driven in the same way, the circuit configurations of the printer control circuit 50 and the piezo element driving circuit 100 are not different. It can be kept simple.

  In the above, the ink jet printer equipped with the piezoelectric element driving circuit of the present embodiment has been described. However, the present invention is not limited to all the above embodiments, and can be implemented in various modes without departing from the gist thereof. Is possible. For example, the piezo element driving circuit of this embodiment may be mounted on a printing apparatus (so-called line head printer or the like) having a larger ejection head. In the case of such a printing apparatus, since a large number of ejection ports are provided as the ejection head becomes larger, it becomes more difficult to make the characteristics of the ejection ports uniform. In this respect, the piezoelectric element of this embodiment If a drive circuit is used, an appropriate voltage waveform can be applied according to the characteristics of each ejection port, so that high-quality images can be printed while suppressing variations in the size of ink droplets ejected from each ejection port. Is possible.

  In the above-described embodiments, the case where the piezo element of the ink jet printer is driven has been described as an example. However, the drive circuit of this embodiment can be applied to various devices that are driven according to the voltage. For example, the present invention can be applied to a display device that can operate with a voltage such as a liquid crystal panel or an organic EL panel. Even when such an apparatus is driven, it is possible to apply an appropriate voltage waveform to each of various elements such as a liquid crystal element and an organic EL element, thereby suppressing variation in operation of each element.

  DESCRIPTION OF SYMBOLS 10 ... Inkjet printer, 20 ... Carriage, 24 ... Jetting head, 30 ... Drive mechanism, 40 ... Platen roller, 50 ... Printer control circuit, 100 ... Piezo element drive circuit, 110 ... Drive voltage waveform generation circuit, 120 ... Comparison voltage generation Reference numeral 150 denotes a gate element control circuit, 200 denotes an ejection port, 202 denotes an ink chamber, 204 denotes a piezoelectric element, 300 denotes a gate unit, and 302 denotes a gate element.

Claims (6)

Voltage waveform output means for outputting a voltage waveform used for driving a plurality of capacitive loads;
Voltage waveform applying means for applying the voltage waveform to each of the plurality of capacitive loads by connecting each of the plurality of capacitive loads to the output of the voltage waveform output means; and
The voltage waveform application means connects the capacitive load and the output of the voltage waveform output means when the voltage waveform voltage is outside the voltage range defined for each of the plurality of capacitive loads. The voltage waveform different from each of the plurality of capacitive loads by connecting the capacitive load to the output of the voltage waveform output means when the voltage waveform voltage is within the voltage range. A capacitive load driving circuit which is means for applying a voltage. The capacitive load drive circuit according to claim 1,
The voltage waveform applying means causes current to flow into the capacitive load when the voltage waveform voltage rises higher than before the capacitive load is disconnected after the capacitive load is disconnected. The capacitive load is connected to the output of the voltage waveform output means via a rectifying element connected to the capacitive load in a direction that prevents the voltage load, and after the connection of the capacitive load is released, the voltage of the voltage waveform is When the capacitive load is lower than before disconnecting, the capacitive load is output to the voltage waveform via the rectifying element connected in a direction that prevents current from flowing out of the capacitive load. A capacitive load drive circuit which is means for connecting to the output of the means. Voltage waveform output means for outputting a voltage waveform used for driving the first capacitive load and the second capacitive load;
Voltage waveform applying means for applying the voltage waveform to the first capacitive load and the second capacitive load;
The voltage waveform applying means connects the first capacitive load and the output of the voltage waveform output means when the voltage waveform voltage is outside the first voltage range defined for the first capacitive load. When the voltage waveform voltage is within the first voltage range, the first capacitive load is connected to the output of the voltage waveform output means, while the voltage waveform voltage is When the load is determined as a capacitive load and is outside the range of the second voltage range in which at least part of the voltage range is different from the first voltage range, the second capacitive load and the output of the voltage waveform output means Disconnecting and connecting the second capacitive load to the output of the voltage waveform output means when the voltage waveform voltage is within the second voltage range; A capacitive load driving circuit which is means for applying the different voltage waveform to the second capacitive load. A capacitive load driving circuit according to any one of claims 1 to 3,
An injection nozzle for injecting a fluid;
An actuator that is connected to the capacitive load drive circuit as the capacitive load and is driven by the capacitive load drive circuit to cause the fluid to be ejected from the ejection nozzle.   A printing apparatus comprising the fluid ejection device according to claim 4. Outputting a voltage waveform used to drive the first capacitive load and the second capacitive load;
Applying the voltage waveform to the first capacitive load and the second capacitive load;
The step of applying the voltage waveform includes the step of applying the first capacitive load and the voltage waveform output means when the voltage of the voltage waveform is outside the first voltage range defined for the first capacitive load. When the connection with the output is released and the voltage waveform voltage is within the first voltage range, the first capacitive load is connected to the output of the voltage waveform output means, while the voltage waveform voltage is The second capacitive load and the voltage waveform output means when the second capacitive load is outside the second voltage range that is different from the first voltage range and is at least partly different from the first voltage range. When the voltage waveform voltage is within the second voltage range, the second capacitive load is connected to the output of the voltage waveform output means to disconnect the first capacitor. Capacitive negative, which is a step of applying different voltage waveforms to the capacitive load and the second capacitive load Driving method.

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