JP2011108710A - Semiconductor package - Google Patents

Abstract

【Task】
By reducing the number of components of the semiconductor package and the number of assembly steps, the assembly cost of the semiconductor package can be greatly reduced, and the thickness of the semiconductor package can be reduced. It is possible to provide a semiconductor package that achieves a thickness of a millimeter or less.
[Solution]
A lead frame, a substrate, a wire, and an adhesive, which are constituent members of a conventional semiconductor package, are unnecessary, and the semiconductor package can be thinned.
[Selection] Figure 2

Description

      The present invention relates to a semiconductor package.

Conventionally, as a structure of a semiconductor package using a metal lead frame as an external electrode,
An external terminal (pad) of the semiconductor chip and an external electrode (lead frame) used for secondary mounting are connected by a metal wire, and a portion excluding the external electrode is covered with a resin.

      The semiconductor package thus configured is used by being mounted on a printed circuit board as a single unit, and the mounting space requires a planar area of the semiconductor package, and the mounting density cannot be increased. Further, since a lead frame is used and a metal wire connection is required, the package assembly cost is high.

      A conventional semiconductor package has a package on package (POP) structure in which packages are stacked vertically to form one system. The ball grid array (BGA) type is the mainstream package used for POPs, but the structure is such that the semiconductor chip is mounted on the substrate (wiring board) and the wiring is deposited on the substrate and the semiconductor chip. These pads are connected with a metal wire and covered with a resin. The wiring on the substrate is electrically connected to a ball (an external electrode of the semiconductor package) provided on the lower surface of the substrate.

      The semiconductor package configured as described above requires a plurality of expensive components, and the thickness of the package becomes thick because a plurality of components are used (0.5 mm or more). The structure up to the stack is the mainstream.

      As described above, the conventional semiconductor package requires a plurality of components and is complicated because the assembly process is complicated. In order to increase the mounting density using a conventional semiconductor package, a POP structure in which BGAs are stacked is used. However, stacking BGA packages in two stages is a practical limit and mounting as expected. Density has not been achieved. The present invention has been made in view of the above points, and by reducing the number of constituent members and the number of assembly steps, the assembly cost of the semiconductor package can be greatly reduced, and further the thickness of the semiconductor package can be reduced. An object of the present invention is to provide a semiconductor package that can achieve a thickness of 1 millimeter or less even when a 10-layer POP is formed.

      The present invention is characterized by taking the following means in order to solve the above-mentioned problems. According to the first aspect of the present invention, when packaging the periphery of a semiconductor chip with an electrically insulating material in a semiconductor package, the package is packaged in a wider range than the size of the semiconductor chip in plan view, and the package is outside the range of the semiconductor chip. The gist of the present invention is to provide a structure in which a hole penetrating the front and back of the package is provided in the part, a metal film is attached to the wall surface of the hole, and the front and back of the package are electrically connected to each other by the wall surface of the hole. Therefore, the lead frame or substrate used in the conventional semiconductor package structure becomes unnecessary.

      According to a second aspect of the present invention, when packaging the periphery of a semiconductor chip with an electrically insulating material in a semiconductor package, the package is packaged in a wider range than the size of the semiconductor chip in plan view, and the package is outside the range of the semiconductor chip. A hole that penetrates the front and back of the package in the part, and a conductive material is embedded in the hole, and the structure is electrically connected by the conductive material embedded in the front and back of the package to form an external electrode. To do. Therefore, the lead frame or substrate used in the conventional semiconductor package structure becomes unnecessary.

      According to a third aspect of the present invention, in the semiconductor package, a conductive post is formed on the electrode pad on the surface of the semiconductor chip, a part of the post is exposed on the surface of the package, and the exposed portion and the first and second aspects are described. The gist is that the external electrodes thus made are electrically connected by wirings attached to the surface of the package. Therefore, since the metal wire used in the conventional semiconductor package structure is not used, the number of members of the semiconductor package and the number of assembly steps can be reduced, and the cost can be greatly reduced.

      The invention of claim 4 is that the metal film deposited on the wall surface of the hole penetrating the front and back surfaces of the semiconductor package is formed by ion plating, and the crystal state of the metal film is indefinite (such as amorphous). And With the ion plating method, it is easy to deposit a metal film on the wall surface of the through hole, and the adhesion strength of the deposited metal film is stronger than the metal film deposited by the printing method or the plating method. .

      The gist of the invention of claim 5 is that the crystalline state of the metal film formed by ion plating of the wiring material to be deposited on the surface of the semiconductor package is indefinite (such as amorphous). With the ion plating method, it is easy to deposit a metal film on the surface of the package, and the adhesion strength of the deposited metal film is stronger than the metal film deposited by a printing method or a plating method.

      According to the first and second aspects of the present invention, since the external electrode for secondary mounting is provided between the semiconductor chip and the outer edge of the package, the external lead protruding outside the package becomes unnecessary. This eliminates the need for the metal lead frame and substrate that were required for conventional semiconductor packages, reduces the number of members and assembly processes that make up the semiconductor package, and achieves significant cost reductions. Since the straight is not used, the package thickness can be reduced (the semiconductor package thickness is 0.1 mm or less).

According to invention of Claim 3, the metal wire which was indispensable for the structure of the conventional semiconductor package becomes unnecessary. For this reason, compared with the conventional semiconductor package, the number of members constituting the semiconductor package and the number of assembly processes are reduced, and a significant cost reduction is achieved.

      According to the invention described in claim 4, the metal film is deposited on the wall surface of the hole penetrating the front and back of the semiconductor package by the ion plating method. The adhesion strength of the metal film deposited by the ion plating method is It is possible to provide a semiconductor package that is stronger and more reliable than a metal film deposited by a printing method or a plating method.

      According to the invention described in claim 5, the wiring material to be deposited on the surface of the package is deposited by the ion plating method. The adhesion strength of the metal film deposited by the ion plating method is determined by the printing method or It is possible to provide a semiconductor package that is stronger and more reliable than a metal film deposited by plating. Furthermore, if the ion plating method is used, the line and space (the line width and the distance between the lines) of the wiring can be miniaturized as compared with the conventional printing method.

It is a top view which shows the example of the semiconductor package concerning this invention. It is a figure which shows the example of the semiconductor package concerning this invention. It is the figure which comprised the POP system with the semiconductor package concerning this invention. It is a figure which shows the Example of the assembly process of the semiconductor package concerning this invention. It is a figure which shows the example of the semiconductor package which uses a lead frame. It is a figure which shows the example of the semiconductor package which uses a substrate. It is the figure which comprised the POP system with the conventional package.

    The semiconductor package 1 according to the present invention includes a semiconductor chip 2, packaging resin 3, front and back through-holes 4, hole wall surface coating films 5, electrode pads 6, posts 7, wirings 8, and external electrodes 9.

      A conductive post 7 is erected on the electrode pad 6 provided on the semiconductor chip 2 and is packaged with the packaging resin 3 so that the back surface without the circuit of the semiconductor chip 2 is exposed. At this time, the post 7 A part of is exposed from the surface of the package.

      The packaging resin 3 is packaged in a range that is considerably larger than the size of the semiconductor chip 2 in plan view, and a front and back through hole 4 is provided between the semiconductor chip 2 and the end of the package, and the inner surface of the through hole The hole wall surface coating film 5 is deposited on a conductive material. The same effect can be obtained by embedding a conductive material in the through hole.

External electrodes 9 are provided on the front and back edges of the front and back through-holes 4 with a conductive material that is electrically connected through the hole wall surface coating film 5. The post 7 and the external electrode 9 are electrically connected by the deposited wiring 8.

      As one embodiment of the method of manufacturing the semiconductor package 1 according to the present invention, the adhesive tape 22 is attached to the frame 21 in a tensioned state (no slack), and the post 7 is formed on the adhesive tape 22. The finished and separated semiconductor chip 2 is mounted. At this time, the semiconductor chip 2 is bonded and fixed to the adhesive tape 22, and the distance between adjacent chips is at least larger than the outer size of the semiconductor package 1.

      Further, the semiconductor chip 2 and the post 7 are covered with the packaging resin 3, and after the resin is cured, the frame 21 and the adhesive tape 22 are removed, and the surface is scraped until a part of the post 7 is exposed.

      Thereafter, the front and back through-holes 4 of the package are provided at the position of the external electrode 9, and the hole wall surface film 5, wiring 8, and external electrode 9 are formed by ion coating.

      Further, the semiconductor package 1 is completed by separating each of the adjacent semiconductor chips 2.

The structure of the semiconductor package 1 according to the present invention eliminates the need for a lead frame and a substrate as compared with the conventional semiconductor package (FIGS. 4 and 5), so that the number of components is reduced and the thickness can be reduced to 1/5 or less. In addition, the wire bonding process is not required, and the cost can be greatly reduced and the reliability can be improved.

DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Semiconductor chip 3 Packaging resin 4 Front and back through-hole 5 Hole wall surface coating film 6 Electrode pad 7 Post 8 Wiring 9 External electrode 10 Lead frame 11 Wire 12 Stage 13 Adhesive 14 Substrate 15 Solder for mounting Ball 16 Package range 17 Separated semiconductor package 18 according to the present invention 10 10-layer POP
19 Two-tiered POP

Claims (5)

      When packaging the periphery of a semiconductor chip with an electrically insulating material, it is packaged in a wider range than the size of the semiconductor chip in plan view, and a hole that penetrates the front and back of the package is formed in the package part outside the range of the semiconductor chip. A semiconductor package having a structure in which a metal film is attached to a wall surface of the hole and the front and back surfaces of the package are electrically connected to each other by the wall surface of the hole to form an external electrode.       When packaging the periphery of a semiconductor chip with an electrically insulating material, it is packaged in a wider range than the size of the semiconductor chip in plan view, and a hole that penetrates the front and back of the package is formed in the package part outside the range of the semiconductor chip. A semiconductor package having a structure in which a conductive material is provided in the hole and electrically connected by a conductive material in which the front and back surfaces of the package are embedded in the hole to form an external electrode.       A conductive post is formed on the electrode pad on the surface of the semiconductor chip described in claim 1 and claim 2, and a part of the post is exposed on the surface of the package. The exposed portion and claim 1 and claim 2 A semiconductor package characterized in that the described external electrode is electrically connected by wiring attached to the surface of the package.       2. The semiconductor package according to claim 1, wherein the metal film deposited on the wall surface of the hole penetrating the front and back surfaces of the package is formed by an ion plating method, and the crystal state of the metal film is indefinite (such as amorphous).       4. The semiconductor package according to claim 3, wherein a crystal state of the metal film formed by ion plating of a wiring material to be deposited on the surface of the package is indefinite (such as amorphous).

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