JP2011108797A - Trench type power mos transistor and manufacturing method of the same - Google Patents

Abstract

In a power MOS transistor, not only has a high breakdown voltage, a high output current, and a high operating speed, but also a horizontal structure, the same chip as a general integrated circuit manufactured in a CMOS manufacturing process. Align on top.
A trench type power MOS transistor of the present invention includes a trench type gate region including a gate conductor (312) and an insulating layer (310). The insulating layer 310 forms a thin sidewall region between the gate conductor 312 and the well region 308, forms a thick sidewall region between the gate conductor 312 and the double-diffused doping region 306, and A thick bottom region is formed between the gate conductor 312 and the deep well region 304.
[Selection] Figure 3

Description

  The present invention relates to a MOS transistor and a method for manufacturing the same, and more particularly, to a trench-type power MOS transistor and a method for manufacturing the same.

  The power MOS transistor is a special MOS transistor and is exclusively used for power supply and switching to the integrated circuit. For this reason, the power MOS transistor is required to have an ability to operate at a high voltage. A general power MOS transistor achieves the purpose of upsizing by being manufactured in a manufacturing process of a complementary metal oxide transistor (CMOS) so that it can operate at a high voltage. On the other hand, the power MOS transistor is also required to output a large current. Accordingly, in general manufacturing, a power MOS transistor is often constructed by integrating several thousand to several hundred thousand transistor cells. Among these, each transistor cell outputs a small current, but this integrated power MOS transistor can output a large current. However, the power MOS transistor manufactured by this manufacturing method has a large area and is not accepted by the industry.

  In order to reduce the area of power MOS transistors, vertical diffusion MOS (vertical-diffused MOS, VDMOS) transistors have appeared in the industry. FIG. 1 shows a schematic cross-sectional view of a VDMOS transistor. Unlike the conventional planar CMOS transistor, current flows in the VDMOS transistor in the vertical direction. As shown in FIG. 1, the drain region of the VDMOS transistor 100 is provided at the top of the VDMOS transistor 100, and the source region of the VDMOS transistor 100 is provided at the bottom of the VDMOS transistor 100. In the structure of FIG. 1, the VDMOS transistor 100 has a high breakdown voltage and a high output current.

  FIG. 2 shows a schematic cross-sectional view of another type of trench type power MOS transistor, that is, a UMOS transistor. As shown in FIG. 2, the UMOS transistor 200 is thus named from a U-shaped gate oxide. The UMOS transistor 200 has a trench-type gate extending downward, and the current of the UMOS transistor 200 flows in the vertical direction, and the drain region of the UMOS transistor 200 is provided at the top of the UMOS transistor 200. The source region of the UMOS transistor 200 is provided at the bottom of the UMOS transistor 200.

  However, since the MOS transistor having the vertical structure described above cannot be matched on the same chip as a general integrated circuit manufactured in a CMOS manufacturing process, it causes an increase in manufacturing complexity and manufacturing cost. I will. Therefore, in order to provide not only a high breakdown voltage, a high output current and a high operating speed, but also a horizontal structure, it is matched on the same chip as a general integrated circuit manufactured in a CMOS manufacturing process. There is a need in the industry for power MOS transistors that can be used.

  A trench power MOS transistor according to an embodiment of the present invention includes a drain region, a double diffusion doping region, a trench gate region, a source region, a well region, a deep well region, and a substrate region. ing. The drain region has characteristics of the first conductivity type and is connected to the drain electrode. The double-diffused doping region has characteristics of the first conductivity type and is provided below the drain region. The trench-type gate region extends to the double-diffused doping region, and includes a gate conductor and an insulating layer for isolating the gate conductor. The source region has characteristics of the first conductivity type and is connected to a source electrode. The well region has characteristics of the second conductivity type and is provided below the source region. The deep well region has characteristics of the first conductivity type and is provided below the double diffusion doping region and the well region. The base material region is provided below the deep well region. The insulating layer forms a thin sidewall region between the gate conductor and the well region, and forms a thick sidewall region between the gate conductor and the double diffusion doping region, and the gate A thickest bottom region is formed between the conductor and the deep well region, and the drain electrode and the source electrode are provided on the upper surface of the trench type power MOS transistor.

  A method for manufacturing a trench power MOS transistor according to an embodiment of the present invention includes a step of forming a deep well region having a first conductivity type characteristic on a base material region, and a step having the first conductivity type characteristic. Forming a drain region of a heavily doped doping region on the deep well region; forming a trench region by etching on a sidewall of the double diffused doping region; and embedding an insulating material in the trench region. A gate region is formed by etching outside the insulating material with respect to the double diffusion doping region, and the insulating material is embedded between the gate region in the trench region and the double diffusion doping region. An insulating material between the gate region and the deep well region in the trench region. And a step of embedding a gate conductor in the gate region, and a well region having a second conductivity type in the vicinity of the gate region and on the deep well region. Forming a drain region having the characteristics of the first conductivity type on the doping region of the double diffusion, and forming a source region having the characteristics of the first conductivity type on the well region. Forming.

  The trench type power MOS transistor of the present invention has a high breakdown voltage, a high output current and a high operating speed due to a special trench type structure. In addition, since the trench type power MOS transistor of the present invention has a horizontal structure, it can be matched on the same chip as a general integrated circuit manufactured in a CMOS manufacturing process, improving the practicality, Manufacturing costs can be reduced.

Cross-sectional schematic diagram of VDMOS transistor Schematic cross section of UMOS transistor Schematic cross-sectional view of a trench type power MOS transistor in an embodiment of the present invention Partially enlarged view of a trench type power MOS transistor in an embodiment of the present invention Schematic of arrangement structure of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention Manufacturing process diagram of trench type power MOS transistor in an embodiment of the present invention

  FIG. 3 is a schematic sectional view of a trench type power MOS transistor according to an embodiment of the present invention. As shown in FIG. 3, the trench power MOS transistor 300 includes a base region 302, a deep well region 304, a double diffusion doping region 306, a well region 308, an insulating layer 310, and a gate conductor 312. A drain region 314, a source region 316, a body region 318, a metal silicide layer 320, an interlayer dielectric layer 322, a first layer metal layer 324, an intermetal dielectric layer 326, and an uppermost metal layer 328. And.

  The trench type power MOS transistor 300 shown in FIG. 3 is an N type transistor. However, since those skilled in the art can easily convert to a P-type transistor, this is also included in the present invention. As shown in FIG. 3, the drain region 314 has N-type conductivity type characteristics and is connected to the drain electrode. The double-diffused doping region 306 has characteristics of the N-type conductivity type and is provided below the drain region 314. In the double-diffused doping region 306, the region near the drain region 314 preferably has a higher ion concentration than the region away from the drain region 314. The insulating layer 310 extends to the double-diffused doping region 306 to isolate the gate conductor 312. The insulating layer 310 and the gate conductor 312 form a trench-type gate region, and the trench-type gate region surrounds the well region 308 in the horizontal direction, and the gate electrode faces the outside of the drain region 314. The gate conductor 312 is connected. The source region 316 has the N-type conductivity type characteristics, surrounds the main body region 318, and is connected to the source electrode. The well region 308 has a P-type conductivity type and is provided below the source region 316. The deep well region 304 has the characteristics of the N-type conductivity type, and is provided below the double diffusion doping region 306 and the well region 308. The base material region 302 has P-type conductivity type characteristics and is provided below the deep well region 304. The metal silicide layer 320 is interposed between the drain region 314, the source region 316, the main body region 318, and the plurality of electrodes. The interlayer dielectric layer 322 is provided above the metal silicide layer 320. The first metal layer 324 is for connecting the plurality of electrodes to the uppermost metal layer 328. The intermetal dielectric layer 326 is interposed between the first metal layer 324 and the uppermost metal layer 328.

  As shown in FIG. 3, the insulating layer 310 forms a thin sidewall region between the gate conductor 312 and the well region 308, and the gate conductor 312, the double-diffused doping region 306, and the like. A thick side wall region is formed, and a thick bottom region is formed between the gate conductor 312 and the deep well region 304. The drain electrode, the source electrode, and the gate electrode are provided on the upper surface of the trench type power MOS transistor 300.

FIG. 4 is a partially enlarged view of the trench type power MOS transistor 300 of FIG. As shown in FIG. 4, when the trench power MOS transistor 300 is conductive, a channel to the source region 316 is formed along the outer wall of the insulating layer 310 in the drain region 314. As shown in FIG. 4, since the effective length L _off of the channel is very short and corresponds to the depth of the well region, the resistance value of the channel can be reduced. Further, since the ion doping concentration of the double diffusion doping region forming the channel is high, the resistance value is also small. Therefore, since the trench type power MOS transistor 300 has a low resistance value in conduction, a high output current can be provided.

  On the other hand, the thickness of the thick sidewall region between the gate conductor 312 and the double diffusion doping region 306 in the insulating layer 310 can increase the breakdown voltage of the trench type power MOS transistor 300. The breakdown voltage of the trench type power MOS transistor 300 can also be increased by the thickness of the lowermost region between the gate conductor 312 and the deep well region 304 in the insulating layer 310. Accordingly, the trench power MOS transistor 300 can provide a high breakdown voltage. In practice, a desired breakdown voltage can be obtained by adjusting the thickness of the thick sidewall region and the thickest bottom region.

  If a breakdown voltage of less than 100 V is desired, the depth A of the insulating layer 310 is less than 2 μm, the width B of the insulating layer 310 is less than 2 μm, and the depth C of the gate conductor 312 is 1 to 1. More preferably, the thickness D of the thickest bottom region is set to 0.02 to 1 μm, and the thickness E of the thick side wall region is set to 0.2 to 1 μm. If a breakdown voltage exceeding 100 V is desired, the depth A of the insulating layer 310 is greater than 2 μm, the width B of the insulating layer 310 is greater than 3 μm, and the depth C of the gate conductor 312 is 1. More preferably, the thickness D is larger than 6 μm, the thickness D of the thickest bottom region is larger than 0.6 μm, and the thickness E of the thick side wall region is larger than 1 μm.

Please refer to FIG. 4 again. Since the effective length of the channel of the trench type power MOS transistor 300 is considerably short, the effective capacitance C _gb from the main body region 318 to the gate conductor 312 becomes considerably small. In addition, since the insulating layer 310 has a considerably thick sidewall region, the C _{gd of the} gate conductor 312 is considerably reduced from the drain region 314. Therefore, the trench power MOS transistor 300 has a high operating speed.

  FIG. 5 shows a schematic diagram of an arrangement structure of the trench type power MOS transistor 300. As shown in FIG. 5, the insulating layer 310 surrounds the drain region 314. The source region 316 surrounds the body region 318. The gate conductor 312 separates the drain region 314 and the source region 316.

  6 to 30 show manufacturing process diagrams of the trench type power MOS transistor in the embodiment of the present invention. The manufacturing process shown in FIGS. 6 to 30 is an N-type transistor manufacturing process. However, those skilled in the art can easily switch to the manufacturing process of the P-type transistor, and this is also included in the present invention.

  As shown in FIG. 6, first, N-type ions are doped on the P-type substrate 302 to form the deep well region 304. As shown in FIG. 7, a double-doping doping region patterning mask 700 is formed on the substrate region 302. As shown in FIG. 8, double diffusion doping drive-in is performed on a portion not covered with a mask to form the double diffusion doping region 306. Is about 900-1000 ° C. As shown in FIG. 9, the patterning mask 700 is removed, and a silicon oxide pad layer / pad nitride 900 is formed in an effective region, and boron-doped silicate A hard mask 910 that may be a salt glass (BSG) is formed on the silicon oxide pad layer / silicon nitride pad layer 900. As shown in FIG. 10, a trench region is formed on the side wall of the double-diffused doping region 306 by etching. As shown in FIG. 11, the hard mask 910 is removed. As shown in FIG. 12, the insulating layer 310 is deposited in the trench region, and the insulating layer 310 is polished by a chemical mechanical polishing (CMP) technique. Of these, the insulating material is an oxide. It is also good. As shown in FIG. 13, a gate conductor patterning mask 1300 is formed above the double-diffused doping region 306. As shown in FIG. 14, the insulating layer 310 is etched to form a gate region. Among these, the insulating layer 310 is embedded between the gate region and the double diffusion doping region 306. And a thick bottom region in which the insulating layer 310 is buried between the gate region and the deep well region 304. More preferably, the etching depth is about 1 to 2 μm.

  As shown in FIG. 15, the patterning mask 1300 is removed, and a gate oxide or insulating layer is grown or deposited on the sidewall of the trench region, and the gate conductor 312 made of polysilicon or metal is Deposit in the gate region. Next, as shown in FIG. 16, the gate conductor 312 is etched. As shown in FIG. 17, the insulating layer 310 is deposited on the etched portion of the gate conductor 312, and the insulating layer 310 is polished by chemical mechanical polishing. Of these, the insulating material may be an oxide. As shown in FIG. 18, the silicon oxide pad layer / silicon nitride pad layer 900 is removed. As shown in FIG. 19, the well region 308 is formed by doping with P-type ions. As shown in FIG. 20, a source / drain patterning mask 2000 is formed at the source / drain location, and N-type ion doping is performed to form the drain region 314 and the source region 316. As shown in FIG. 21, the patterning mask 2000 is removed to form a main body patterning mask 2100, and ion doping is performed to form the main body region 318. As shown in FIG. 22, the patterning mask 2100 is removed, and the bonding surface is annealed to form the metal silicide layer 320, which can be a metal silicide of titanium or cobalt. Of these, the annealing temperature may be 800 to 1000 ° C. As shown in FIG. 23, the interlayer dielectric layer 322 is formed on the metal silicide layer 320, and a contact patterning mask 2300 is formed on the interlayer dielectric layer 322, which can be made of borosilicate glass. .

  As shown in FIG. 24, contact etching is performed. As shown in FIG. 25, the patterning mask 2300 is removed, and metal tungsten is deposited at the location of contact etching to form source, drain and gate contacts, and the plurality of contacts are subjected to a chemical mechanical polishing technique. Polish with. As shown in FIG. 26, the first metal layer 324 is deposited on the interlayer dielectric layer 322, and a patterning mask 2600 for the first metal layer is formed at the plurality of contacts. As shown in FIG. 27, the first metal layer 324 is etched and the patterning mask 2600 is removed. As shown in FIG. 28, the intermetal dielectric layer 326, which can be made of borosilicate glass, is deposited on the first metal layer 324 and the interlayer dielectric layer 322. As shown in FIG. 29, a via hole patterning mask is formed on the intermetal dielectric layer 326. Thereafter, contact etching is performed to remove the patterning mask, and metal tungsten is deposited to form via holes on the plurality of contacts. As shown in FIG. 30, the uppermost metal layer 328 is formed on the intermetal dielectric layer 326, and a patterning mask is formed on the uppermost metal layer 328. Etching is performed and the patterning mask is removed.

  The technical contents and technical features of the present invention have been disclosed as described above. However, those skilled in the art are familiar with various technical ideas of the present invention based on the teachings and disclosure of the present invention. Substitutions and additions can be made. Accordingly, the scope of protection of the present invention is not limited to that disclosed in the examples, and includes various substitutions and additions that are not different from the present invention, and is included in the scope of the appended claims. is there.

100 VDMOS transistor 200 UMOS transistor 300 Trench-type power MOS transistor 302 Base region 304 Deep well region 306 Double diffusion doping region 308 Well region 310 Insulating layer 312 Gate conductor 314 Drain region 316 Source region 318 Body region 320 Metal silicide Layer 322 Interlayer dielectric layer 324 First layer metal layer 326 Intermetal dielectric layer 328 Top layer metal layer 700, 1300, 2100, 2300, 2600 Patterning mask 900 Silicon oxide pad layer / silicon nitride pad layer 910 Hard mask

Claims (20)

A drain region having characteristics of the first conductivity type and connected to the drain electrode;
A double-diffused doping region provided with characteristics of the first conductivity type and provided below the drain region;
A trench-type gate region comprising: a gate conductor; and an insulating layer extending to the double-diffused doping region and being isolated from the gate conductor;
A source region having the characteristics of the first conductivity type and connected to a source electrode;
A well region having characteristics of a second conductivity type and provided below the source region;
A deep well region having the characteristics of the first conductivity type and provided below the double diffusion doping region and the well region;
A base material region provided below the deep well region;
A trench type power MOS transistor comprising:
The insulating layer forms a thin sidewall region between the gate conductor and the well region, forms a thick sidewall region between the gate conductor and the double diffusion doping region, and A trench type characterized in that a thickest bottom region is formed between the gate conductor and the deep well region, and the drain electrode and the source electrode are provided on an upper surface of the trench type power MOS transistor. Power MOS transistor.   2. The trench according to claim 1, wherein the trench-type gate region includes a gate electrode that surrounds the well region in a horizontal direction and is connected to the gate conductor facing the outside of the drain region. Type power MOS transistor.   The depth of the trench gate region is less than 2 μm, the width of the trench gate region is less than 2 μm, the depth of the gate conductor is 1 to 2 μm, and the thickness of the thickest bottom region is 0.02 to 2. The trench type power MOS transistor according to claim 1, wherein the thickness is set to 1 [mu] m and the thickness of the thick side wall region is set to 0.2 to 1 [mu] m.   The depth of the trench type gate region is greater than 2 μm, the width of the trench type gate region is greater than 3 μm, the depth of the gate conductor is greater than 1.6 μm, and the thickness of the thickest bottom region is 0.6 μm. 2. The trench type power MOS transistor according to claim 1, wherein the thickness is larger and the thickness of the thick side wall region is larger than 1 μm.   2. The trench type power MOS transistor according to claim 1, wherein in the double diffusion doping region, a region closer to the drain region has a higher ion concentration than a region away from the drain region.   2. The trench type power MOS transistor according to claim 1, wherein upper surfaces of the drain region and the source region are isolated by the gate conductor.   2. The trench type power MOS transistor according to claim 1, further comprising a main body region surrounded by the source region.   2. The trench type power MOS transistor according to claim 1, further comprising a metal silicide layer interposed between the plurality of electrodes, the drain region, and the source region.   9. The trench type power MOS transistor according to claim 8, further comprising an interlayer dielectric layer provided on the metal silicide layer.   10. The trench type power MOS transistor according to claim 9, further comprising an intermetal dielectric layer provided on the interlayer dielectric layer. Forming a deep well region having a first conductivity type characteristic on the substrate region;
Forming a drain region of a double-diffusion doped region having the characteristics of the first conductivity type on the deep well region;
Etching a trench region on a sidewall of the double-diffused doping region; and
Embedding an insulating material in the trench region;
A gate region is formed by etching outside the insulating material with respect to the double diffusion doping region, and the insulating material is embedded between the gate region and the double diffusion doping region in the trench region. Providing a thick sidewall region and having a thick bottom region embedded with an insulating material between the gate region and the deep well region in the trench region;
Embedding a gate conductor in the gate region;
Forming a well region having characteristics of a second conductivity type in the vicinity of the gate region and on the deep well region;
Forming a drain region having the characteristics of the first conductivity type on the double-diffused doping region;
Forming a source region having the characteristics of the first conductivity type on the well region. A method of manufacturing a trench type power MOS transistor, comprising:   12. The manufacturing method according to claim 11, wherein an etching depth of the gate region is 1 to 2 [mu] m.   The method according to claim 11, wherein the double diffusion doping region is formed by a doping drive-in technique having a temperature of 900 to 1000 ° C.   12. The manufacturing method according to claim 11, wherein a material of the gate conductor is either polysilicon or metal.   A metal silicide layer is formed on the source region and the drain region by annealing the bonding surface, wherein the annealing temperature is 800 to 1000 ° C., and the metal silicide is a metal of titanium or cobalt. The method according to claim 11, further comprising a step of being a silicide.   The method according to claim 15, further comprising: forming the interlayer dielectric layer made of borosilicate glass on the metal silicide layer.   The method according to claim 16, further comprising: forming a first metal layer on the interlayer dielectric layer.   The manufacturing method according to claim 17, further comprising: forming an intermetallic dielectric layer made of borosilicate glass on the first metal layer.   The manufacturing method according to claim 18, further comprising: forming a top metal layer on the intermetal dielectric layer.   The method further comprises: performing contact etching on the source region and the drain region, and depositing the metal tungsten at a location of contact etching to form contacts of the source region and the drain region. 11. The production method according to 11.

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