JP2011108750A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device capable of detecting cracks in a semiconductor substrate and a method for manufacturing the same are provided.
A semiconductor device includes a first conductivity type semiconductor substrate, and a first exposed portion and a second exposed portion exposed to the outside. The semiconductor substrate 10 includes a first conductivity type first semiconductor region 12 and a second conductivity type second semiconductor region 13A opposite to the first conductivity type. A PN junction is formed between the first semiconductor region 12 and the second semiconductor region 13A. The first semiconductor region 12 and the second semiconductor region 13A have the first exposed portion 26 and the second exposed portion 26, respectively, so that the diode characteristics of the PN junction can be measured via the first exposed portion 26 and the second exposed portion 26. Connected to. The second semiconductor region 13 </ b> A is formed in a strip shape extending along the outer periphery 11 of the semiconductor substrate 10. The outer end of the second semiconductor region 13 </ b> A is located inside the outer peripheral end of the semiconductor substrate 10.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device, and more particularly to detection of a crack in a semiconductor device.

  A substrate called a circular wafer includes a large number of chip regions each corresponding to a semiconductor device (chip). A semiconductor circuit is formed in each chip region, and a semiconductor device is manufactured through a dicing process for separating these chip regions. In order to prevent the influence of dicing from affecting the semiconductor circuit, it is desirable to increase the distance between the semiconductor circuit and the scribe line. However, in recent years, there is a tendency that the distance from the outer periphery of the chip to the semiconductor circuit is shortened, such as by forming a semiconductor circuit under the bonding pad.

  As the distance between the scribe line and the semiconductor circuit is shortened, cracks generated on the outer periphery of the chip during dicing easily reach the semiconductor circuit, and problems such as deterioration in electrical characteristics and reliability of the semiconductor circuit are likely to occur.

  Conventionally, cracks have been detected by visual inspection using the naked eye or a microscope. In the appearance inspection, a fine crack may be overlooked, and there is a problem that a chip having a crack is regarded as a non-defective product. There is a need for an inspection method that can easily and reliably remove cracked chips.

  Patent Document 1 discloses a technique capable of electrically detecting a crack. FIG. 1 shows a double barrier 201 disclosed in US Pat. The double barrier 201 is formed in the vicinity of the chip end portion in the chip in order to prevent the expansion of the crack and the movement of the contamination via the crack. The integrity of the double barrier 201 can be monitored. Double barrier 201 is formed in a low dielectric constant (low k) material and provides a continuous electrical path from the top metal layer to the bottom metal layer below and from the top metal layer to the bottom metal layer below. Including via pass to bring. If the double barrier 201 cannot prevent the crack from expanding, the crack will pass through the double barrier 201, which will have a detectable effect on the electrical properties of the double barrier 201. By connecting the monitoring device 202 to the double barrier 201 and measuring the magnitude of capacitance and / or resistance, the effect can be monitored and detected.

  According to the study of the present inventor, in the technique disclosed in Patent Document 1, since the double barrier is formed from the wiring layer from the uppermost metal to the lowermost metal and vias connecting them, the semiconductor substrate It is difficult to detect cracks that have occurred.

    According to the study of the present inventor, in the technique disclosed in Patent Document 1, since a double barrier is provided on the outer peripheral portion of the chip, it is difficult to detect a crack generated in the chip. Furthermore, since the double barrier is formed from all the wiring layers from the lowermost layer metal to the uppermost layer metal and vias connecting them, the double barrier and the other wiring are crossed when the double barrier is crossed. A part of the wiring layer needs to be removed, and the wiring arrangement is restricted. Therefore, it is difficult to provide a double barrier other than the outer periphery of the chip.

JP 2004-214626 A

  There is a demand for a semiconductor device capable of detecting cracks in a semiconductor substrate and a manufacturing method thereof.

  The means for solving the problem will be described below using the numbers used in the (DETAILED DESCRIPTION). These numbers are added to clarify the correspondence between the description of (Claims) and (Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  The semiconductor device according to the present invention includes a first conductivity type semiconductor substrate (10), a first exposed portion (26, 10b) and a second exposed portion (26, 10b) exposed to the outside. The semiconductor substrate (10) includes a first conductivity type first semiconductor region (12) and a second conductivity type second semiconductor region (13A, 13C) opposite to the first conductivity type. A PN junction is formed between the first semiconductor region (12) and the second semiconductor region (13A, 13C). The first semiconductor region (12) and the second semiconductor region (13A, 13C) are configured so that the diode characteristics of the PN junction can be measured through the first exposed portion (26, 10b) and the second exposed portion (26, 10b). ) Are connected to the first exposed portion (26, 10b) and the second exposed portion (26, 10b), respectively. The second semiconductor regions (13A, 13C) are formed in a strip shape extending along the outer periphery (11) of the semiconductor substrate (10). The outer end of the second semiconductor region (13A, 13C) is located inside the outer peripheral end of the semiconductor substrate (10).

  The method of manufacturing a semiconductor device according to the present invention includes a step (S1) of processing a first conductivity type semiconductor wafer including a plurality of chip regions, and a step of separating the plurality of chip regions into individual chip regions (10) by dicing (S2). And a step (S3) of inspecting the chip region (10) for cracks. In the processing step (S1), a second conductivity type opposite to the first conductivity type is formed in the chip region (10) so that a PN junction is formed between the first conductivity type and the first semiconductor region (12). Forming a second semiconductor region (13A, 13C). The second semiconductor regions (13A, 13C) have a strip shape extending along the outer periphery (11) of the chip region (10), and the outer ends of the second semiconductor regions (13A, 13C) are after dicing. It is formed so as to be located inside the outer peripheral edge of the chip region. The step of inspecting (S3) includes a step of electrically measuring the diode characteristics of the PN junction and a step of determining the presence or absence of cracks based on the diode characteristics.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can detect the crack of a semiconductor substrate, and its manufacturing method are provided.

FIG. 1 is a cross-sectional view of a conventional double barrier. FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view of a general wiring lead pad. FIG. 5 is a block diagram of the inspection apparatus. FIG. 6 is a graph showing an example of diode characteristics measured by the inspection apparatus. FIG. 7 is a flowchart of the semiconductor device manufacturing method according to the first embodiment. FIG. 8 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention.

  With reference to the accompanying drawings, embodiments for carrying out a semiconductor device and a manufacturing method thereof according to the present invention will be described below.

(First embodiment)
FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention. The semiconductor device includes a P-type semiconductor substrate 10, transistors 50 </ b> A and 50 </ b> B formed on the semiconductor substrate 10, a P-type region extraction pad 41 disposed around the upper surface of the semiconductor device, and an N-type region. A lead pad 42 and a general wiring lead pad 43 are provided. The P-type region lead pad 41, the N-type region lead pad 42, and the general wiring lead pad 43 are bonding pads. In the semiconductor substrate 10, an N-type region 13A is formed to detect cracks. A PN junction is formed between the P-type region 12 and the N-type region 13A of the semiconductor substrate 10. The P-type region lead pad 41 is connected to the P-type region 12, and the N-type region lead pad 42 is connected to the N-type region 13A. Each general wiring lead pad 43 is used for normal wiring and is connected to an internal circuit of a semiconductor device such as the transistor 50A or the transistor 50B. The internal circuit is, for example, a transistor, a diode, a sub-contact, or an ESD (Electrostatic Discharge) protection element. The transistors 50A and 50B are disposed inside the outer periphery of the semiconductor device and are surrounded by the N-type region 13A.

  For convenience of explanation, the P-type region lead pad 41 and the N-type region lead pad 42 are arranged at opposite positions of the semiconductor device as shown in FIG. As long as connection is possible, it may be arranged at another position. Further, when flip-chip mounting is applied to the semiconductor device, the P-type region lead pad 41, the N-type region lead pad 42, and the general wiring lead pad 43 can be arranged in the central portion of the upper surface of the semiconductor device.

  N-type region 13A has a strip shape extending along outer periphery 11 of semiconductor substrate 10 forming the rectangular outer periphery of the semiconductor device. The N-type region 13 </ b> A preferably extends as long as possible along the outer periphery 11 so that cracks that progress from the outer periphery 11 toward the inside of the semiconductor substrate 10 can be easily detected. However, considering the adverse effects of the N-type region 13A forming a closed loop, the N-type region 13A is formed over 3/4 of the outer periphery 11 so as not to form a closed loop (for example, the outer periphery 11) is preferable. In the case where adverse effects are allowed, the N-type region 13A may form a closed loop as shown in FIG. The N-type region 13 </ b> A may be formed over less than 3/4 of the outer periphery 11, for example, over 1/2 of the outer periphery 11.

  FIG. 3 is a cross-sectional view of the semiconductor device according to the present embodiment taken along the line A-A ′ of FIG. 2. The semiconductor device includes a semiconductor substrate 10, a wiring formation layer 20 formed on the semiconductor substrate 10, and a cover film 30 formed on the wiring formation layer 20. The semiconductor substrate 10 includes a front surface 10a and a back surface 10b on the opposite side. The wiring formation layer 20 is formed on the surface 10 a and includes an interlayer insulating film 28. An element isolation region 16 is formed in the vicinity of the surface 10 a of the semiconductor substrate 10.

  In the semiconductor substrate 10, an insulating element isolation region 16 is formed in the vicinity of the surface 10 a, and an N-type region 13 A is formed immediately below the element isolation region 16. The width W1 of the N-type region 13A is, for example, 1 μm or more. The width W1 may be narrower than 1 μm. The N-type region 13A is formed so that the upper surface of the N-type region 13A is below the surface 10a. A distance D1 between the upper surface of the N-type region 13A and the surface 10a is, for example, 0.2 μm or more.

  Each of the P-type region lead pad 41 and the N-type region lead pad 42 includes a contact 21, a first wiring 22, a first via 23, a second wiring 24, a pad via 25, and a cover opening of the cover film 30. A pad metal 26 is provided as an exposed portion exposed from 31 to the outside. The contact 21, the first wiring 22, the first via 23, the second wiring 24, the pad via 25, and the pad metal 26 are formed in the wiring forming layer 20. The pad metal 26 of the P-type region lead pad 41 is formed of a P-type via the contact 21, the first wiring 22, the first via 23, the second wiring 24, and the pad via 25 through the opening of the element isolation region 16. Connected to region 12. A P + type region 17 is formed in the surface layer portion of the P type region 12 in contact with the contact 21 of the P type region lead pad 41. The pad metal 26 of the N-type region lead pad 42 is formed by the contact 21, the first wiring 22, the first via 23, the second wiring 24, and the pad via 25 through the opening of the element isolation region 16. 13A. An N + type region 18 is formed in the surface layer portion of the N type region 13A in contact with the contact 21 of the N type region extraction pad 42.

  The transistor 50A is an NMOS (N-Metal-Oxide-Silicon) transistor, and includes an N-type drain region 51A, an N-type source region 52A, and a gate electrode 53A. The drain region 51 </ b> A and the source region 52 </ b> A are formed in the P-type region 12 in the opening of the element isolation region 16. The gate electrode 53A is formed in the wiring formation layer 20.

  The transistor 50B is a PMOS (P-Metal-Oxide-Silicon) transistor, and includes a P-type drain region 51B, a P-type source region 52B, and a gate electrode 53B. The drain region 51 </ b> B and the source region 52 </ b> B are formed in the N-type region 14 formed in the opening of the element isolation region 16. An N-type region 15 is formed immediately below the N-type region 14. The gate electrode 53B is formed in the wiring formation layer 20.

  N-type regions 14 and 15 are separated from N-type region 13A by P-type region 12 and element isolation region 16.

  FIG. 4 is a sectional view of the general wiring lead pad 43. The general wiring lead pad 43 includes the second wiring 24, the pad via 25, and the pad metal 26 as an exposed portion exposed to the outside from the cover opening 31 of the cover film 30. The second wiring 24, the pad via 25, and the pad metal 26 are formed in the wiring forming layer 20. The pad metal 26 is connected to an internal circuit such as the transistor 50A or the transistor 50B by the second wiring 24 and the pad via 25.

  The P-type region lead pad 41, the N-type region lead pad 42, and the general wiring lead pad 43 are separated from each other by the interlayer insulating film 28.

  The number of wiring metal layers (a wiring layer including the first wiring 22 and a wiring layer including the second wiring 24) of the semiconductor device according to the present embodiment is not limited to two. The number of wiring metal layers may be one or more than ten. Further, both transistors 50A and 50B may be NMOS transistors or PMOS transistors.

  The diode characteristics of the PN junction are measured, and the presence or absence of cracks in the semiconductor substrate 10 is determined based on the result. FIG. 5 shows an inspection apparatus 100 used for measuring the diode characteristics. The inspection apparatus 100 is connected to the P-type region 12 through the pad metal 26 of the P-type region extraction pad 41 and is connected to the N-type region 13A through the pad metal 26 of the N-type region extraction pad 42. The inspection apparatus 100 includes a variable voltage source 101 that applies a variable voltage to the PN junction, an ammeter 102 that measures the current flowing through the PN junction, and a voltmeter 103 that measures the voltage applied to the PN junction. Prepare.

  With reference to the graph of FIG. 6, the difference in diode characteristics between the case where the PN junction is destroyed by a crack and the case where the PN junction is not destroyed will be described. In FIG. 6, the horizontal axis represents the voltage V applied to the PN junction, and the vertical axis represents the current I flowing through the PN junction. When the PN junction is not broken by a crack, the leakage current is small and the diode characteristic is shown by a curve 61. When the PN junction is broken by a crack, the leakage current is large, and therefore the diode characteristic is shown by a curve 62.

  When the N-type region 13A reaches the outer periphery 11, the leakage current increases even if there are no cracks, so that it becomes difficult to detect cracks based on the diode characteristics of the PN junction. Therefore, it is preferable that the outer end of the N-type region 13 </ b> A is located inside the outer peripheral end of the semiconductor substrate 10. A distance L1 between the outer end of the N-type region 13A and the outer peripheral end of the semiconductor substrate 10 is, for example, 0.2 μm or more.

  Next, with reference to FIG. 7, a method for manufacturing the semiconductor device according to the present embodiment will be described. The method for manufacturing a semiconductor device includes a wafer processing step S1, a dicing step S2, and a crack inspection step S3. In the wafer processing step S1, a P-type semiconductor wafer including a plurality of chip regions is processed. In the dicing step S2, the plurality of chip regions are separated into individual chip regions. The outer periphery 11 is formed at the cut end in dicing. Each chip region corresponds to the semiconductor device shown in FIGS. 2 to 4, and the outer periphery of the chip region corresponds to the outer periphery 11. In the crack inspection step S3, the presence or absence of cracks is inspected for each semiconductor device, that is, the chip region.

  In the wafer processing step S1, the transistor 50A, the transistor 50B, the N-type region 13A, and the element isolation region 16 are formed in the chip region, and then the wiring forming layer 20 and the cover film 30 are formed on the chip region. The N-type region 13A has a strip shape extending along the outer periphery (outer periphery 11) of the chip region so that a PN junction is formed between the N-type region 13A and the outside of the N-type region 13A. It is formed so that the end is located inside the outer peripheral end of the chip area after dicing. As a result, a part of the P-type region 12 is sandwiched between the outer periphery 11 and the outer end of the N-type region 13A, and the N-type region 13A does not reach the outer periphery 11. The N-type region 13A can be formed only by changing the mask used in the photolithography process for forming the N-type regions 14 and 15, and an additional step for forming the N-type region 13A is necessary. And not.

  The crack inspection step S3 includes a step of measuring the diode characteristics of the PN junction as described above and a step of determining the presence or absence of cracks based on the diode characteristics.

  When the back surface 10b is exposed to the outside, the inspection apparatus 100 may be connected to the back surface 10b instead of being connected to the pad metal 26 of the P-type region extraction pad 41 in the crack inspection step S3. When the N-type region 13A is formed so as to reach the exposed back surface 10b, a part of the back surface 10b of the N-type region 13A is formed instead of connecting the inspection apparatus 100 to the pad metal 26 of the N-type region extraction pad 42. It may be connected to the surface.

  Next, a modification of the semiconductor device according to the present embodiment will be described with reference to FIG. An N-type region 13B arranged inside the N-type region 13A is added to the semiconductor device described above. The N-type region 13B is formed in the semiconductor substrate 10 so that a PN junction is formed between the N-type region 13B and the P-type region 12. The N-type region 13B can be arranged at a place where an internal circuit such as the transistors 50A and 50B is not formed or a place where the operation of the internal circuit is not affected. For example, the N-type region 13B is formed immediately below a portion of the element isolation region 16 sandwiched between the transistors 50A and 50B. The N-type region 13B is separated from the N-type regions 14 and 15 by the element isolation region 16 and the P-type region 12.

  The N-type region 13B is formed so that the upper surface of the N-type region 13B is below the surface 10a. The distance between the upper surface of the N-type region 13B and the surface 10a is, for example, 0.2 μm or more. The N-type region 13B preferably has a strip shape, and the width W2 of the N-type region 13B in this case is preferably 1 μm or more. The width W2 may be narrower than 1 μm.

  The N-type region 13B is connected to the pad metal 26 of the N-type region extraction pad 42 through a diffusion layer or wiring of the same conductivity type as the N-type region 13A. In the present modification, cracks inside the semiconductor substrate 10 can also be detected by measuring the diode characteristics related to the N-type region 13B as described above. The N-type region 13B can be formed simultaneously with the N-type region 13A.

(Second Embodiment)
A semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. The semiconductor device according to the present embodiment is obtained by adding one or both of the N-type regions 13C and 13D to the semiconductor device according to the first embodiment. The N-type regions 13C and 13D are formed in a deep layer of the semiconductor substrate 10 so as not to affect internal circuits such as the transistors 50A and 50B. A space is provided between the upper surface of each of the N-type regions 13C and 13D and the lower surface of the element isolation region 16. A PN junction is formed between the N-type region 13C and the P-type region 12, and a PN junction is formed between the N-type region 13D and the P-type region 12. N-type region 13C and N-type region 13D are separated from N-type regions 14 and 15 by P-type region 12, respectively.

  The N-type region 13 </ b> C has a strip shape extending along the outer periphery 11 below the N-type region 13 </ b> A, and the outer end of the N-type region 13 </ b> C is located inside the outer peripheral end of the semiconductor substrate 10. The width W3 of the N-type region 13C is, for example, 1 μm or more. The width W3 may be narrower than 1 μm. The distance D3 between the upper surface of the N-type region 13C and the surface 10a is greater than 0.2 μm, for example. A distance L3 between the outer end of the N-type region 13C and the outer peripheral end of the semiconductor substrate 10 is, for example, 0.2 μm or more. A part of the P-type region 12 overhangs on the N-type region 13C, and the overhanging part of the P-type region 12 is sandwiched between the N-type region 13C and the element isolation region 16. The N-type region 13C is connected to the pad metal 26 of the N-type region lead pad 42 via an N-type region 13A as a diffusion layer of the same conductivity type as the N-type region 13C and a wiring. The N-type region 13 </ b> C is preferably formed over 3/4 of the outer periphery 11, but may be formed over less than 3/4 of the outer periphery 11, for example, over 1/2 of the outer periphery 11.

  N-type region 13D is formed below the portion of element isolation region 16 sandwiched between transistors 50A and 50B. The N-type region 13D is formed so that the upper surface of the N-type region 13D is below the surface 10a. The distance between the upper surface of the N-type region 13D and the surface 10a is, for example, 0.2 μm or more. The N-type region 13D preferably has a strip shape, and the width W4 of the N-type region 13D in this case is preferably 1 μm or more. The width W4 may be narrower than 1 μm. A part of the P-type region 12 overhangs on the N-type region 13D, and the overhanging portion of the P-type region 12 is sandwiched between the N-type region 13d and the portion where the element isolation region 16 is sandwiched. The N-type region 13D is connected to the pad metal 26 of the N-type region extraction pad 42 via N-type regions 13A and 13C as diffusion layers of the same conductivity type as the N-type region 13D, or wiring. The N-type region 13B described above may be provided on the N-type region 13D. Cracks inside the semiconductor substrate 10 can also be detected by the N-type region 13D.

  The semiconductor device manufacturing method according to the present embodiment is obtained by changing the wafer processing step S1 in the semiconductor device manufacturing method according to the first embodiment. For example, a step of forming the N-type regions 13C and 13D in the deep layer of the semiconductor wafer by a high energy ion beam implantation method is added. Alternatively, the N-type regions 13C and 13D are formed near the surface of the semiconductor wafer, and a P-type semiconductor layer is epitaxially grown thereon, and the element isolation region 16 and the N-type region 13A are formed in the grown P-type semiconductor layer. N-type semiconductor regions formed in deep layers such as the N-type region 13C and the N-type region 13D are patterned by photolithography.

  The N-type regions 13C and 13D formed in the deep layer are not limited in arrangement as compared to the N-type region 13A and the N-type region 13B because they do not easily affect internal circuits such as the transistors 50A and 50B. Therefore, according to the present embodiment, by measuring the diode characteristics related to the N-type regions 13C and 13D as described above, cracks can be detected with high probability, and the reliability of the semiconductor device is improved. .

  Also in the present embodiment, the connection to the inspection apparatus 100 may be made on the back surface 10b instead of the pad metal 26. Further, in the present embodiment, there may be no portions other than those necessary for drawing out the N-type regions 13C and 13D to the pad metal 26 in the N-type region 13A.

  The N-type semiconductor region formed in the deep layer may be formed on the entire surface of the semiconductor wafer. Since there is a low possibility that a crack will reach a part away from the outer peripheral part of the chip region, it is not necessary to form a deep N-type semiconductor region in that part. If the deep N-type semiconductor region is formed except for the portion away from the outer peripheral portion of the chip region, the back surface 10b can be connected as in the case where the deep N-type semiconductor region is not formed.

  The above technique can also be applied to a semiconductor device using an SOI (Silicon On Insulator) substrate. The SOI substrate includes an insulating film, silicon immediately above the insulating film, and silicon above the insulating film. Both silicons are semiconductors having opposite conductivity types. The presence or absence of cracks is detected based on the diode characteristics of a PN junction formed between the two silicons.

  The structure in which any of the N-type regions 13 </ b> A to 13 </ b> D is provided under the element isolation region 16 is suitable for detecting a crack that progresses from the bottom to the top of the semiconductor substrate 10.

  In each of the above embodiments, the conductivity type of the semiconductor substrate 10 may be an N type. In that case, the P-type and the N-type described above have opposite conductivity types.

  In each of the above embodiments, the wiring barrier layer 20 may be provided with the above-described double barrier 201 (see FIG. 1).

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 10a ... Front surface 10b ... Back surface 11 ... Outer periphery 12 ... P-type area | region 13A-13D, 14, 15 ... N-type area | region 16 ... Element isolation | separation area | region 17 ... P + type area | region 18 ... N + type area | region 20 ... Wiring formation layer 21 ... Contact 22 ... First wiring 23 ... First via 24 ... Second wiring 25 ... Pad via 26 ... Pad metal 28 ... Interlayer insulating film 30 ... Cover film 31 ... Cover opening 41 ... P-type region extraction pad 42 ... N-type region Drawer pad 43 ... General wiring lead pads 50A, 50B ... Transistors 51A, 51B ... Drain regions 52A, 52B ... Source regions 53A, 53B ... Gate electrodes 61 ... Curve 62 ... Curve 100 ... Inspection device 101 ... Variable voltage source 102 ... Ammeter 103 ... Voltmeter 201 ... Double barrier 202 ... Monitor device

Claims (12)

A first conductivity type semiconductor substrate;
A first exposed portion and a second exposed portion exposed to the outside;
The semiconductor substrate includes a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type,
A PN junction is formed between the first semiconductor region and the second semiconductor region;
The first semiconductor region and the second semiconductor region may be the first exposed portion and the second exposed portion, respectively, so that the diode characteristics of the PN junction can be measured through the first exposed portion and the second exposed portion. Connected to the
The second semiconductor region is formed in a strip shape extending along the outer periphery of the semiconductor substrate,
A semiconductor device, wherein an outer end of the second semiconductor region is located inside an outer peripheral end of the semiconductor substrate. The semiconductor device according to claim 1, wherein the second semiconductor region is formed over 3/4 or more of the outer periphery. An element isolation region is formed near the surface of the semiconductor substrate,
The semiconductor device according to claim 2, wherein the second semiconductor region is formed immediately below the element isolation region. The semiconductor substrate includes a third semiconductor region of the second conductivity type,
A PN junction is formed between the first semiconductor region and the third semiconductor region,
The third semiconductor region is connected to the second exposed portion;
The third semiconductor region is disposed inside the second semiconductor region;
The semiconductor device according to claim 2, wherein the first semiconductor region includes a portion sandwiched between the second semiconductor region and the third semiconductor region. The semiconductor substrate includes a deep region of the second conductivity type,
A PN junction is formed between the first semiconductor region and the deep region,
The deep region is connected to the second exposed portion;
The semiconductor device according to claim 2, wherein the first semiconductor region includes a portion overhanging the deep region. The deep region is formed in a strip shape extending along the outer periphery under the second semiconductor region,
The semiconductor device according to claim 5, wherein an outer end of the deep region is located inside an outer peripheral end. The semiconductor device according to claim 1, wherein each of the first exposed portion and the second exposed portion is a bonding pad. The semiconductor device according to claim 1, wherein one of the first exposed portion and the second exposed portion is a bonding pad, and the other is a back surface of the semiconductor substrate. Processing a first conductivity type semiconductor wafer including a plurality of chip regions;
Separating the plurality of chip regions into individual chip regions by dicing; and
Inspecting the chip area for cracks,
In the processing step, a second conductivity type second semiconductor region opposite to the first conductivity type is formed in the chip region so that a PN junction is formed between the first conductivity type and the first semiconductor region. Comprising the steps of:
The second semiconductor region has a strip shape extending along the outer periphery of the chip region, and the outer end of the second semiconductor region is positioned inside the outer peripheral end of the chip region after the dicing. Formed,
The step of inspecting comprises:
Electrically measuring the diode characteristics of the PN junction;
Determining the presence or absence of the crack based on the diode characteristics. The method of manufacturing a semiconductor device according to claim 9, wherein the second semiconductor region is formed over 3/4 or more of the outer periphery. The method of manufacturing a semiconductor device according to claim 10, wherein the step of processing includes a step of epitaxially growing the semiconductor layer of the first conductivity type on the second semiconductor region. The method of manufacturing a semiconductor device according to claim 10, wherein in the forming step, the second semiconductor region is formed by a high energy ion beam implantation method.

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