JP2011108345A - Semiconductor memory device, semiconductor device, and method of controlling semiconductor memory device - Google Patents

Abstract

An object of the present invention is to expand the range of power supply voltage that can be operated.
A memory cell matrix of an SRAM includes memory cells C0a and C0b connected to the same bit line pair BL0z and BL0x. Memory cell C0a includes one cell portion 31a and two transfer gates 32a and 33a. The two inverter circuits 34a and 35a of the cell unit 31a have their input terminals and output terminals connected to each other. Memory cell C0b includes one cell portion 31b and two transfer gates 32b and 33b. The two inverter circuits 34b and 35b of the cell unit 31b have their input terminals and output terminals connected to each other. The two ports P1a and P2a included in the memory cell C0a are connected to the two ports P1b and P2b included in the memory cell C0b via the switch circuits S0z and S0x, respectively.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor memory device, a semiconductor device, and a method for controlling the semiconductor memory device.

  One of the semiconductor memory devices is a static random access memory (SRAM). The SRAM is connected to the semiconductor device of the CPU as a single chip or is formed on a single chip together with a circuit such as a CPU to constitute a system LSI. The system LSI is called system-on-chip or system-on-silicon.

  The SRAM has a memory cell that stores one piece of data. The SRAM cell includes, for example, two transfer gates and two inverter circuits having a CMOS structure (see, for example, Patent Document 1). The two inverter circuits have their input terminals connected to each other's output terminals, and the input terminals (output terminals) of each inverter circuit are each connected to a pair of bit lines via a transfer gate. The SRAM holds complementary data by a flip-flop composed of two inverter circuits.

Japanese Patent Laid-Open No. 2007-4960 (FIG. 2)

  The electrical characteristics (for example, threshold voltage) of the transistors included in the SRAM cell are set according to the power supply voltage supplied to the SRAM cell. In addition, the power supply voltage of the semiconductor device is lowered to reduce power consumption. However, if the power supply voltage supplied to the SRAM cell is lowered, the static noise margin (SNM) indicating the stability of the SRAM cell is reduced, and the write data and the retained data of the cell are different. There is a risk of malfunction such as the difference between the data held in the memory and the data read via the bit line.

  An object of this semiconductor memory device is to expand the range of power supply voltage that can be operated.

  According to one aspect of the present invention, a cell unit including two inverter circuits for inputting mutual output signals and having an input / output port to which an output terminal of the inverter circuit is connected, and the input / output port and the bit line Connected between the first and second memory cells including a transfer gate connected therebetween, the input / output port of the first memory cell, and the input / output port of the second memory cell. And a first switch circuit.

  According to one aspect of the present invention, the range of power supply voltages that can be operated can be expanded.

1 is a block circuit diagram of a semiconductor memory device according to a first embodiment. FIG. 3 is a circuit diagram of a memory cell according to the first embodiment. It is a block circuit diagram of the semiconductor memory device of the second embodiment. It is a circuit diagram of a memory cell of a second embodiment. It is a circuit diagram of a memory cell of a third embodiment. It is a block circuit diagram of the semiconductor memory device of the fourth embodiment. It is a block circuit diagram of the semiconductor memory device of the fifth embodiment. FIG. 10 is a circuit diagram of a memory cell according to a fifth embodiment. It is an operation | movement waveform diagram of the memory cell of 5th embodiment. It is a block circuit diagram of the semiconductor memory device of 6th embodiment. It is a circuit diagram of the memory cell of 6th embodiment. It is an operation | movement waveform diagram of the memory cell of 6th embodiment. It is a schematic block diagram of the semiconductor device of 7th embodiment. It is a block circuit diagram of the semiconductor memory device of the seventh embodiment. It is a circuit diagram of a memory cell of a seventh embodiment. (A)-(d) is operation | movement explanatory drawing of a memory.

(First embodiment)
Hereinafter, the first embodiment will be described.
FIG. 1 is a schematic block diagram of a semiconductor memory device. The semiconductor memory device 10 is a static random access memory (SRAM). Hereinafter, the SRAM 10 will be described.

The SRAM 10 includes a memory cell matrix 11 and various circuits for accessing the memory cells of the memory cell matrix 11.
The memory cell matrix 11 includes a plurality of memory cells, and the memory cells are arranged in a matrix. The number of memory cells included in the memory cell matrix 11 is set according to the number of data (storage capacity) stored in the SRAM 10 and the number of bits of data. The memory cells in each column are connected to a word line WL, and the memory cells in each row are connected to a bit line pair. That is, the memory cell matrix 11 has the number of word lines WL and bit line pairs corresponding to the arrangement of the memory cells.

  The SRAM 10 selects a word line WL and a bit line pair corresponding to the address ADD, and a memory cell connected to the selected word line WL and bit line pair is an access target. Then, data corresponding to the input data ID is written into the target memory cell. Further, the data held in the target memory cell is read, and output data OD corresponding to the data is output.

  The address ADD is input to an address register (Address Register) 12. The address register 12 outputs the address ADD by dividing it into a row address RA and a column address CA according to the configuration of the memory cell matrix 11. The number of bits of the row address RA is set according to the number of word lines WL, and the number of bits of the column address CA is set according to the number of bit line pairs. The row address RA is input to a row decoder (Row Decoder) 13, and the column address CA is input to a column decoder (Column Decoder) 14.

  A clock buffer (Clock Buffer) 15 receives a clock signal CK, a chip enable signal CE, and a write enable signal WE. The clock signal CK is a pulse signal having a predetermined period. The write enable signal WE is activated when data is written to the SRAM 10. The chip enable signal CE is activated when the SRAM 10 is accessed. The clock buffer 15 outputs a signal obtained by buffering the signals CK, CE, and WE.

  A pulse generator 16 generates an activation pulse based on a signal input from the clock buffer 15. The activation pulse includes a data write pulse corresponding to data write and a data read pulse corresponding to data read. The pulse generator 16 outputs the generated activation pulse.

  The row decoder 13 outputs a word line selection signal generated by decoding the row address RA to a word line buffer 17 based on the row address RA and the activation pulse. The SRAM 10 has a word line buffer 17 connected to each of a plurality of word lines WL. Each word line buffer 17 activates one word line WL in response to a word line selection signal.

  The column decoder 14 outputs a column selection signal generated by decoding the column address CA based on the column address CA and the activation pulse. This column selection signal is input to a column selector 18.

  The column selector 18 has a plurality of column switches connected to a plurality of bit line pairs. In response to the column selection signal, the column selector 18 connects a number of bit line pairs equal to the number of data bits to the data bus. That is, the column selector 18 selects a bit line pair corresponding to the column address CA.

  A memory cell connected to the activated word line WL and the selected bit line pair is a target cell for data writing or data reading, that is, a memory cell directly designated by the address ADD.

  In the target cell, the input data ID is written through the input data register 19 and the write amplifier 20 at the time of data writing. The data read from the target cell is output as output data OD via a sense amplifier 21 and an output data register 22 at the time of data reading.

  Mask data DM is input to a data mask register 23. The data mask register 23 holds the mask data DM and outputs the held data. The input data register 19 performs a logical operation (for example, a logical product operation (AND)) on the mask data output from the data mask register 23 and the input data ID, and outputs a signal corresponding to the operation result.

A voltage recognition signal LP is input to the address register 12 and the cell short circuit control circuit (Cell Short) 24.
The voltage recognition signal LP is supplied with a level set according to the power supply voltage VDD supplied to the SRAM 10 from the outside. The SRAM 10 is supplied with a standard voltage (first power supply voltage) or a voltage lower than the standard voltage (second power supply voltage: low voltage). The standard voltage is, for example, a voltage set at the time of designing the memory cell, and is a voltage near the center of the voltage range (allowable voltage range) in which the operation of the memory cell is guaranteed (eg, 1.1 V).

  When the first power supply voltage is supplied to the SRAM 10, the L 10 voltage recognition signal LP is supplied to the SRAM 10. On the other hand, when the second power supply voltage is supplied to the SRAM 10, the H-level voltage recognition signal LP is supplied to the SRAM 10. The SRAM 10 operates in the normal operation mode in response to the L level voltage recognition signal LP, and operates in the low voltage mode in response to the H level voltage recognition signal LP.

The address register 12 outputs the row address RA so as to change the number of activated word lines WL based on the voltage recognition signal LP.
For example, the address register 12 outputs, as a row address RA, an address having the number of bits corresponding to the number of word lines WL and an inverted signal of the address among the input address ADD. Then, in response to the L level voltage recognition signal LP, the address register 12 complementarily outputs the address of each bit position of the row address RA and its inverted signal as the activation level based on the address ADD. The row decoder 13 activates one of the plurality of word line selection signals based on the row address RA, and the word line buffer 17 to which the activated word line selection signal is input is connected to the connected word. The line WL is activated.

  On the other hand, in response to the H level voltage recognition signal LP, the address register 12 simultaneously outputs the address at the predetermined bit position of the row address RA and its inverted signal as the activation level. The row decoder 13 activates a word line selection signal corresponding to the activated address and a word line selection signal corresponding to the activated inverted signal. Accordingly, the two word line selection signals are activated simultaneously, and the word line WL connected to the word line buffer 17 to which the respective word line selection signals are input is activated.

An operation example of the address register 12 will be described.
For example, the address ADD is composed of 8-bit signals A7 to A0. The address register 12 outputs upper 4 bits of signals A7 to A4 and inverted signals A7X to A4X. In the normal operation mode (LP is L level), the address register 12 sets the signal A7 and the inverted signal A7X to the activation level (for example, H level) in a complementary manner. Then, the column decoder 14 activates one word line WL in order to activate one word line selection signal.

  In the low voltage mode (the voltage recognition signal LP is at H level), the address register 12 simultaneously activates the signal A7 and the inverted signal A7X. Then, since the column decoder 14 activates the two word line selection signals, the two word lines WL are activated simultaneously.

  The cell short circuit control circuit 24 outputs a voltage recognition signal LPZ to the memory cell matrix 11 based on the voltage recognition signal LP. For example, the cell short circuit control circuit 24 outputs a voltage recognition signal LPZ having a level equal to the voltage recognition signal LP.

The configuration of the memory cell matrix 11 will be described.
FIG. 2 shows four memory cells C0a, C0b, C1a, and C1b among the memory cells included in the memory cell matrix 11.

  Memory cell C0a includes one cell portion 31a and two transfer gates 32a and 33a. The cell unit 31a includes two inverter circuits 34a and 35a, and the two inverter circuits 34a and 35a are connected to each other's input terminal and output terminal. Therefore, the cell unit 31a is a bistable circuit in which two inverter circuits 34a and 35a are connected in a loop.

  The inverter circuit 34a has a CMOS structure in which a P-channel MOS transistor T1a and an N-channel MOS transistor T2a are connected in series. A high potential voltage VDD is supplied to the source of the P channel MOS transistor T1a, the drain of the transistor T1a is connected to the drain of the N channel MOS transistor T2a, and a low potential voltage (for example, ground level) is applied to the source of the transistor T2a. Have been supplied.

  A connection point connecting the drain of the transistor T1a and the drain of the transistor T2a is an output terminal of the inverter circuit 34a. The gates of both transistors T1a and T2a are connected to each other, and the connection point serves as the input terminal of the inverter circuit 34a.

  Similarly, the inverter circuit 35a has a CMOS structure in which a P-channel MOS transistor T3a and an N-channel MOS transistor T4a are connected in series. A high potential voltage VDD is supplied to the source of the P channel MOS transistor T3a, a drain of the transistor T3a is connected to a drain of the N channel MOS transistor T4a, and a low potential voltage (ground level) is supplied to the source of the transistor T4a. Has been.

  A connection point connecting the drain of the transistor T3a and the drain of the transistor T4a becomes an output terminal of the inverter circuit 35a. The gates of the transistors T3a and T4a are connected to each other, and the connection point serves as the input terminal of the inverter circuit 35a.

  A connection point (internal node) connecting the output terminal of the inverter circuit 34a and the input terminal of the inverter circuit 35a is one input / output port P1a of the cell unit 31a. The output terminal of the inverter circuit 35a and the input terminal of the inverter circuit 34a The connection point (internal node) connecting the two is the other input / output port P2a of the cell unit 31a. Both ports P1a and P2a are connected to bit lines BL0z and BL0x via transfer gates 32a and 33a, respectively.

  The transfer gates 32a and 33a are N-channel MOS transistors, and the gates are connected to the word line WL1. The transfer gates 32a and 33a are turned on when the word line WL1 is activated and turned off when the word line WL1 is inactive. That is, when the word line WL1 is activated, the input / output ports P1a and P2a of the memory cell C0a are connected to the bit line pair BL0z and BL0x, respectively.

  The memory cell C0b is configured similarly to the memory cell C0a. That is, the memory cell C0b includes one cell portion 31b and two transfer gates 32b and 33b. The cell unit 31b is a bistable circuit that includes two inverter circuits 34b and 35b and connects the input terminal and the output terminal of each other, that is, connects the two inverter circuits 34b and 35b in a loop.

  The inverter circuit 34b has a CMOS structure in which a P channel MOS transistor T1b and an N channel MOS transistor T2b are connected in series. A high potential voltage VDD is supplied to the source of the P-channel MOS transistor T1b, a drain of the transistor T1b is connected to a drain of the N-channel MOS transistor T2b, and a low potential voltage (ground level) is supplied to the source of the transistor T2b. Has been.

  A connection point connecting the drain of the transistor T1b and the drain of the transistor T2b is an output terminal of the inverter circuit 34b. The gates of both transistors T1b and T2b are connected to each other, and the connection point serves as the input terminal of the inverter circuit 34b.

  Similarly, the inverter circuit 35b has a CMOS structure in which a P-channel MOS transistor T3b and an N-channel MOS transistor T4b are connected in series. A high potential voltage VDD is supplied to the source of the P-channel MOS transistor T3b, a drain of the transistor T3b is connected to a drain of the N-channel MOS transistor T4b, and a low potential voltage (ground level) is supplied to the source of the transistor T4b. Has been.

  A connection point connecting the drain of the transistor T3b and the drain of the transistor T4b is an output terminal of the inverter circuit 35b. The gates of both transistors T3b and T4b are connected to each other, and the connection point serves as the input terminal of the inverter circuit 35b.

  A connection point (internal node) connecting the output terminal of the inverter circuit 34b and the input terminal of the inverter circuit 35b is one input / output port P1b of the cell unit 31b. The output terminal of the inverter circuit 35b and the input terminal of the inverter circuit 34b The connection point (internal node) connecting the two is the other input / output port P2b of the cell unit 31b. Both ports P1b and P2b are connected to bit lines BL0z and BL0x via transfer gates 32b and 33b, respectively.

  The transfer gates 32b and 33b are N-channel MOS transistors, and the gates are connected to the word line WL2. The transfer gates 32b and 33b are turned on when the word line WL2 is activated and turned off when the word line WL2 is inactive. That is, when the word line WL2 is activated, the input / output ports P1b and P2b of the memory cell C0b are connected to the bit line pair BL0z and BL0x, respectively.

  The two ports P1a and P2a included in the memory cell C0a are connected to the two ports P1b and P2b included in the memory cell C0b via the switch circuits S0z and S0x, respectively.

  The switch circuits S0z and S0x are N channel MOS transistors, for example, and a voltage recognition signal LPZ is supplied to the gates of the transistors. Therefore, the switch circuits S0z and S0x are turned on in response to the H level voltage recognition signal LPZ and turned off in response to the L level voltage recognition signal LPZ.

  Both terminals of the switch circuit S0z are connected to the port P1a of the memory cell C0a and the port P1b of the memory cell C0b. Both terminals of the switch circuit S0x are connected to the port P2a of the memory cell C0a and the port P2b of the memory cell C0b.

  The port P1a is connected to the bit line BL0z via the transfer gate 32a, and the port P1b is connected to the bit line BL0z via the transfer gate 32b. Therefore, the switch circuit S0z connects and disconnects the port P1a and the port P1b connected to the same bit line BL0z among the ports included in the two memory cells C0a and C0b.

  Similarly, the port P2a is connected to the bit line BL0x via the transfer gate 33a, and the port P2b is connected to the bit line BL0x via the transfer gate 33b. Accordingly, among the ports included in the two memory cells C0a and C0b, the switch circuit S0x connects and disconnects the port P2a and the port P2b connected to the same bit line BL0x.

  In the normal operation mode, the voltage recognition signals LP and LPZ are at the L level, and both the switch circuits S0z and S0x are turned off. At this time, the ports P1a and P2a of the memory cell C0a are separated from the ports P1b and P2b of the memory cell C0b. Therefore, the ports P1a and P2a of the memory cell C0a are connected to and separated from the bit line pair BL0z and BL0x by the transfer gates 32a and 33a that are turned on / off in response to the activation / deactivation of the word line WL1. Similarly, the ports P1b and P2b of the memory cell C0b are connected to and separated from the bit line pair BL0z and BL0x by transfer gates 32b and 33b that are turned on / off in response to activation / deactivation of the word line WL2.

  The switch circuits S0z and S0x are turned off in response to the L level voltage recognition signal LPZ, that is, the voltage recognition signal LP shown in FIG. 1, and the address register 12 in FIG. 1 responds to the L level voltage recognition signal LP. The row address RA corresponding to the address ADD is output. Therefore, the word line buffer 17 in FIG. 2 activates the word line WL1 and the word line WL2 individually. Accordingly, the two memory cells C0a and C0b function as individual memory cells each holding one data.

  In the low voltage mode, the voltage recognition signals LP and LPZ are at the H level, and both the switch circuits S0z and S0x are turned on. At this time, the ports P1a and P2a of the memory cell C0a are connected to the ports P1b and P2b of the memory cell C0b. Therefore, the ports P1a and P1b of both the memory cells C0a and C0b are turned on / off in response to activation / inactivation of the word line WL2 and a transfer gate 32a that is turned on / off in response to activation / inactivation of the word line WL1. The bit line BL0z is connected to or separated from at least one of the transfer gates 32b. Similarly, the ports P2a and P2b of both memory cells C0a and C0b are turned on / off in response to activation / inactivation of the word line WL1 and transfer gate 33a which is turned on / off in response to activation / inactivation of the word line WL1. The bit line BL0x is brought into and out of contact with at least one of the transfer gates 33b.

  The voltage recognition signal LPZ, that is, the voltage recognition signal LP shown in FIG. 1 is at the H level, and the address register 12 in FIG. 1 activates two word lines simultaneously in response to the H level voltage recognition signal LP. Thus, the row address RA is output. With this row address RA, the word line buffer 17 in FIG. 2 activates two word lines WL1 and WL2 simultaneously. The activated word lines WL1 and WL2 connect the ports of both memory cells C0a and C0b to the corresponding bit lines BL0z and BL0x. Accordingly, the two memory cells C0a and C0b are simultaneously read or written and function as one memory cell that holds one data.

  This one memory cell is called a composite cell. Each memory cell is composed of 6 transistors, and the composite cell is composed of 12 transistors. Therefore, the number of composite cells included in the memory cell matrix 11 is half of the number of individual memory cells.

  When the switch circuit S0z is turned on, the transistor T1a of the memory cell C0a and the transistor T1b of the memory cell C0b are connected in parallel to each other between the wiring that supplies the high potential voltage VDD and the ports P1a and P1b. It becomes a state. Further, the gate of the transistor T1a is connected to the gate of the transistor T1b via the switch circuit S0x. Therefore, both transistors T1a and T1b are turned on and off simultaneously.

When both the transistor T1a and the transistor T1b are turned on,
Similarly, the transistors T2a and T2b are connected in parallel between the ports P1a and P1b and a wiring for supplying a low potential voltage. The switch circuit S0x also causes the transistors T3a and T3b, and the transistors T4a and T4b to be connected in parallel. The transistors corresponding to the two memory cells C0a and C0b, that is, the transistors T2a and T2b, the transistors T3a and T3b, and the transistors T4a and T4b are turned on and off at the same time.

  The memory cell C1a is configured similarly to the memory cell C0a, and the memory cell C1b is configured similar to the memory cell C0b. For this reason, the elements included in the memory cells C1a and C1b are assigned the same reference numerals as the elements included in the memory cells C0a and C0b.

  The memory cells C1a and C1b are connected to the bit line pair BL1z, BL1x. The ports P1a and P2a of the memory cell C1a are connected to the ports P1b and P2b of the memory cell C1b via the switch circuits S1z and S1x, respectively.

  The SRAM 10 configured as described above can increase the stability and expand the operating range by connecting two memory cells and operating as a memory cell storing one data. This is due to the following reason.

  As an index indicating the stability of the SRAM, a static noise margin (SNM) is used. The SNM is represented by the size of a figure (for example, the length of one side of a square) that is inscribed in the two characteristic waveforms by superimposing characteristic waveforms indicating voltage changes at the two input / output ports of the memory cell. The intersection of the two characteristic waveforms becomes the operating point (operating point).

  The operating point is that the threshold voltage of the transistors constituting the inverter circuit included in the memory cell, the current flowing through the load transistor (eg, P channel MOS transistor) constituting the inverter circuit, and the driver transistor (eg, N channel MOS transistor). It is determined by the ratio of the flowing current. This current ratio corresponds to the beta ratio of the inverter circuit (ratio of the β value of the driver transistor to the β value of the load transistor).

  One of the operation ranges of the SRAM is a power supply voltage range in which data can be stably held in memory cells. This voltage range corresponds to variations in characteristics of transistors included in the memory cell. The characteristic variation causes the above-described variation in current ratio. Therefore, the operation range (power supply voltage range) of the SRAM is determined by the stability of the memory cell including the inverter circuit having a small current ratio.

  As shown in FIG. 2, the two memory cells C0a and C0b connected to each other by the switch circuits S0z and S0x are different from the transistors T1a to T4a included in the memory cell C0a with respect to the transistors T1b to T4b included in the memory cell C0b. Are connected in parallel. Then, for example, the amount of current flowing from the wiring supplying the high potential voltage VDD to the ports P1a and P1b is the sum of the amount of current flowing through the transistor T1a and the amount of current flowing through the transistor T1b. The amount of current flowing through the wiring that supplies the low potential voltage from the ports P1a and P1b is the sum of the amount of current flowing through the transistor T2a and the amount of current flowing through the transistor T2b.

  Then, the current ratio is a ratio between the amount of current flowing through the transistors T1a and T2a and the amount of current flowing through the transistors T1b and T2b. This current ratio is an average value of the current ratios of the individual inverter circuits. Therefore, the variation in the current ratio in the memory cell matrix when two memory cells are connected to each other is smaller than the variation in the current ratio in the memory cell matrix when each memory cell is operated independently.

  That is, connecting the two memory cells C0a and C0b to each other by the switch circuits S0z and S0x is equivalent to reducing variations in elements included in the memory cells C0a and C0b. As a result, the current ratio that determines the power supply voltage range is increased. For this reason, the stability of the memory cell is higher than when operating individual memory cells. That is, the operating range of the memory cell is widened.

  As described above, the operation range can be widened by connecting two memory cells to operate as one memory cell. Therefore, it is possible to obtain the SRAM 10 that operates at a low voltage mode, that is, stably operates in the low voltage mode.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The memory cell matrix 11 of the SRAM 10 includes memory cells C0a and C0b connected to the same bit line pair BL0z and BL0x. Memory cell C0a includes one cell portion 31a and two transfer gates 32a and 33a. The two inverter circuits 34a and 35a of the cell unit 31a have their input terminals and output terminals connected to each other. Memory cell C0b includes one cell portion 31b and two transfer gates 32b and 33b. The two inverter circuits 34b and 35b of the cell unit 31b have their input terminals and output terminals connected to each other. The two ports P1a and P2a included in the memory cell C0a are connected to the two ports P1b and P2b included in the memory cell C0b via the switch circuits S0z and S0x, respectively.

  Therefore, when the switch circuits S0z and S0x are turned off, the memory cells C0a and C0b perform data reading or writing independently of each other. On the other hand, when the switch circuits S0z and S0x are turned on, the memory cells C0a and C0b operate as memory cells that store one piece of data. When the two memory cells C0a and C0b are connected to each other, the influence of variations in the elements included in the memory cells C0a and C0b is reduced, and the power supply voltage range is determined as compared with the case of operating individual memory cells. The current ratio increases. As a result, the stability of the memory cell can be made higher than when individual memory cells are operated, that is, the operating range of the memory cell can be widened.

  (2) By connecting the ports P1a and P2a of the memory cell C0a and the ports P1b and P2b of the memory cell C0b, the operation range of the memory cell is widened. Therefore, even if the high potential voltage VDD supplied to the memory cells C0a and C0b is lowered as the operating voltage, data can be held and malfunction can be prevented. Therefore, the voltage of the SRAM 10 can be reduced.

(Second embodiment)
The second embodiment will be described below.
In addition, the same code | symbol is attached | subjected about the same component as the said embodiment.

As shown in FIG. 3, the SRAM 40 of the present embodiment includes a cell voltage control circuit (VDD2 Gen) 41.
The cell voltage control circuit 41 supplies the memory cell matrix 11 with a high potential voltage VDD (first high potential voltage) or a second high potential voltage lower than the high potential voltage VDD based on the voltage recognition signal LP. For example, the cell voltage control circuit 41 supplies the high potential voltage VDD to the memory cell matrix 11 in response to the L level voltage recognition signal LP, and the second high potential voltage in response to the H level voltage recognition signal LP. Is supplied to the memory cell matrix 11.

  As shown in FIG. 4, the high potential voltage VDD is supplied to the memory cells C0a and C1a connected to the word line WL1 through the wiring L1. Memory cell C0a includes one cell portion 31a and two transfer gates 32a and 33a. The cell unit 31a includes two inverter circuits 34a and 35a. The P channel MOS transistor T1a of the inverter circuit 34a and the P channel MOS transistor T3a of the inverter circuit 35a are connected to the wiring L1. Accordingly, the high potential voltage VDD is supplied as the operating voltage to the inverter circuits 34a and 35a of the memory cell C0a. Since the memory cell C1a is the same as the memory cell C0a, description thereof is omitted.

The memory cell C0b paired with the memory cell C0a is connected to the cell voltage control circuit 41 via the wiring L2.
Cell voltage control circuit 41 includes a P-channel MOS transistor T11 and an N-channel MOS transistor T12. The high potential voltage VDD is supplied to the source of the PMOS transistor T11, the drain is connected to the wiring L2, and the voltage recognition signal LP is supplied to the gate. The PMOS transistor T11 is turned on / off in response to the voltage recognition signal LP, and the high potential voltage VDD is supplied to the memory cell C0b via the turned-on PMOS transistor T11 and the wiring L2.

  The source of the NMOS transistor T12 is connected to the wiring L2, the high potential voltage VDD is supplied to the drain, and the voltage recognition signal LP is supplied to the gate. The NMOS transistor T12 is turned on / off in response to the voltage recognition signal LP. That is, the PMOS transistor T11 and the NMOS transistor T12 are complementarily turned on and off in response to the voltage recognition signal LP.

  The H level voltage recognition signal LP is at the high potential voltage VDD level. For this reason, when the NMOS transistor T12 is turned on, the source potential of the NMOS transistor T12 becomes as low as the threshold voltage of the NMOS transistor T12. Therefore, the cell voltage control circuit 41 generates a voltage lower than the high potential voltage VDD by the threshold value of the NMOS transistor T12 as the second high potential voltage. Then, the second high potential voltage is supplied to the memory cell C0b via the wiring L2.

  The memory cell C0b is connected to and separated from the paired memory cell C0a via the switch circuits S0z and S0x based on the voltage recognition signal LPZ. Similarly, the memory cell C1b is connected to and separated from the paired memory cell C1a via the switch circuits S1z and S1x based on the voltage recognition signal LPZ. Since both the memory cells C0b and C1b have the same configuration and operate in the same manner, the memory cell C0b and the memory cell C1a to which the memory cell C0b is connected and separated will be described below.

  When the switch circuits S0z and S0x are turned off by the voltage recognition signals LP and LPZ, the memory cell C0b is disconnected from the memory cell C0a. Then, the high potential voltage VDD is supplied from the cell voltage control circuit 41 to the memory cell C0b. Accordingly, each of the memory cells C0a and C0b functions as a memory cell that stores one piece of data.

  On the other hand, when the switch circuits S0z and S0x are turned on by the voltage recognition signals LP and LPZ, the memory cell C0b is connected to the memory cell C0a. Therefore, the memory cells C0a and C0b function as one memory cell that holds one data in cooperation.

  At this time, the second high potential voltage is supplied from the cell voltage control circuit 41 to the memory cell C0b. Since the ports P1b and P2b of the memory cell C0b are connected to the ports P1a and P2a of the memory cell C0a via the switch circuits S0z and S0x that are turned on, they are at the same level.

  Therefore, the amount of current flowing through P channel MOS transistors T1b and T3b of memory cell C0b is smaller than the amount of current flowing through P channel MOS transistors T1a and T3a of memory cell C0a. On the other hand, the amount of current flowing through N channel MOS transistors T2b and T4b of memory cell C0b is the same as the amount of current flowing through N channel MOS transistors T2a and T4a of memory cell C0a. As a result, the ratio of the amount of current flowing through the N-channel MOS transistors T2a, T4a, T2b, and T4b to the amount of current flowing through the P-channel MOS transistors T1a, T3a, T1b, and T3b is different for each of the memory cells C0a and C0b. It becomes larger than the case where it operates. For this reason, the stability of the memory cell is higher than when operating individual memory cells. That is, the operating range of the memory cell is widened.

  Then, by making the operating voltage of the memory cell C0b lower than the high potential voltage VDD, the operating characteristics of the inverter circuits 34b and 35b shift to the low potential side. As a result, the operation range of the two memory cells C0a and C0b becomes wider toward the low potential side. Therefore, even if the high potential voltage VDD is lowered, the SNM becomes a predetermined value or more, that is, the stability is ensured.

As described above, according to the present embodiment, the following effects can be obtained.
(1) A pair of memory cells C0b is connected to the memory cell C0a via the switch circuits S0z and S0x, and a second high voltage lower than the high potential voltage VDD from the cell voltage control circuit 41 is connected to the memory cell C0b. A potential voltage was supplied. Thereby, the ratio of the amount of current flowing through the driver transistors T2a, T4a, T2b, and T4b to the amount of current flowing through the load transistors T1a, T3a, T1b, and T3b causes each of the memory cells C0a and C0b to operate separately. Larger than For this reason, the stability of the memory cell can be made higher than when individual memory cells are operated, that is, the operating range of the memory cell can be widened.

  (2) By making the operating voltage of the memory cell C0b lower than the high potential voltage VDD, the operating characteristics of the inverter circuits 34b and 35b shift to the low potential side. As a result, the operation range of the two memory cells C0a and C0b can be widened toward the low potential side. Therefore, even if the high potential voltage VDD is lowered, the SNM becomes a predetermined value or more, that is, the stability can be ensured.

  (3) The cell voltage control circuit 41 includes a P-channel MOS transistor T11 and an N-channel MOS transistor T12. In the normal operation mode, the cell T11 is turned on to supply the high potential voltage VDD to the memory cell C0b. Occasionally, the transistor T12 is turned on to supply a voltage lower than the high potential voltage VDD by the threshold voltage of the transistor T12 to the memory cell C0b. As a result, the high potential voltage supplied to the memory cell C0b can be easily controlled.

(Third embodiment)
Hereinafter, a third embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same component as the said embodiment.

  As shown in FIG. 5, the memory cells C0b and C1b connected to the word line WL2 are connected to the cell voltage control circuit 51. The cell voltage control circuit 51 includes transistors T21 and T22 corresponding to the memory cells C0b and C1b. FIG. 5 shows a configuration corresponding to the memory cells C0b and C1b.

  The transistor T21 is, for example, a P channel MOS transistor. The transistor T21 has a source supplied with a high potential voltage VDD, and a drain connected to the power supply terminals of the inverter circuits 34b and 35b of the memory cell C0b, that is, the sources of the P-channel MOS transistors T1b and T3b included in the inverter circuits 34b and 35b. Yes. The voltage recognition signal LPZ is supplied to the gate of the transistor T21.

  In the transistor T22, similarly to the transistor T21, the high potential voltage VDD is supplied to the source, the drain is connected to the power supply terminals of the inverter circuits 34b and 35b of the memory cell C1b, and the voltage recognition signal LPZ is supplied to the gate.

  The transistors T21 and T22 are turned on / off in response to the voltage recognition signal LPZ. When the transistors T21 and T22 are turned on, the high potential voltage VDD is supplied to the inverter circuits 34b and 35b of the memory cells C0b and C1b. On the other hand, when the transistors T21 and T22 are turned off, the supply of the high potential voltage VDD to the inverter circuits 34b and 35b of the memory cells C0b and C1b is stopped.

That is, the cell voltage control circuit 51 of this embodiment supplies the high potential voltage VDD or stops supplying the high potential voltage VDD in response to the voltage recognition signal LPZ.
The memory cell C0b is connected to and separated from the paired memory cell C0a via the switch circuits S0z and S0x based on the voltage recognition signal LPZ. Similarly, the memory cell C1b is connected to and separated from the paired memory cell C1a via the switch circuits S1z and S1x based on the voltage recognition signal LPZ. Since both the memory cells C0b and C1b have the same configuration and operate in the same manner, the memory cell C0b and the memory cell C1a to which the memory cell C0b is connected and separated will be described below.

  When the switch circuits S0z and S0x are turned off by the voltage recognition signals LP and LPZ, the memory cell C0b is disconnected from the memory cell C0a. Then, the high potential voltage VDD is supplied from the cell voltage control circuit 41 to the memory cell C0b. Accordingly, each of the memory cells C0a and C0b functions as a memory cell that stores one piece of data.

  On the other hand, when the switch circuits S0z and S0x are turned on by the voltage recognition signals LP and LPZ, the memory cell C0b is connected to the memory cell C0a. Therefore, the memory cells C0a and C0b function as one memory cell that holds one data in cooperation.

  At this time, the cell voltage control circuit 41 stops supplying the high potential voltage VDD to the memory cell C0b. Since the ports P1b and P2b of the memory cell C0b are connected to the ports P1a and P2a of the memory cell C0a via the switch circuits S0z and S0x that are turned on, they are at the same level.

  Therefore, the amount of current flowing through the P-channel MOS transistors T1b and T3b of the memory cell C0b is zero. On the other hand, the amount of current flowing through N channel MOS transistors T2b and T4b of memory cell C0b is the same as the amount of current flowing through N channel MOS transistors T2a and T4a of memory cell C0a. As a result, the ratio of the amount of current flowing through the N-channel MOS transistors T2a, T4a, T2b, and T4b to the amount of current flowing through the P-channel MOS transistors T1a, T3a, T1b, and T3b is different for each of the memory cells C0a and C0b. It becomes larger than the case where it operates. For this reason, the stability of the memory cell is higher than when operating individual memory cells. That is, the operating range of the memory cell is widened.

  Then, by stopping the supply of the high potential voltage VDD to the memory cell C0b, the operating characteristics of the inverter circuits 34b and 35b shift to the low potential side. As a result, the operation range of the two memory cells C0a and C0b becomes wider toward the low potential side. Therefore, even if the high potential voltage VDD is lowered, the SNM becomes a predetermined value or more, that is, the stability is ensured.

As described above, according to the present embodiment, the following effects can be obtained.
(1) A pair of memory cells C0b is connected to the memory cell C0a via the switch circuits S0z and S0x, and the cell voltage control circuit 51 stops supplying the high potential voltage VDD to the memory cell C0b. I did it. As a result, the ratio of the amount of current flowing through the driver transistors T2a, T4a, T2b, and T4b to the amount of current flowing through the load transistors T1a and T3a is larger than when the memory cells C0a and C0b are operated separately. Become. For this reason, the stability of the memory cell can be made higher than when individual memory cells are operated, that is, the operating range of the memory cell can be widened.

  (2) By stopping the supply of the high potential voltage VDD to the memory cell C0b, the operating characteristics of the inverter circuits 34b and 35b shift to the low potential side. As a result, the operation range of the two memory cells C0a and C0b can be widened toward the low potential side. Therefore, even if the high potential voltage VDD is lowered, the SNM becomes a predetermined value or more, that is, the stability can be ensured.

  (3) The cell voltage control circuit 51 includes a P-channel MOS transistor T21 connected to the inverter circuits 34b and 35b of the memory cell C0b. The transistor T21 is turned on in the normal operation mode, and the transistor T21 is turned on in the low voltage mode. I tried to turn it off. As a result, the high potential voltage VDD supplied to the memory cell C0b can be easily controlled.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same component as the said embodiment.

As shown in FIG. 6, the SRAM 60 includes an address register 61.
Address register 61 receives address ADD, write enable signal WE, and voltage recognition signal LP.

The write enable signal WE is activated when data is written to the SRAM 60.
Based on the voltage recognition signal LP, the address register 61 generates a row address RA so as to activate one word line WL based on the address ADD in the normal operation mode. Further, the address register 61, based on the voltage recognition signal LP, in the low voltage mode, according to the write enable signal WE, either one of the two word lines that are paired or two word lines WL. A row address RA is generated so as to activate.

  Specifically, in the low voltage mode, the address register 61 activates one of the two word lines that are paired when data is read based on the write enable signal WE, and A row address RA is generated so that the two word lines WL are simultaneously activated.

Since the memory cell matrix 11 is configured in the same manner as in the first embodiment, the operation of the address register 61 will be described with reference to FIG.
The memory cell matrix 11 has a memory cell C0a connected to the word line WL1 and a memory cell C0b connected to the word line WL2, and both the memory cells C0a and C0b are connected to and separated from each other via the switch circuits S0z and S0x. It is. That is, the memory cell C0a and the memory cell C0b are two memory cells that form a pair.

  The address register 61 outputs a row address RA to select the two word lines WL1 and WL2 based on the H level voltage recognition signal LP and the activated write enable signal WE. Based on this, the word line WL1 and the word line WL2 are activated. Based on the activated word lines WL1 and WL2, the transfer gates 32a and 33a of the memory cell C0a and the transfer gates 32b and 33b of the memory cell C0b are turned on. As a result, the ports P1a and P1b of both the memory cells C0a and C0b are connected to the bit line BL0z via the two transfer gates 32a and 32b that are turned on, and the ports P2a and P2b are the two transfer gates 33a and 33b that are turned on. To the bit line BL0x.

  On the other hand, the address register 61 outputs a row address RA to select one word line WL1 based on the H level voltage recognition signal LP and the inactive write enable signal WE, and based on the row address RA. Thus, the word line WL1 is activated. At this time, the word line WL2 is not activated, that is, inactive. Then, the transfer gates 32a and 33a of the memory cell C0a are turned on, and the transfer gates 32b and 33b of the memory cell C0b are turned off. As a result, the ports P1a and P1b of both the memory cells C0a and C0b are connected to the bit line BL0z through one turned-on transfer gate 32a, and the ports P2a and P2b are bit-connected through one turned-on transfer gate 33a. Connected to line BL0x.

  The memory cells C0a and C0b are connected to each other via the switch circuits S0z and S0x to form a composite cell. Therefore, in the address register 61, the number of transfer gates that connect the synthesized cell to the bit line pair BL0z, BL0x is changed between writing and non-writing. Therefore, the ratio of the current amount of the driver transistor (the transistor connected between the input / output port and the wiring supplied with the low potential voltage) to the current amount of the transfer gate is larger than that at the time of writing. . That is, the stability (SNM) of the memory cell at the time of non-reading (at the time of reading and non-accessing) becomes higher than the stability at the time of writing. Therefore, even when the operating voltage is lowered, data can be retained stably. In addition, since the stability at the time of reading is increased, it is possible to prevent a malfunction such as that the level of the input / output port is inverted and erroneous data is held during the reading operation. In other words, the stability at the time of writing is lower than the stability at the time of non-reading (during reading and non-accessing). Therefore, data can be easily held from the bit lines BL0z and BL0x.

  Note that the address register 61 of this embodiment may be applied to the SRAMs of the second and third embodiments. For example, in the case of the SRAM 40 according to the second embodiment, the operation range when the composite cell is configured is wider than that in the case of using individual memory cells, and is shifted in the low voltage direction. Therefore, when the address register 61 of the present embodiment is applied, the stability of the composite cell during non-write can be increased when the operating voltage is lowered.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The address register 61 generates a row address RA based on the voltage recognition signal LP so as to activate one word line WL based on the address ADD in the normal operation mode. In response to the write enable signal WE, the row address RA is generated so as to activate any one or two word lines WL of the pair of two word lines. Based on the row address RA, the word lines WL1 and WL2 are activated during the write operation. On the other hand, during the non-write operation, the word line WL1 is activated and the word line WL2 is deactivated. As a result, the stability (SNM) of the memory cell during non-reading (during reading and non-accessing) can be made higher than the stability during writing. Therefore, even when the operating voltage is lowered, data can be retained stably. In addition, since the stability at the time of reading is increased, it is possible to prevent a malfunction such as that the level of the input / output port is inverted and erroneous data is held during the reading operation.

  (2) Further, the stability at the time of writing is made lower than the stability at the time of non-reading (during reading and non-accessing), so that data can be easily written from the bit lines BL0z and BL0x.

(Fifth embodiment)
The fifth embodiment will be described below.
In addition, the same code | symbol is attached | subjected about the same component as the said embodiment.

As shown in FIG. 7, the SRAM 70 includes a memory cell matrix 71, an address register 72, and a cell short circuit control circuit 73.
The address register 72 receives an address ADD, a write enable signal WE, and a voltage recognition signal LP.

  The address register 72 operates in the normal operation mode in response to the L level signal LP based on the voltage recognition signal LP and in the low voltage mode in response to the H level signal LP, as in the above embodiment. Works. Further, the address register 72 uses a predetermined period from the rising timing of the voltage recognition signal LP as a data transfer period, and in this data transfer period, the word line WL to which one of the two memory cells that are paired is connected, The row address RA is output so as to be activated for a certain period. Here, of the two memory cells in a pair, a memory cell connected to a word line that is not activated during the data transfer period is called a main cell, and a memory cell connected to a word line that is activated during the data transfer period Is called a subcell.

  The cell short-circuit control circuit 73 generates signals LPZ, LPXP, LPZ2 based on the voltage recognition signal LP. These signals LPZ, LPXP, LPZ2 are supplied to the memory cell matrix 71. In FIG. 7, only LPZ is shown as a signal name.

  As shown in FIG. 9, when the voltage recognition signal LP is at the L level, the cell short circuit control circuit 73 outputs L level signals LPZ and LPZ2 and an H level signal LPXP. In response to the H level voltage recognition signal LP, the cell short circuit control circuit 73 outputs an L level signal LPXP and an H level signal LPZ2. When a predetermined time elapses after the H level signal LP is input, the H level signal LPZ is output. Further, when a predetermined time elapses, an H level signal LPXP is output.

  A period from when the H level voltage recognition signal LP is input to when the H level signal LPXP is output is a data transfer period. As in the above embodiment, the word lines WL1 and WL2 are word lines to which two memory cells that form a pair are connected. In this data transfer period, the address register 72 shown in FIG. 7 activates the word line WL2 for a certain period (H level). Then, the cell short-circuit control circuit 73 shown in FIG. 7 outputs an H level signal LPZ after the word line WL2 is deactivated. In the present embodiment, the address register 72 and the cell short-circuit control circuit 73 receive the row address RA and the signal LPZ after the time set by a time constant or the like has elapsed since the H level voltage recognition signal LP was input. Each is configured to change.

Next, the configuration of the memory cell matrix 71 will be described.
FIG. 8 shows four memory cells C0a, C0b2, C1a, and C1b2 included in the memory cell matrix 71 of FIG. Memory cells C0a and C1a are connected to word line WL1, and memory cells C0b2 and C1b2 are connected to word line WL2. That is, the memory cells C0a and C1a are main cells, and the memory cells C0b2 and C1b2 are subcells.

  Memory cell C0b2 includes a cell portion 31b, transfer gates 32b and 33b, and switch circuits S0H and S0L. The cell portion 31b is connected to a wiring to which a high potential voltage VDD is supplied via the switch circuit S0H, and is connected to a wiring for supplying a low potential voltage via the switch circuit S0L.

  The switch circuit S0H is, for example, a P-channel MOS transistor, the high potential voltage VDD is supplied to the source of this transistor, and the drain is connected to the cell unit 31b. The switch circuit S0L is, for example, an N-channel MOS transistor, a low potential voltage is supplied to the source of this transistor, and the drain is connected to the cell portion 31b.

  As described above, the cell unit 31b includes two inverter circuits 34b and 35b. The inverter circuit 34b includes a transistor T1b and a transistor T2b. The inverter circuit 35b includes a transistor T3b and a transistor T4b. Therefore, the sources of the PMOS transistors T1b and T3b are connected to the switch circuit S0H, and the sources of the NMOS transistors T2b and T4b are connected to the switch circuit S0L. That is, the switch circuit S0H is connected to the high potential side power supply terminals of the inverter circuits 34b and 35b, and the switch circuit S0L is connected to the low potential side power supply terminals of the inverter circuits 34b and 35b.

  The switch circuit S0H is turned on / off in response to the signal LPZ2 output from the cell short circuit control circuit 73 shown in FIG. 7, and the switch circuit S0L is turned on / off in response to the signal LPXP output from the cell short circuit control circuit 73. The signal LPZ2 is at H level during the low voltage mode based on the voltage recognition signal LP. Accordingly, the switch circuit S0H is turned on during the normal operation mode and turned off during the low voltage mode. That is, as in the fourth embodiment, the high potential voltage VDD is supplied to the cell unit 31b during the normal operation mode, and the supply of the high potential voltage VDD is stopped during the low voltage mode.

  The signal LPXP is at the L level during the data transfer period. Accordingly, the switch circuit S0L is turned on during the normal operation mode. In addition, the switch circuit S0L is turned off during the data transfer period and turned on after the data transfer period in the low voltage mode. Therefore, the cell portion 31b is in a so-called floating state that is separated from the wiring that supplies the high potential voltage VDD and the wiring that supplies the low potential voltage during the data transfer period.

  In this data transfer period, the word line WL2 is activated to turn on the transfer gates 32b and 33b of the memory cell C0b2, and the input / output ports P1b and P2b of the cell unit 31b are connected to the bit lines BL0z and BL0x, respectively. The The bit line pair BL0z, BL0x is reset to the high potential voltage VDD level (H level) by, for example, the column selector 18 (see FIG. 1) at times other than the read operation and the write operation. Therefore, when the transfer gates 32b and 33b are turned on, the potentials of the ports P1b and P2b rise toward the potentials of the bit line pairs BL0z and BL0x, that is, the H level, as shown in FIG.

Next, as shown in FIG. 9, when the word line WL2 is deactivated, the transfer gates 32b and 33b are turned off, and the ports P1b and P2b are disconnected from the bit lines BL0z and BL0x.
Next, as shown in FIG. 9, when an H level signal LPZ is output from the cell short circuit control circuit 73 (see FIG. 7), the switch circuits S0z and S0x are turned on, and the ports P1b and P2b of the memory cell C0b2 are turned on. Are connected to the ports P1a and P2b of the memory cell C0a, respectively. Then, the levels of the ports P1b and P2b of the subcell C0b2 change according to the levels of the ports P1a and P2a of the connected main cell C0a and eventually become equal to the levels of the ports P1a and P2a of the main cell C0a.

  Next, when the H level signal LPXP is output from the cell short circuit control circuit 73 (see FIG. 7), the switch circuit S0L is turned on, and the cell portion 31b of the memory cell C0b2 is connected to the wiring for supplying the low potential voltage. Is done.

  The levels of the ports P1a and P2a of the main cell C0a correspond to the data held by the main cell C0a. That is, the data held in the main cell C0a is transferred to the subcell C0b2.

As described above, according to the present embodiment, the following effects can be obtained.
(1) In the memory cell C0b, the switch circuits S0H and S0L connected to the inverter circuits 34b and 35b are turned off to stop the supply of the high potential voltage VDD and the low potential voltage to the inverter circuits 34b and 35b. S0x was turned on. As a result, the levels of the ports P1b and P2b of the memory cell C0b are equal to the levels of the ports P1a and P2a of the memory cell C0a, that is, the data of the memory cell C0a can be transferred to the memory cell C0b. Therefore, data in the memory cell C0a can be held when the normal operation mode is switched to the low voltage mode.

  (2) The switch circuits S0H and S0L connected to the inverter circuits 34b and 35b of the memory cell C0b are turned off, and the word line WL2 corresponding to the memory cell C0b is activated. By activating the word line WL2, the levels of the ports P1b and P1b of the memory cell C0b rise toward the level of the bit line pair BL0z and BL0x, that is, the high potential voltage VDD level. Then, after the word line WL2 is deactivated, the switch circuits S0z and S0x are turned on. Then, the level of the corresponding port of the memory cell C0b changes to the low potential voltage level by the driver transistor (T2a or T4a) of the port holding the L level of the memory cell C0a. As a result, the level of the port holding the H level does not change even when the memory cell C0b is connected. That is, the data of the memory cell C0a can be held and the data can be transferred to the memory cell C0b.

(Sixth embodiment)
Hereinafter, a sixth embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same component as the said embodiment.

As shown in FIG. 10, the SRAM 80 includes a memory cell matrix 81 and a cell short-circuit control circuit 82.
The cell short circuit control circuit 82 generates signals LPZ, LPXP, and LPZP based on the voltage recognition signal LP. These signals LPZ, LPXP, LPZP are supplied to the memory cell matrix 81. In FIG. 10, only LPZ is shown as a signal name.

  As shown in FIG. 12, when the voltage recognition signal LP is at L level, the cell short circuit control circuit 82 outputs L level signals LPZ and LPZP and H level signal LPXP. The cell short-circuit control circuit 82 outputs an L level signal LPXP in response to the H level voltage recognition signal LP. When a predetermined time elapses after the H level signal LP is input, the H level signal LPZ is output. Further, when a predetermined time elapses, an H level signal LPXP is output. A period from when the H level voltage recognition signal LP is input to when the H level signal LPXP is output is a data transfer period. The cell short-circuit control circuit 82 outputs an H level signal LPZP for a certain period from the rising timing of the voltage recognition signal LP.

  The signal LPXP and the signal LPZP are one of two memory cells that form a pair, and are supplied to a memory cell in which a word line is not activated at the time of non-writing. This memory cell is called a sub cell, and a memory cell connected to a word line activated at the time of non-writing is called a main cell.

Next, the configuration of the memory cell matrix 81 will be described.
FIG. 11 shows four memory cells C0a, C0b3, C1a, C1b3 included in the memory cell matrix 81 of FIG. Memory cells C0a and C1a are connected to word line WL1, and memory cells C0b3 and C1b3 are connected to word line WL2. The signals LPXP and LPZP are supplied to the memory cells C0b3 and C1b3. The address register 61 shown in FIG. 10 outputs a row address RA so as to activate the word line WL1 during non-writing. That is, the memory cells C0a and C1a are main cells, and the memory cells C0b3 and C1b3 are subcells.

  Memory cell C0b3 includes a cell portion 31b, transfer gates 32b and 33b, and switch circuits S0S and S0L. The cell unit 31b is connected to a wiring for supplying a low potential voltage via the switch circuit S0L.

  The switch circuit S0L is, for example, an N-channel MOS transistor, a low potential voltage is supplied to the source of this transistor, and the drain is connected to the cell portion 31b. As described above, the cell unit 31b includes two inverter circuits 34b and 35b. The inverter circuit 34b includes a transistor T1b and a transistor T2b. The inverter circuit 35b includes a transistor T3b and a transistor T4b. The high potential voltage VDD is supplied to the sources of the PMOS transistors T1b and T3b, and the sources of the NMOS transistors T2b and T4b are connected to the switch circuit S0L.

  The switch circuit S0L is turned on / off in response to the signal LPXP output from the cell short-circuit control circuit 82 shown in FIG. The signal LPXP is at the L level during the data transfer period. Accordingly, the switch circuit S0L is turned on during the normal operation mode. In addition, the switch circuit S0L is turned off during the data transfer period and turned on after the data transfer period in the low voltage mode. Therefore, the cell portion 31b is disconnected from the wiring that supplies the low potential voltage during the data transfer period.

  The switch circuit S0S is connected between the port P1b and the port P2b. The switch circuit S0S is, for example, an N channel MOS transistor, and is turned on / off in response to the signal LPZP. As described above, this signal LPZP is at the H level for a certain period in the data transfer period. Accordingly, the switch circuit S0S is turned on for a certain period in response to the H level signal LPZP. The switched switch circuit S0S connects both ports P1b and P2b to each other, that is, short-circuits both ports P1b and P2b.

  As shown in FIG. 12, since the word lines WL1, WL2 are not activated, the transfer gates 32a, 33a, 32b, 33b of both memory cells C0a, C0b3 are turned off. When an L level signal LPXP is input in the data transfer period, the switch circuit S0L is turned off. When the H level signal LPZP is input, the switch circuit S0S is turned on. The switch circuit S0S that is turned on short-circuits the input / output terminals of the inverter circuits 34b and 35b. In the normal operation mode, the levels of both ports P1b and P2b are complementary levels according to the data held in the memory cell C0b3. When the ports P1b and P2b are connected to each other, the levels of the ports P1b and P2b change toward an intermediate level (a potential between the high potential voltage VDD and the low potential voltage).

  Next, as shown in FIG. 12, when an H level signal LPZ is output from the cell short circuit control circuit 82 (see FIG. 10), the switch circuits S0z and S0x are turned on, and the ports P1b and P2b of the memory cell C0b3 are Are connected to the ports P1a and P2b of the memory cell C0a, respectively. Then, the levels of the ports P1b and P2b of the subcell C0b3 change according to the levels of the ports P1a and P2a of the connected main cell C0a, and eventually become equal to the levels of the ports P1a and P2a of the main cell C0a.

  Next, when the H level signal LPXP is output from the cell short circuit control circuit 82 (see FIG. 10), the switch circuit S0L is turned on, and the cell portion 31b of the memory cell C0b3 is connected to the wiring for supplying the low potential voltage. Is done.

  The levels of the ports P1a and P2a of the main cell C0a correspond to the data held by the main cell C0a. That is, the data held in the main cell C0a is transferred to the subcell C0b3.

As described above, according to the present embodiment, the following effects can be obtained.
(1) In the memory cell C0b, the switch circuit S0L connected to the inverter circuits 34b and 35b is turned off, the supply of the low potential voltage to the inverter circuits 34b and 35b is stopped, and the switch circuit S0S between the ports P1b and P2b is turned on. . By this switch circuit S0S, the levels of both ports P1b and P2b become intermediate levels of the levels of the ports P1b and P2b of the memory cell C0b. By turning on the switch circuits S0z and S0x, the levels of the ports P1b and P2b of the memory cell C0b become equal to the levels of the ports P1a and P2a of the memory cell C0a, that is, the data of the memory cell C0a is transferred to the memory cell C0b. Can be transferred to. Therefore, data in the memory cell C0a can be held when the normal operation mode is switched to the low voltage mode.

  (2) By setting the ports P1b and P2b to the intermediate level, the levels of the ports P1b and P2b can be set in a short time compared to the time required to change the level of one port from the H level to the L level. It can be made equal to the levels of P1a and P2a, and the data transfer period can be shortened.

(Seventh embodiment)
Hereinafter, a seventh embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same component as the said embodiment.

  A semiconductor device 90 shown in FIG. 13 is, for example, a system LSI, and includes a core circuit 91, a peripheral circuit 92, and a memory 93 formed on one chip. Each circuit is connected to each other via a bus 94.

  The core circuit 91 is a CPU, for example. The core circuit 91 accesses the peripheral circuit 92 and the memory 93 via the bus 94. The bus 94 transfers an access address, a control signal, data, and the like. Peripheral circuit 92 includes one or more circuits. Examples of the circuit included in the peripheral circuit 92 include a logic circuit, an interface circuit, and a processing circuit. The memory 93 is used as a memory for temporarily storing data for processing, a cache memory, a buffer memory, and the like.

  The memory 93 includes an access control circuit 95 and two sub memories 96 and 97. The access control circuit 95 is connected to the bus 94, and the two sub memories 96 and 97 are connected to the access control circuit 95.

  The first sub memory 96 is configured as shown in FIG. 14, for example. The sub memory 96 includes a memory cell matrix 101 and an address register 102 for the configuration of one of the SRAMs of the above embodiment, for example, the SRAM 10 of the first embodiment (see FIG. 1). Does not have.

  FIG. 15 shows four memory cells C0a, C0b, C1a, and C1b included in the memory cell matrix 101 of FIG. That is, the memory cell matrix 101 does not have the switch circuits S0z, S0x, S1z, and S1x with respect to the configuration of the memory cell matrix 11 of the first embodiment. The address register 102 outputs the address ADD by dividing it into a row address RA and a column address CA.

  A second sub memory 97 shown in FIG. 13 is one of the SRAMs of the above embodiment, for example, the SRAM 40 of the second embodiment. Therefore, the second sub-memory 97 operates in the low voltage mode based on the voltage recognition signal LP, and the operating voltage range in this mode is wider than the normal operation mode and shifted to the low voltage side. . That is, the second sub memory 97 is a wide range memory capable of widening the operating voltage range.

  On the other hand, since the first sub memory 96 does not have the switch circuits S0z, S0x, etc., the operating voltage range is substantially equal to the operating voltage range of the second sub memory 97 in the normal operation mode. The first sub memory 96 is called a normal memory.

  In order to enable the semiconductor device 90 to operate even at a low voltage, it is sufficient to provide an SRAM corresponding to a low voltage, that is, a wide range memory, like the second sub memory 97. However, the wide range memory requires two switch circuits for every two memory cells. For this reason, the occupied area of the memory cell matrix becomes larger than that of the normal memory. This increases the chip area of the semiconductor device. Further, when the voltage is lowered, the operations of the core circuit 91 and the peripheral circuit 92 are limited, so that the amount of data to be held is reduced. For this reason, mounting the first sub-memory 96, which is a normal memory, and the second sub-memory 97, which is a wide-range memory, on a single chip can cope with low voltage and increase the chip area. Suppressed.

  The access control circuit 95 receives an address ADD, a control signal CNT, and data DI. The control signal CNT includes the clock signal CK, the chip enable signal CE, the write enable signal WE, and the voltage recognition signal LM.

The access control circuit 95 is configured to switch the mode between the normal operation mode and the low voltage mode based on the voltage recognition signal LM.
The access control circuit 95 controls an access (read / write) target based on various signals input from an external circuit via the bus 94. For example, in the normal operation mode, the access control circuit 95 sets the first sub memory 96 and the second sub memory 97 as access targets of the external circuit. On the other hand, in the low voltage mode, the access control circuit 95 sets the first sub memory 96 as a non-access target of the external circuit, and sets the second sub memory 97 as the access target of the external circuit.

  One of the external circuits that access the memory 93 is a core circuit 91. The core circuit 91 outputs an address ADD and a control signal in order to access the memory 93. The core circuit 91 outputs data DI to be written to the memory 93 and receives data DO read from the memory 93.

  The number of bits of the address ADD corresponds to the storage capacity of the memory 93 and the set storage area. The storage capacity of the memory 93 is the total value of the storage capacity of the first sub memory 96 and the storage capacity of the second sub memory 97. For example, the number of bits necessary for accessing the first sub memory 96 is 7 bits (A7 to A0). Similarly, the number of bits necessary for accessing the second sub memory 97 is 7 bits (A7 to A0). The storage areas of the first sub memory 96 and the second sub memory 97 are set to be continuous.

In normal operation mode,
The access control circuit 95 outputs the address AD1 or the address AD2 based on one bit (for example, A8) higher than the addresses of the first sub memory 96 and the second sub memory 97 in the address ADD. In this embodiment, when the corresponding bit is 0, the access control circuit 95 outputs the lower plural bits (8 bits in this embodiment) of the address ADD to the first sub memory 96 as the address AD1, and the bit is 1 In this case, the lower 8 bits of the address ADD are output to the first sub memory 96 as the address AD2.

  Further, the access control circuit 95 outputs a control signal CN1 substantially equal to the control signal CNT to the first sub memory 96, and outputs a control signal CN2 substantially equal to the control signal CNT to the second sub memory 97. To do. The access control circuit 95 outputs the control signal CN2 including the voltage recognition signal LP, and does not include the signal LP in the control signal CN1.

  The access control circuit 95 outputs the data DI as data DI1 and DI2 to the first and second sub memories 96 and 97, respectively. Then, the access control circuit 95 outputs the data DO1 and DO2 output from the first and second sub memories 96 and 97 to the bus 94 as data DO.

  On the other hand, in the low voltage mode, the access control circuit 95 outputs, as the address AD2, the address ADD that accesses a part of the storage area of the first sub memory 96 to the second sub memory 97 to be accessed. To do. A part of the storage area of the first sub memory 96 is an area for storing data necessary for the continuation of the operation among the data stored in the first sub memory 96 by the core circuit 91.

  For example, in the low voltage mode, the core circuit 91 has the number of processes executed in parallel and the amount of data (for example, the number of instructions to be prefetched and the amount of data in the cache). More limited. On the other hand, processing such as system services requires continuous operation even when the operation mode is switched. An area for storing data necessary for such processing is set in the storage area of the first sub-memory 96.

  However, in the low voltage mode, the first sub memory 96 may not be able to reliably retain data from the viewpoint of the operating range. Therefore, by setting the access destination of necessary data in the second sub memory 97 when the normal operation mode is switched to the low voltage mode, the data can be reliably held.

  By the way, in order to continue the operation, it is necessary to store the data stored in the first sub memory 96 in the second sub memory 97. Further, after switching from the low voltage mode to the normal operation mode, it is necessary to read / write the first sub memory 96 again. Therefore, the access control circuit 95 has a data transfer circuit (data transfer function) that transfers data between the first sub memory 96 and the second sub memory 97.

  The data transfer circuit generates addresses AD1 and AD2 for accessing the first sub memory 96 and the second sub memory 97, and reads / writes data from / to the first sub memory 96 and the second sub memory 97. A control signal for performing writing is generated. The data transfer circuit stores the data read from the first sub-memory 96 in the second sub-memory 97 and the data read from the second sub-memory 97 in the first sub-memory. The second data transfer stored in 96 is selectively executed.

  That is, as shown in FIG. 16A, the access control circuit 95 receives the address input via the bus 94 (see FIG. 13) in the normal operation mode and the corresponding first sub memory 96 and the first sub memory 96. 2 to the sub memory 97. Thereby, the first sub memory 96 and the second sub memory 97 are respectively accessed, and the access control circuit 95 inputs / outputs data to / from the first sub memory 96 and the second sub memory 97. Do.

  Next, when switching to the low voltage mode by the voltage recognition signal LM, the access control circuit 95 outputs an H level voltage recognition signal LP to the second sub memory 97, and the second sub memory 97 It operates in the low voltage mode in response to the voltage recognition signal LP. Then, in the data transfer period at the start of the low voltage mode, the access control circuit 95 reads data necessary for the low voltage from the first sub memory 96 by the data transfer circuit 95a as shown in FIG. The data is written into the second sub memory 97. That is, data is transferred from the first sub memory 96 to the second sub memory 97.

  When the data transfer is completed, the access control circuit 95 outputs the input address or the like to the second sub memory 97 as shown in FIG. As a result, the second sub memory 97 becomes an access target, and the access control circuit 95 inputs and outputs data.

Next, when switching to the normal operation mode by the voltage recognition signal LM,
In the data transfer period at the start of the normal operation mode, the access control circuit 95 reads data from the second sub-memory 97 by the data transfer circuit 95a as shown in FIG. Write to the sub memory 96. That is, data is transferred from the second sub memory 97 to the first sub memory 96.

  Then, the access control circuit 95 outputs an L level voltage recognition signal LP to the second sub memory 97, and the second sub memory 97 responds to the voltage recognition signal LP in the normal operation mode. Operate.

  When the data transfer is completed, the access control circuit 95 outputs the input address or the like to the corresponding first sub memory 96 and second sub memory 97 as shown in FIG. Thereby, the first sub memory 96 and the second sub memory 97 are respectively accessed, and the access control circuit 95 inputs / outputs data to / from the first sub memory 96 and the second sub memory 97. Do.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The memory 93 includes a first sub-memory 96 that is a normal memory and a second sub-memory 97 that supports low voltage. When the operation mode is switched, the access control circuit 95 sets a predetermined period from the start of each operation mode as a data transfer period. When the normal operation mode is switched to the low voltage mode, data is transferred from the first sub memory 96 to the second sub memory 97 in the data transfer period. In addition, when the low voltage mode is switched to the normal operation mode, data is transferred from the second sub memory 97 to the first sub memory 96 in the data transfer period. In the normal operation mode, the first sub memory 96 stores data necessary for continuing the operation of the core circuit 91 and the like. Therefore, by transferring this data to the second sub memory 97 corresponding to the voltage reduction, the operation can be stably continued after the voltage reduction.

  (2) The memory 93 includes a first sub-memory 96 that is a normal memory and a second sub-memory 97 that supports low voltage. Therefore, the voltage of the system LSI 90 can be reduced. Since the first sub memory 96 and the second sub memory 97 are provided, the area occupied by the memory 93 is reduced as compared with the case where all the memories are adapted to lower voltage. An increase in area can be suppressed.

In addition, you may implement each said embodiment in the following aspects.
In each of the above embodiments, an SRAM including a memory cell having a CMOS structure is embodied. However, the configuration of the memory cell may be changed as appropriate. For example, the load transistor may be an N-channel MOS transistor (NMOS load type) or a resistor (resistance load type).

In addition, a so-called five-transistor type memory cell in which a transfer gate that connects a cell portion to any one of the bit line pairs is omitted may be used.
In each of the above embodiments, the transfer gate that connects the input / output port to the bit line is an N-channel MOS transistor, but a P-channel MOS transistor may be used. Also, an N channel MOS transistor and a P channel MOS transistor connected in parallel with each other, that is, a CMOS structure may be used.

  In each of the above embodiments, the switch circuit that connects and separates the input / output ports of the two cells is an N-channel MOS transistor, but a P-channel MOS transistor may be used. Also, an N channel MOS transistor and a P channel MOS transistor connected in parallel with each other, that is, a CMOS structure may be used.

  In the first and second embodiments, the first memory cell and the second memory cell connected to the bit line pair to which the first memory cell is connected are connected between the output nodes. However, the output nodes of two memory cells connected to different bit line pairs may be connected to and separated from each other via the switch circuit.

In the fifth embodiment, the level at which the bit line pair is reset may be changed as appropriate. For example, it is set to an intermediate level (for example, VDD / 2) between the high potential voltage VDD and the low potential voltage.
In the seventh embodiment, the supply of the operating voltage (high potential voltage VDD) to the first sub memory 96 that does not support the voltage reduction may be stopped in the low voltage mode. By stopping the supply of the operating voltage to circuits that are not used in this operation mode, current consumption can be reduced.

In the seventh embodiment, the access control circuit 95 may suspend a response, output a data transfer period, a signal indicating that processing is in progress (for example, a busy signal), or the like.
In the seventh embodiment, the storage capacity of the first sub memory 96 and the storage capacity of the second sub memory 97 may be set to different values. In the low voltage mode, the range of the address AD2 output to the second sub memory 97 may be changed as appropriate according to the area for storing data required by the core circuit 91 and the peripheral circuit 92. . Note that the storage area of the first SRAM 96 and the storage area of the second SRAM 97 may not be continuous.

The following notes are disclosed regarding the above embodiments.
(Appendix 1)
A cell unit including two inverter circuits for inputting mutual output signals and having an input / output port to which an output terminal of the inverter circuit is connected; and a transfer gate connected between the input / output port and a bit line. Including first and second memory cells;
A first switch circuit connected between the input / output port of the first memory cell and the input / output port of the second memory cell;
A semiconductor memory device comprising:
(Appendix 2)
A word that activates or deactivates the first word line connected to the transfer gate of the first memory cell and the second word line connected to the transfer gate of the second memory cell. A line control circuit;
The word line control circuit changes an operation mode based on a signal, and activates the first word line and the second word line individually when the operation mode is the first mode, Simultaneously activating the first word line and the second word line when the mode is a second mode different from the first mode;
2. The semiconductor memory device according to appendix 1, wherein:
(Appendix 3)
A first high potential voltage is supplied to the inverter circuit of the first memory cell;
A voltage control circuit for controlling a second high potential voltage supplied to the inverter circuit of the second memory cell according to an operation mode;
The semiconductor memory device according to appendix 1 or 2, characterized by the above.
(Appendix 4)
The voltage control circuit supplies a second high potential voltage equal to the first high potential voltage to the second memory cell in the first mode, and the second control cell supplies the second high potential voltage in the second mode. Supplying a second high potential voltage lower than one high potential voltage to the second memory cell;
The semiconductor memory device according to appendix 3, wherein
(Appendix 5)
The voltage control circuit supplies a second high potential voltage equal to the first high potential voltage to the second memory cell in the first mode, and the second control cell supplies the second high potential voltage in the second mode. 2 stops the supply of high potential voltage,
The semiconductor memory device according to appendix 3, wherein
(Appendix 6)
The word line control circuit activates the first and second word lines during a write operation and activates the first word line during a non-write operation based on a write enable signal in the second mode. Activate and deactivate the second word line;
The semiconductor memory device as set forth in Appendix 2, wherein
(Appendix 7)
The second memory cell is
A second switch circuit connected between a high-potential side power supply terminal of the inverter circuit and a wiring for supplying the high-potential voltage;
A third switch circuit connected between a low-potential side power supply terminal of the inverter circuit and a wiring for supplying the low-potential voltage;
The semiconductor memory device according to any one of appendices 1 to 6, characterized by comprising:
(Appendix 8)
The word line control circuit activates the second word line for a predetermined period in response to a signal for changing an operation mode,
A cell short-circuit control circuit for controlling the first to third switch circuits in response to a signal for changing the operation mode;
The cell short circuit control circuit is:
In response to a signal for changing the operation mode, the second and third switch circuits are turned off, the first switch circuit is turned on, and the third switch circuit is turned on.
The semiconductor memory device according to appendix 7, wherein
(Appendix 9)
The second memory cell is
A second switch circuit connected between the two input / output ports;
A third switch circuit connected between a low-potential side power supply terminal of the inverter circuit and a wiring for supplying the low-potential voltage;
The semiconductor memory device according to any one of appendices 1 to 6, characterized by comprising:
(Appendix 10)
A cell short-circuit control circuit for controlling the first to third switch circuits in response to a signal for changing an operation mode;
The cell short circuit control circuit is:
In response to a signal for changing the operation mode, the third switch circuit is turned off, the second switch circuit is turned on, the first switch circuit is turned on, and the third switch circuit is turned on. ,
The semiconductor memory device according to appendix 9, wherein
(Appendix 11)
First and second sub-memory, and an access control circuit for controlling access to the sub-memory,
The second sub memory is a semiconductor memory device having a switch circuit connected between input / output ports of two memory cells,
The first sub-memory is a semiconductor memory device that does not have the switch circuit,
The access control circuit includes:
When the operation mode is switched from the first mode to the second mode, after the data is transferred from the first sub memory to the second sub memory, the first and second sub memories are Outputs a signal for access,
When data is transferred from the second sub-memory to the first sub-memory when the second mode is switched to the first mode, an access signal to the first sub-memory is sent to the first sub-memory. Output to 2 sub-memory,
A semiconductor device.
(Appendix 12)
A cell unit including two inverter circuits for inputting mutual output signals and having an input / output port to which an output terminal of the inverter circuit is connected; and a transfer gate connected between the input / output port and a bit line. Including first and second memory cells;
When the operation mode is the first mode, the first and second memory cells are individually selected, and data is read or written to the selected one memory cell.
When the operation mode is the second mode, the first and second memory cells are connected by connecting the input / output port of the first memory cell and the input / output port of the second memory cell. Reading or writing one piece of data for
A method for controlling a semiconductor memory device.

C0a, C0b Memory cell 31a, 31b Cell part 32a, 33a, 32b, 33b Transfer gate 34a, 35a, 34b, 35b Inverter circuit P1a, P2a, P1b, P2b Input / output port S0z, S0x switch circuit S0H, S0L switch circuit S0S switch Circuit WL, WL1, WL2 Word line BL0z, BL0x Bit line 12 Address register (word line control circuit)
13 Row decoder (word line control circuit)
17 Word line buffer (word line control circuit)
24 cell short circuit control circuit

Claims (5)

A cell unit including two inverter circuits for inputting mutual output signals and having an input / output port to which an output terminal of the inverter circuit is connected; and a transfer gate connected between the input / output port and a bit line. Including first and second memory cells;
A first switch circuit connected between the input / output port of the first memory cell and the input / output port of the second memory cell;
A semiconductor memory device comprising: A word that activates or deactivates the first word line connected to the transfer gate of the first memory cell and the second word line connected to the transfer gate of the second memory cell. A line control circuit;
The word line control circuit changes an operation mode based on a signal, and activates the first word line and the second word line individually when the operation mode is the first mode, Simultaneously activating the first word line and the second word line when the mode is a second mode different from the first mode;
The semiconductor memory device according to claim 1. A first high potential voltage is supplied to the inverter circuit of the first memory cell;
A voltage control circuit for controlling a second high potential voltage supplied to the inverter circuit of the second memory cell according to an operation mode;
The semiconductor memory device according to claim 1, wherein: First and second sub-memory, and an access control circuit for controlling access to the sub-memory,
The second sub memory is a semiconductor memory device having a switch circuit connected between input / output ports of two memory cells,
The first sub-memory is a semiconductor memory device that does not have the switch circuit,
The access control circuit includes:
When the operation mode is switched from the first mode to the second mode, after the data is transferred from the first sub memory to the second sub memory, the first and second sub memories are Input / output signals for access,
When data is transferred from the second sub-memory to the first sub-memory when the second mode is switched to the first mode, an access signal to the first sub-memory is sent to the first sub-memory. Output to 2 sub-memory,
A semiconductor device. A cell unit including two inverter circuits for inputting mutual output signals and having an input / output port to which an output terminal of the inverter circuit is connected; and a transfer gate connected between the input / output port and a bit line. Including first and second memory cells;
When the operation mode is the first mode, the first and second memory cells are individually selected, and data is read or written to the selected one memory cell.
When the operation mode is the second mode, the first and second memory cells are connected by connecting the input / output port of the first memory cell and the input / output port of the second memory cell. Reading or writing one piece of data for
A method for controlling a semiconductor memory device.

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