JP2011192879A - Non-volatile memory device and method of manufacturing the same - Google Patents

Abstract

The present invention provides a nonvolatile memory device with a high degree of integration and a method for manufacturing the nonvolatile memory device.
A plurality of insulating films and electrode films alternately stacked; a semiconductor pillar penetrating the stacked body; a charge trap film provided between the electrode film and the semiconductor pillar; The electrode film extends in one direction orthogonal to the stacking direction of the stacked body, and is provided with a plurality of spaced apart from each other, and the two semiconductor pillars intersecting and adjacent to the common electrode film Provides a non-volatile memory device characterized in that they intersect at different positions in the width direction of the electrode film.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile memory device and a method for manufacturing the nonvolatile memory device.

  In a conventional nonvolatile memory device (memory), elements are integrated in a two-dimensional plane on a silicon substrate. In order to increase the storage capacity of a memory, the size of one element is reduced (miniaturized), but in recent years, the miniaturization has become difficult in terms of cost and technology.

  On the other hand, in order to increase the storage capacity of a nonvolatile memory device (memory), a batch-processed three-dimensional stacked memory cell has been proposed (see, for example, Patent Document 1). According to this method, since it is possible to form stacked memories in a batch regardless of the number of stacked layers, an increase in cost can be suppressed.

In this collective processing type three-dimensional stacked memory, a stacked body having insulating films and electrode films stacked alternately, a semiconductor pillar (silicon pillar) penetrating the stacked body, a semiconductor pillar (silicon pillar), and an electrode film. And a charge storage layer (storage layer; charge trap film) between them, and thereby a memory cell is provided at the intersection of the semiconductor pillar (silicon pillar) and each electrode film.
However, in recent years, even in such a stacked nonvolatile memory device, it has been desired to achieve higher integration by arranging memory cells more densely in a plane.

JP 2007-266143 A

  The present invention provides a highly integrated nonvolatile memory device and a method for manufacturing the nonvolatile memory device.

  According to one embodiment of the present invention, a plurality of insulating films and electrode films are alternately stacked, a semiconductor pillar passing through the stacked body, and provided between the electrode film and the semiconductor pillar. A charge trap film, and the electrode film extends in one direction perpendicular to the stacking direction of the stacked body, and is provided in a plurality spaced apart from each other. A non-volatile memory device is provided in which the semiconductor pillars of the book cross at different positions in the width direction of the electrode film.

  According to another aspect of the present invention, a step of forming a stacked body in which a plurality of insulating films and sacrificial films are alternately stacked, and a plurality of through holes extending in the stacking direction of the stacked body are formed. A step of forming a semiconductor pillar in the through hole, a step of forming a trench extending in the stacking direction of the stacked body, a step of selectively removing the sacrificial film through the trench, and the semiconductor pillar Forming a charge trap film on the outer peripheral surface side of the substrate, and forming a plurality of electrode films between the insulating film and the insulating film in the stacking direction of the insulating film, and forming the electrode film The electrode film extends in one direction orthogonal to the stacking direction of the insulating film and is formed in a plurality spaced apart from each other, and in the step of forming the through hole, the electrode film extends in the one direction. Two of said through-holes each other Ri is a method of manufacturing a nonvolatile memory device, characterized in that it is formed so as to intersect with each other at different positions in the width direction of the common of the electrode film is provided.

  According to the present invention, a highly integrated nonvolatile memory device and a method for manufacturing the nonvolatile memory device are provided.

1 is a schematic perspective view for illustrating a nonvolatile memory device according to a first embodiment. 1 is a schematic cross-sectional view for illustrating a nonvolatile memory device according to a first embodiment. It is a mimetic diagram for illustrating the arrangement form of a semiconductor pillar. FIG. 6 is a schematic plan view illustrating the positional relationship between bit lines, word lines, select gates, and semiconductor pillars in a nonvolatile memory device according to a comparative example. It is a schematic diagram for illustrating the operation effect of this embodiment. It is a model perspective view for illustrating the nonvolatile memory device concerning a 2nd embodiment. FIG. 5 is a schematic cross-sectional view for illustrating a nonvolatile memory device according to a second embodiment. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. It is a schematic process sectional view for illustrating a method for manufacturing a nonvolatile memory device. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG. 6 is a schematic process cross-sectional view for illustrating the method for manufacturing the nonvolatile memory device. FIG.

Hereinafter, embodiments of the present invention will be illustrated with reference to the drawings.
FIG. 1 is a schematic perspective view for illustrating the nonvolatile memory device according to the first embodiment. In order to avoid complication, only the conductive portion is shown in principle, and the insulating portion is omitted.
FIG. 2 is a schematic cross-sectional view for illustrating the nonvolatile memory device according to the first embodiment. 2A is a diagram viewed from the bit line BL direction (Y direction in FIG. 1), FIG. 2B is a diagram viewed from the word line WL direction (X direction in FIG. 1), and FIG. ) Is a cross-sectional view taken along the line AA in FIG. 2A, FIG. 2D is a cross-sectional view taken along the line BB in FIG. 2B, and FIG. 2E is a portion C in FIG. FIG.
X, Y, and Z in the figure represent an orthogonal coordinate system, which is a direction perpendicular to the upper surface of the silicon substrate 11, that is, a horizontal direction parallel to the upper surface of the silicon substrate 11. The word line WL direction is the X direction, and the bit line BL direction is the Y direction. The same applies to other embodiments described later.

The nonvolatile memory device 1 according to the present embodiment is a three-dimensional stacked flash memory in which a plurality of semiconductor pillars SP are provided in a stacked body in which electrode films and insulating films are stacked alternately. In such a nonvolatile memory device 1, since a channel is formed by connecting a depletion layer formed by applying a voltage to a gate electrode, electrons usually do not exist in the channel. Therefore, even if a pass voltage (Vpass) is applied to a non-selected cell, there is a feature that malfunction due to program disturb or read disturb is unlikely to occur. Further, since the channel is P ⁻ type, holes can be easily drawn from the silicon substrate during erasing. Therefore, the erasing characteristics are good.

  In the nonvolatile memory device 1 according to the present embodiment, the semiconductor pillars SP are arranged in a staggered manner as viewed from the Z direction, as shown in FIGS. 2C and 2D and FIG. 3 described later. ing. For this reason, since the shortest distance between the semiconductor pillars SP can be a certain value or more, a denser arrangement can be achieved, so that higher integration can be achieved. Further, connection to the bit line BL and the source line SL can be facilitated. Details regarding the arrangement of the semiconductor pillars SP will be described later.

Hereinafter, the configuration of the nonvolatile memory device 1 according to the present embodiment will be exemplified.
As shown in FIGS. 1 and 2, the nonvolatile memory device 1 according to the present embodiment is provided with a silicon substrate 11 made of, for example, single crystal silicon. A source line SL is formed on the surface layer portion of the silicon substrate 11 by ion implantation.

On the silicon substrate 11, a memory stacked body ML is provided. In the memory stacked body ML, a plurality of insulating films 14, select gates SG, and a plurality of word lines WL (electrode films) are alternately provided. The insulating film 14 functions as an interlayer insulating film that insulates the word lines WL from each other. Further, a plurality of word lines WL (electrode films) extend in the X direction orthogonal to the stacking direction (Z direction) of the memory stacked body ML and are spaced apart from each other. In the example shown in FIGS. 2A and 2B, four layers of word lines WL are provided, but the present invention is not limited to this.
Furthermore, an insulating film 17 and an insulating film 16 are laminated in this order above the uppermost select gate SG.

  The word line WL is divided in units of erase blocks, and is one conductive film parallel to the XY plane in the erase block. The word line WL can be formed of, for example, tungsten.

The insulating film 14 can be made of an insulating material such as silicon oxide.
The insulating film 16 can be formed of an insulating material such as silicon nitride.
The insulating film 17 can be made of an insulating material such as silicon oxide.
A film necessary for the process, such as a stopper film made of silicon nitride, may be appropriately provided at an arbitrary position between the films.

  A plurality of through holes 18 extending in the stacking direction (Z direction) are formed in the memory stacked body ML. Each through hole 18 penetrates the entire memory stacked body ML. Inside each through hole 18, a semiconductor pillar SP as a semiconductor pillar is embedded.

The semiconductor pillar SP may be formed of a semiconductor, for example, polycrystalline silicon doped with boron. In this case, the boron concentration can be 10 ¹⁷ to 10 ¹⁸ cm ⁻³ . The semiconductor pillar SP may be formed of other semiconductor materials, for example, amorphous silicon or polysilicon, and these semiconductor materials may be doped with impurities or may not be doped. .

The shape of the semiconductor pillar SP is a columnar shape extending in the Z direction, for example, a cylindrical shape.
In this case, the semiconductor pillar SP can have a concentric double structure. That is, each semiconductor pillar SP can be provided with a central portion including the central axis and an outer peripheral portion surrounding the periphery of the central portion. Each of the central portion and the outer peripheral portion extends over the entire length of the semiconductor pillar SP. The outer peripheral portion of the semiconductor pillar SP is formed of silicon containing impurities, such as phosphorus, and functions as a semiconductor portion. That is, in the outer peripheral portion, an inversion layer is formed and a current flows according to the potential of an electrode film disposed in the vicinity thereof, or a depletion layer is formed and a current is interrupted. On the other hand, the central portion of the semiconductor pillar SP is formed of silicon containing impurities and oxygen, and the oxygen concentration of the central portion is between single silicon (Si) and silicon dioxide (SiO ₂ ). Thereby, the central portion functions as a semiconductor portion having a higher resistance than the outer peripheral portion. That is, the central portion can stop the depletion layer extending from the outer peripheral portion to stabilize the threshold value of each memory transistor and allow a certain amount of driving current to flow. Therefore, even if the nonvolatile memory device 1 is highly integrated and the semiconductor pillar SP is thinned, the drive current can be secured while stabilizing the threshold value of the memory cell.

  The semiconductor pillar SP may be solid or cylindrical (hollow pipe). The cylindrical shape (hollow pipe shape) is effective in suppressing variation in threshold voltage (Vth) because the thickness of the semiconductor pillar SP controlled by the gate electrode is equal between the stacked memory cells. is there.

The cross-sectional shape of the semiconductor pillar SP is not particularly limited, but if the cross-sectional shape is circular, the radius of curvature in the tunnel oxide film 24, the charge trap film 23, and the charge block film 22 described later can be made substantially constant.
Moreover, if the cross-sectional shape is an ellipse, a large semiconductor pillar SP can be formed in the long axis direction. In this case, if the major axis direction is the word line WL direction (X direction in FIG. 1), the width direction (Y direction) dimension of the word line WL can be reduced.
The semiconductor pillar SP is provided over the entire length in the stacking direction of the memory stacked body ML, and its lower end is connected to the source line SL of the silicon substrate 11.

As shown in FIG. 2E, in the memory stacked body ML, a tunnel oxide film 24, a charge trap film 23, and a charge block film 22 are stacked in this order on the outer peripheral surface side of the through hole 18. That is, the tunnel oxide film 24, the charge trap film 23, and the charge block film 22 are also disposed between the semiconductor pillar SP and the word line WL. The charge block film 22 is in contact with the word line WL and the tunnel oxide film 24 is in contact with the word line WL. Is in contact with the semiconductor pillar SP. A portion of the word line WL where the semiconductor pillar SP intersects becomes a gate electrode.
2A to 2D, the tunnel oxide film 24, the charge trap film 23, and the charge block film 22 are integrally represented in order to avoid complication.

The charge block film 22 is a film that does not substantially flow current even when a voltage is applied within the drive voltage range of the nonvolatile memory device 1, and has a high dielectric constant material, for example, a dielectric constant that passes through the charge trap film 23. It is made of a material having a dielectric constant higher than that of the material to be formed, for example, alumina.
The charge trap film 23 is a film capable of holding charges, for example, a film including an electron trap site, and is, for example, a silicon nitride film.
The tunnel oxide film 24 is normally insulative, but is a film that allows a tunnel current to flow when a predetermined voltage within the drive voltage range of the nonvolatile memory device 1 is applied. For example, a single-layer silicon oxide film A film or an ONO film (oxide-nitride-oxide film: oxide-nitride-oxide film) is used.

  In this case, the radius of curvature is different between the tunnel oxide film 24 and the charge block film 22, and the electric field can be more strongly concentrated by the tunnel oxide film 24 having a small curvature radius. Therefore, the W / E characteristics can be greatly improved as compared with the planar MONOS structure. It is also effective for performing MLC (multi-level cell) operation.

A drain region 15 into which arsenic is ion-implanted is provided at the upper end of the semiconductor pillar SP.
Furthermore, an insulating film 19 and a plug P1 embedded in the insulating film 19 are provided on the memory stacked body ML. The insulating film 19 is provided so as to embed the plug P1, and as shown in FIG. 2B, the insulating film 19 is provided so as to divide the memory stacked body ML in the Y direction.

The insulating film 19 can be made of an insulating material such as TEOS / O ₃ .
The plug P1 can be made of a metal such as tungsten.

  Above these, a plurality of bit lines BL extending in the Y direction are provided. The bit line BL is made of metal. Each bit line BL is disposed so as to pass through a region immediately above the semiconductor pillar SP of each column disposed along the Y direction, and is connected to the upper end portion of the semiconductor pillar SP via a plug P1. Yes. Thereby, the semiconductor pillar SP is connected between the bit line BL and the source line SL. The semiconductor pillar SP is connected to a different bit line BL for each column extending in the Y direction. An insulating layer 20 is provided on the bit lines BL and between the bit lines BL, and wirings 25 and 26 and insulating layers 27 and 28 are appropriately provided on the upper surface thereof. In addition, plugs (not shown) for wiring such as the bit lines BL and the word lines WL are appropriately provided.

Such a stacked nonvolatile memory device has the following advantages.
(1) Since the number of steps hardly increases with respect to the number of layers, the manufacturing cost per bit can be reduced as the number of steps is increased.
(2) Since the semiconductor pillar (silicon channel) is sequentially surrounded by the tunnel oxide film, the charge trap film, the charge block film, and the gate electrode, the electric field is concentrated on the tunnel oxide film having a smaller curvature radius than the charge block film. be able to. Therefore, the write / erase speed characteristic (W / E characteristic) for the memory cell can be greatly improved as compared with the planar MONOS structure.

However, in such a stacked nonvolatile memory device, it is necessary to form a MONOS structure on the side wall of a semiconductor pillar (silicon channel) standing upright to the substrate. For this reason, it is difficult to reduce the distance between adjacent semiconductor pillars (silicon channels), and there is a restriction on the cell arrangement on the plane that the limit of miniaturization is about 65 to 50 nm (nanometer) at half pitch. As a result, there is also a problem that the number of stacked layers reaches 10 or more.
Therefore, in the nonvolatile memory device 1 according to the present embodiment, the semiconductor pillar SP is arranged as illustrated below, so that the memory cells are more densely arranged in the plane and further integrated. It tries to make it.

Next, the arrangement form of the semiconductor pillar SP will be further illustrated.
FIG. 3 is a schematic view for illustrating the arrangement form of the semiconductor pillar SP.
As shown in FIG. 3, in the nonvolatile memory device 1, two semiconductor pillars SP that intersect and are adjacent to a common select gate SG and a common word line WL (electrode film) are connected in the width direction (Y (Direction) intersect at different positions. More specifically, the plurality of semiconductor pillars SP crossing the common select gate SG and the common word line WL are alternately arranged along one side in the width direction (Y direction) of the word lines WL along the X direction. The plurality of semiconductor pillars SP intersecting with the other side and disposed along the Y direction intersect with each other on the same side in the width direction (Y direction) of the word line WL.

  That is, all of the plurality of semiconductor pillars SP commonly connected to a certain bit line BL cross the word line WL on the same side in the width direction, for example, the + Y direction side, and are arranged next to the bit line BL. The plurality of semiconductor pillars SP commonly connected to the other bit lines BL cross the word line WL on the opposite side in the width direction, for example, on the −Y direction side. As a result, the semiconductor pillars SP are arranged in a staggered manner when viewed from the Z direction.

  Next, in order to illustrate the effect of this embodiment, it illustrates about the comparative example of this embodiment. FIG. 4 is a schematic plan view illustrating the positional relationship between the bit line, the word line, the select gate, and the semiconductor pillar in the nonvolatile memory device according to the comparative example.

  As shown in FIG. 4, in the nonvolatile memory device 101 according to the comparative example, all the semiconductor pillars SP intersect at the same position in the width direction of the word line WL, specifically, at the center. Thus, the semiconductor pillars SP are arranged in a matrix along the X direction and the Y direction when viewed from the Z direction. Other configurations in the comparative example are the same as those in the first embodiment.

Hereinafter, the effects of the present embodiment will be illustrated in comparison with the above-described comparative example.
FIG. 5 is a schematic diagram for illustrating the function and effect of this embodiment.
FIGS. 5A and 5B are schematic plan views illustrating the effects of the present embodiment. FIG. 5A illustrates an apparatus according to a comparative example, and FIG. 5B illustrates an apparatus according to the present embodiment. .

As shown in FIG. 5 (a), in the nonvolatile memory device 101 according to the comparative example, when the minimum feature size and F _1, the diameter of the through-hole 18 (see FIG. 2) is F _1, through-holes the diameter of the buried semiconductor pillar SP in 18 is less than F _1. The width of the word line WL is 2F ₁ because the through hole 18 must be formed therein, and the interval between the word lines WL is F ₁ . The bit line BL because the may be connected via a plug P1 to the semiconductor pillar SP, its width is F _1, the spacing between the bit lines BL is also F _1. Thus, X-direction of the length of one memory cell is 2F _1, the length of the Y direction is 3F _1, therefore, the cell area is _6F ^{1 2.} In this case, the shortest distance L ₁ between the center axis of the semiconductor pillar SP is the distance between the center axis of the semiconductor pillar SP adjacent in the X direction, it is L 1 ₌ 2F _1.

In contrast, as shown in FIG. 5 (b), in the nonvolatile memory device 1 according to this embodiment, when the minimum feature size and F _2, the width of the word line WL is 3F _2, word spacing between lines WL is _{F 2.} The width of the bit line BL contrast is _{F 3,} the spacing between the bit lines BL is _{F 2.} Since 2F ₃ is equal to the diameter of the semiconductor pillar SP, it becomes F ₂ . That is, the length in the X direction of one memory cell is 2F ₃ = F ₂ , the length in the Y direction is 4F ₂ , and thus the cell area is 4F ₂ ² .
As described above, according to the present embodiment, the semiconductor pillars SP are arranged in a staggered manner, thereby reducing the shortest distance in the X direction between the semiconductor pillars SP and preventing the interference between the semiconductor pillars SP, and the cell area. Can be reduced. As a result, a non-volatile memory device with a high degree of integration can be realized.

  In a three-dimensional stacked nonvolatile memory device such as the nonvolatile memory device 1, as a technique for miniaturizing a memory cell, it is conceivable to reduce the diameter of the through-hole 18 and the arrangement period of the bit lines BL. . In general, as a method of reducing the diameter of a hole, there is a method of once filling a hole with a spacer after forming the hole. However, in the case of the nonvolatile memory device 1, since a sufficient electric field needs to be formed between the word line WL and the semiconductor pillar SP, the through hole 18 cannot be backfilled with a spacer. On the other hand, shortening the arrangement period of the bit lines BL can be realized by, for example, a sidewall processing method. The miniaturization of the memory cell in the present embodiment can also be easily realized by applying an existing technique because it also shortens the bit line arrangement cycle.

  Further, according to the present embodiment, the bit line pitch can be halved compared to the word line pitch. Therefore, the bit density can be improved. However, in order to avoid the interference of the semiconductor pillar in the Y direction, the length of the memory cell in the Y direction is about 1.3 times longer. This means that when the number of stacked layers is the same, a bit density of about 1.7 times that of the comparative example described above can be realized. Alternatively, when the bit density is equivalent, the number of stacked layers is approximately 1 / 1.7 as compared with the above-described comparative example. That is, it is possible to realize a higher bit density with a smaller number of stacks, that is, with a three-dimensional structure having a lower height. Therefore, it is possible to provide a nonvolatile memory device having a higher bit density without imposing a heavy burden on integration.

Next, a second embodiment of the present invention will be illustrated.
FIG. 6 is a schematic perspective view for illustrating the nonvolatile memory device according to the second embodiment. In order to avoid complication, only the conductive portion is shown in principle, and the insulating portion is omitted.
FIG. 7 is a schematic cross-sectional view for illustrating the nonvolatile memory device according to the second embodiment. 7A is a diagram viewed from the bit line BL direction (Y direction in FIG. 6), FIG. 7B is a diagram viewed from the word line WL direction (X direction in FIG. 6), and FIG. ) Is a cross-sectional view taken along the line DD in FIG. 7A, FIG. 7D is a cross-sectional view taken along the line E-E in FIG. 7B, and FIG. 7E is a section F in FIG. FIG.
In addition, the same components as those in the nonvolatile memory device 1 according to the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

  In the present embodiment, adjacent semiconductor pillars SP standing upright on the upper surface of the silicon substrate 11 are connected by phosphorus-doped N-type polycrystalline silicon, and the select gate is provided only above the semiconductor pillar SP. ing. In other words, this is an example of a three-dimensional stacked flash memory in which the number of layers for forming the select gate is only one. According to the present embodiment, the source line SL and the bit line BL can be formed in one processing step by further pulling out the source line SL and the bit line BL in the same direction.

As shown in FIGS. 6 and 7, the nonvolatile memory device 2 according to the present embodiment is lower in the insulation of the lowermost layer of the memory stacked body ML than the nonvolatile memory device 1 according to the first embodiment described above. The insulating film 29 and the channel 30 are provided between the film 14 and the silicon substrate 11, the source lines SL are provided alternately with the bit lines BL, and the inner periphery of the through hole 18 is doped with boron. The difference is that the polycrystalline silicon film 31 is provided and a plug P2 for connecting the source line SL to the upper end portion of the semiconductor pillar SP is provided.
The insulating film 29 can be made of an insulating material such as silicon oxide.
The channel 30 may be formed of, for example, polycrystalline silicon doped with phosphorus.
The lower end of the polycrystalline silicon film 31 doped with boron is connected to the channel 30. The polycrystalline silicon film 31 has a cylindrical shape (hollow pipe shape), but may be solid. In this case, if the cylindrical shape (hollow pipe shape) is used, the thickness of the semiconductor pillar SP controlled by the gate electrode becomes equal between the stacked memory cells, so that variation in threshold voltage (Vth) is suppressed, and This is effective for improving the cutoff performance.
The plug P2 can be made of a metal such as tungsten.

That is, the non-volatile memory device 2 is provided below the memory stacked body ML, and has a lower end portion of a first semiconductor pillar formed at a position intersecting on one side in the width direction of the electrode film, and adjacent to the electrode film. A channel 30 provided at a position where the lower end portion of the second semiconductor pillar formed at the position where the other electrode film intersects the other side in the width direction of the matching electrode film and the memory stacked body ML are provided; A plurality of bit lines BL extending in the direction and a plurality of source lines SL provided above the memory stacked body ML and extending in the Y direction, and any of the first semiconductor pillar and the second semiconductor pillar One upper end of the first semiconductor pillar and the second semiconductor pillar is connected to the bit line BL, and the other upper end of the first semiconductor pillar is connected to the source line SL.
Further, the bit lines BL and the source lines SL are alternately arranged.

Also in the nonvolatile memory device 2 according to the present embodiment, the semiconductor pillars SP are arranged in a staggered manner as viewed from the Z direction, as shown in FIGS. 6, 7 (c), and (d). Yes.
Therefore, the same effect as the above-described nonvolatile memory device 1 can be enjoyed. That is, by disposing the semiconductor pillars SP in a staggered manner, the cell area can be reduced while maintaining the shortest distance between the semiconductor pillars SP and preventing interference between the semiconductor pillars SP. As a result, a non-volatile memory device with a high degree of integration can be realized.
Further, the bit line pitch can be halved compared to the word line pitch. Therefore, the bit density can be improved. This means that when the number of stacked layers is the same, a bit density that is about twice that of the above-described comparative example can be realized. Alternatively, when the bit density is equivalent, the number of stacked layers is about ½ as compared with the comparative example described above. That is, it is possible to realize a higher bit density with a smaller number of stacks, that is, with a three-dimensional structure having a lower height. Therefore, it is possible to provide a nonvolatile memory device having a higher bit density without imposing a heavy burden on integration.

  In addition, in the nonvolatile memory device 2 according to the present embodiment, the source line SL and the bit line BL can be drawn out in the same direction, so that the source line SL and the bit line BL are formed in one processing step. can do. Therefore, it is possible to reduce manufacturing steps and costs.

Next, a third embodiment of the present invention will be illustrated.
8 to 14 are schematic process cross-sectional views for illustrating the method for manufacturing the nonvolatile memory device 1.
In each figure, (a) is a side sectional view in the bit line BL direction (Y direction in FIG. 1), (c) is a sectional view taken along line GG in (a), and (b) is in the word line WL direction. (D) is a HH arrow cross-sectional view in (b).

First, as shown in FIGS. 8A to 8D, a peripheral circuit (not shown) of the nonvolatile memory device 1 is formed on the silicon substrate 11. Further, an N-type source region 102 to be the source line SL is formed. Then, in order to form the memory stacked body ML on the entire surface of the silicon substrate 11, six layers of silicon oxide films 103 and silicon nitride films 104 are alternately formed by PECVD (Plasma-Enhanced Chemical Vapor Deposition). Thereafter, a silicon oxide film 105 and a silicon nitride film 106 are further formed to form a stacked body of the silicon nitride film and the silicon oxide film.
Note that the formed stack is not limited to a silicon nitride film or a silicon oxide film. A sacrificial film capable of highly selective etching can be selected as appropriate. Also, the method of forming the laminated body is not limited to the PECVD method. For example, the SACVD (Semi-Atmospheric Chemical Vapor Deposition) method, the LPCVD (Low Pressure Chemical Vapor Deposition) method, the sputtering method, the SOD (Spin On Dielectric). ) Method. Moreover, these methods can also be combined suitably.
As an example, the case where six layers of the silicon oxide film 103 and the silicon nitride film 104 are alternately formed has been described, but the number of stacked layers is not limited to this.

Next, as shown in FIGS. 9A to 9D, a carbon film (not shown) is formed on the entire surface by a CVD (Chemical Vapor Deposition) method, and a known lithography method and a reactive ion etching method are used. A through-hole 128 communicating with the silicon substrate 11 is formed by batch processing the laminated body illustrated in FIG. Subsequently, the formed carbon film is removed to form a semiconductor pillar SP mold.
At this time, as shown in FIGS. 9C and 9D, the through holes 128 are arranged in a staggered manner. In this way, since the shortest distance between the polycrystalline silicon film 107, which will be described later, and thus the semiconductor pillars SP described above becomes a certain value or more, a denser arrangement can be achieved. Integration can be achieved. Further, connection to a tungsten film 112 (bit line BL) and a source region 102 (source line SL), which will be described later, can be facilitated. The staggered arrangement is the same as that described above, and a description thereof is omitted.

Next, as shown in FIGS. 10A to 10D, by forming a polycrystalline silicon film 107 doped with boron by LPCVD (Low Pressure Chemical Vapor Deposition) method, the through hole 128 is buried and the lower end is filled. Connect to source region 102. In this case, the boron concentration can be 10 ¹⁷ to 10 ¹⁸ cm ⁻³ . Further, the through hole 128 can be completely filled with the polycrystalline silicon film 107 doped with boron, or can be buried in a cylindrical shape (hollow pipe shape). If it is embedded in a cylindrical shape (hollow pipe shape), the thickness of the semiconductor pillar SP controlled by the gate electrode becomes equal between the stacked memory cells, so that variation in threshold voltage (Vth) is suppressed. It is effective for.
Further, the polycrystalline silicon film 107 doped with boron in the vicinity of the upper end of the through hole 128 is etched back. Subsequently, a drain region 108 into which arsenic is ion-implanted is formed in the vicinity of the upper end of the polycrystalline silicon film 107 doped with boron by a known lithography method and ion implantation method.

  Next, as shown in FIGS. 11A to 11D, a carbon film (not shown) is formed on the entire surface by a CVD (Chemical Vapor Deposition) method, and a known lithography method and a reactive ion etching method are used. The laminated body illustrated in FIG. 5 is collectively processed to form a trench 129, and the laminated body is divided into gate electrode shapes. Subsequently, the formed carbon film is removed.

  Next, as shown in FIGS. 12A to 12D, the silicon nitride film 104 is selectively removed by hot phosphoric acid through the trench 129 to form a cavity serving as a template for forming the MONOS structure. . At this time, since the polycrystalline silicon film 107 serves as a column and supports the silicon oxide films 103, 105, and 106, the cavity is not collapsed.

  Next, as shown in FIGS. 13A to 13D, a tunnel oxide film 24, a charge trap film 23, and a charge block film 22 constituting the MONOS cell are formed. In order to avoid complication, the tunnel oxide film 24, the charge trap film 23, and the charge block film 22 are integrally shown in FIGS. Here, FIG.13 (e) is a model enlarged view of the I section in Fig.13 (a).

  For example, the tunnel oxide film 24 is an ONO film (oxide-nitride-oxide film: silicon oxide-silicon nitride-silicon oxide film) formed by LPCVD (Low Pressure Chemical Vapor Deposition), and the charge trap film 23 is The silicon nitride film formed by the ALD (Atomic Layer Deposition) method and the charge block film 22 can be an alumina film formed by the ALD (Atomic Layer Deposition) method. In this structure, the tunnel oxide film 24 and the charge block film 22 have different radii of curvature, and the electric field can be concentrated more strongly by the tunnel oxide film 24 having a small curvature radius. Therefore, the W / E characteristics can be greatly improved as compared with the planar MONOS structure. It is also effective for performing MLC (multi-level cell) operation.

Further, a tungsten film 110 is formed by a CVD (Chemical Vapor Deposition) method, and the tungsten film 110 is processed by a dry etching method using CF ₄ to form a gate electrode (word line WL) for each of the stacked memory layers. Divide like so.

Next, as shown in FIGS. 14A to 14D, a TEOS / O ₃ film 111 is formed on the entire surface and planarized. Then, a contact hole communicating with the tungsten film 110 and the drain region 108 is formed, and a plug is formed by filling the tungsten film 112 using a CVD (Chemical Vapor Deposition) method.
Thereafter, the bit line BL, the insulating layer 20, the wiring 25, the insulating layer 27, the wiring 26, and the insulation 28 are sequentially formed by a multilayer wiring process.

  As illustrated above, in the method for manufacturing the nonvolatile memory device according to this embodiment, a plurality of insulating films (for example, silicon oxide film 103) and sacrificial films (for example, silicon nitride film 104) are alternately formed. A step of forming a laminated body, a step of forming a plurality of through holes 128 extending in the stacking direction of the laminated body, and depositing silicon while introducing impurities into the through holes 128 to form the semiconductor pillar SP. A step, a step of forming a trench 129 extending in the stacking direction of the stacked body, a step of selectively removing the sacrificial film through the trench 129, and a step of forming the charge trap film 23 on the outer peripheral surface side of the semiconductor pillar SP. And a step of forming a plurality of electrode films (for example, tungsten film 110) between the insulating films in the stacking direction of the insulating films, In the step of forming the polar film, the electrode film extends in one direction (for example, the X direction in FIG. 1) orthogonal to the stacking direction of the insulating films, and is formed with a plurality of electrodes spaced apart from each other. The two through holes adjacent in one direction (for example, the X direction in FIG. 1) intersect with each other at different positions in the width direction of the common electrode film (for example, the tungsten film 110). It is formed.

  More specifically, in the step of forming the through holes 128, the plurality of through holes 128 formed along one direction (for example, the X direction in FIG. 1) are alternately formed along the one direction. The electrode film (for example, the tungsten film 110) is formed at a position where one side and the other side in the width direction intersect, and is orthogonal to the stacking direction (for example, the Z direction in FIG. 1) and to one direction. The plurality of through holes 128 formed along other directions intersecting each other (for example, the Y direction in FIG. 1) are formed at positions where they intersect with each other on the same side in the width direction of the electrode film. Further, in the step of forming the semiconductor pillar SP, silicon is deposited while introducing impurities into the outer peripheral portion of the through-hole 128 to form the cylindrical (hollow pipe-shaped) semiconductor pillar SP.

2, for example, the source region 102 is the source line SL, the silicon oxide film 103 is the insulating film 14, the silicon oxide film 105 is the insulating film 17, the silicon oxide film 106 is the insulating film 16, and polycrystalline silicon. The film 107 is a semiconductor pillar SP, the drain region 108 is a drain region portion 15, the tungsten film 110 is a word line WL, the TEOS / O ₃ film 111 is an insulating film 19, and the tungsten film 112 is a plug P1.

  According to the present embodiment, the above-described nonvolatile memory device 1 can be efficiently manufactured. In this case, the bit line pitch can be halved compared to the word line pitch. Therefore, the bit density can be improved. This means that when the number of stacked layers is the same, a bit density of about 1.7 times that of the comparative example described above can be realized. Alternatively, when the bit density is equivalent, the number of stacked layers is approximately 1 / 1.7 as compared with the above-described comparative example. That is, it is possible to realize a higher bit density with a smaller number of stacks, that is, with a three-dimensional structure having a lower height. Therefore, it is possible to manufacture a nonvolatile memory device having a higher bit density without imposing a heavy burden on integration.

Next, a fourth embodiment of the present invention will be illustrated.
15 to 23 are schematic process cross-sectional views for illustrating the method for manufacturing the nonvolatile memory device 2.
In each figure, (a) is a side sectional view in the bit line BL direction (Y direction in FIG. 7), (c) is a sectional view taken along line JJ in (a), and (b) is in the word line WL direction. FIG. 7 is a side cross-sectional view (in the X direction in FIG. 7), and FIG.

  First, as shown in FIGS. 15A to 15D, a peripheral circuit (not shown) of the nonvolatile memory device 2 is formed on the silicon substrate 11. Then, a silicon oxide film 202 is formed in a portion to be a memory cell, and a trench is formed by a known lithography method and reactive ion etching method. Thereafter, a polycrystalline silicon film 203 doped with phosphorus is buried, and this is left only in the trench. That is, the channel 30 illustrated in FIG. 7 is formed.

Next, as shown in FIGS. 16A to 16D, in order to form the memory stacked body ML, the silicon oxide film 204 and the silicon nitride film 205 are alternately formed by LPCVD (Low Pressure Chemical Vapor Deposition) method. 6 layers are formed. Thereafter, a silicon oxide film 204a and a silicon nitride film 205a are further formed, and a laminated body of the silicon nitride film and the silicon oxide film is formed.
Note that the formed stack is not limited to a silicon nitride film or a silicon oxide film. A sacrificial film capable of highly selective etching can be selected as appropriate. Further, the method of forming the laminate is not limited to the LPCVD method. For example, the PECVD method, the SACVD (Semi-Atmospheric Chemical Vapor Deposition) method, the LPCVD (Low Pressure Chemical Vapor Deposition) method, the sputtering method, the SOD (SOD) Spin On Dielectric) method. Moreover, these methods can also be combined suitably.
As an example, the case where six layers of silicon oxide films 204 and silicon nitride films 205 are alternately formed has been described, but the number of stacked layers is not limited to this.

  Next, as shown in FIGS. 17A to 17D, a carbon film (not shown) is formed on the entire surface by a CVD (Chemical Vapor Deposition) method, and a known lithography method and a reactive ion etching method are used. The laminated body illustrated in 16 is collectively processed to form a trench. Subsequently, a silicon oxide film 206 is buried on the entire surface, and planarized by CMP (Chemical Mechanical Polishing) using the silicon nitride film 205a as a stopper. The purpose of the trench in which the silicon oxide film 206 is buried is to suppress erroneous writing to a re-adjacent non-selected cell during reading and writing.

Next, as shown in FIGS. 18A to 18D, a through hole 228 communicating with the polycrystalline silicon film 203 doped with phosphorus is formed. Subsequently, the formed carbon film is removed to form a semiconductor pillar SP mold.
At this time, as shown in FIGS. 18C and 18D, the through holes 228 are arranged in a staggered manner so as to sandwich the silicon oxide film 206 embedded in the trench. In this way, since the shortest distance between the polycrystalline silicon film 207, which will be described later, and between the semiconductor pillars SP described above is equal to or greater than a certain value, a denser arrangement can be achieved. Integration can be achieved. Further, connection to a bit line BL and a source line SL described later can be facilitated. The staggered arrangement is the same as that described above, and a description thereof is omitted.

Next, as shown in FIGS. 19A to 19D, by forming a polycrystalline silicon film 207 doped with boron by LPCVD (Low Pressure Chemica Vapor Deposition) method, the through hole 228 is buried and the lower end is filled. Connected to the polycrystalline silicon film 203. In this case, the boron concentration can be 10 ¹⁷ to 10 ¹⁸ cm ⁻³ . Further, it can be embedded in a cylindrical shape (hollow pipe shape) by the polycrystalline silicon film 207 doped with boron, or the through hole 228 can be completely embedded. If it is embedded in a cylindrical shape (hollow pipe shape), the thickness of the semiconductor pillar SP controlled by the gate electrode becomes equal between the stacked memory cells, so that variation in threshold voltage (Vth) is suppressed. It is effective for.

Further, a silicon oxide film 208 is embedded by an ALD (Atomic Layer Deposition) method. Subsequently, the silicon oxide film 208 is retreated using a reactive ion etching method to bury a polycrystalline silicon film doped with boron. Then, arsenic is ion-implanted into the boron-doped polycrystalline silicon film using a known lithography method and ion implantation method to form a source region 209 and a drain region 210.
19 (e) is a cross-sectional view taken along line LL in FIG. 19 (a), and FIG. 19 (f) is a cross-sectional view taken along line MM in FIG. 19 (b).

  Next, as shown in FIGS. 20A to 20D, a carbon film (not shown) is formed on the entire surface by a CVD (Chemical Vapor Deposition) method, and a known lithography method and a reactive ion etching method are used. The laminated body illustrated in FIG. 5 is collectively processed to form a trench 229, and the laminated body is divided into gate electrode shapes. Subsequently, the formed carbon film is removed.

  Next, as shown in FIGS. 21A to 21D, the silicon nitride film 205 is selectively removed through the trench 229 by vapor etching using hydrofluoric acid vapor to form a MONOS structure. A cavity is formed as a mold for the purpose.

Next, as shown in FIGS. 22A to 22D, a tunnel oxide film 24, a charge trap film 23, and a charge block film 22 constituting the MONOS cell are formed. In order to avoid complication, in FIGS. 22A to 22D, the tunnel oxide film 24, the charge trap film 23, and the charge block film 22 are integrally shown. Here, FIG.22 (e) is a model enlarged view of the N section in Fig.22 (a).
For example, the tunnel oxide film 24 is a thermal oxide film formed by ISSG (In-Situ Steam Generator) oxidation, the charge trap film 23 is a silicon nitride film formed by an ALD (Atomic Layer Deposition) method, and the charge block film 22 is A hafnia film formed by an ALD (Atomic Layer Deposition) method can be obtained.

In this structure, the tunnel oxide film 24 and the charge block film 22 have different radii of curvature, and the electric field can be concentrated more strongly by the tunnel oxide film 24 having a small curvature radius. Therefore, the W / E characteristics can be greatly improved as compared with the planar MONOS structure. It is also effective for performing MLC (multi-level cell) operation.
Further, a tungsten film 213 is formed by a CVD (Chemical Vapor Deposition) method, and the tungsten film 213 is processed by a dry etching method using CF ₄ to form gate electrodes (word lines WL) for the respective memory layers stacked. Divide like so.

Next, as shown in FIGS. 23A to 23D, a TEOS / O ₃ film 215 is formed on the entire surface and planarized. Then, contact holes communicating with the tungsten film 213, the source region 209, and the drain region 210 are formed, and a plug is formed by filling the tungsten film 214 with a CVD (Chemical Vapor Deposition) method.
Thereafter, the bit line BL, the source line SL, the insulating layer 20, the wiring 25, the insulating layer 27, the wiring 26, and the insulation 28 are sequentially formed by a multilayer wiring process.

As illustrated above, in the method for manufacturing the nonvolatile memory device according to this embodiment, the first electrode film (for example, tungsten film 213) is formed at a position where it intersects on one side in the width direction. The second through hole formed at the position where the lower end of the first through hole 228 and the second electrode film (for example, tungsten film 213) adjacent to the first electrode film intersect on the other side in the width direction. A step of forming the channel 30 (polycrystalline silicon film 203) at a position where the lower end portion of 228 is in contact with each other, and a plurality of portions provided above the semiconductor pillar SP and extending in other directions (for example, the Y direction in FIG. 6). A step of forming a plurality of bit lines BL and a plurality of source lines SL provided above the semiconductor pillar SP and extending in another direction (for example, the Y direction in FIG. 6). An upper end of one of the semiconductor pillar SP formed by the first through hole 228 and the semiconductor pillar SP formed by the second through hole 228 in the step of forming the bit line BL. The portion is connected to the bit line BL, and in the step of forming the source line SL, either the semiconductor pillar SP formed by the first through hole 228 or the semiconductor pillar SP formed by the second through hole 228 Is connected to the source line SL.
In the step of forming the bit line BL or the step of forming the source line SL, the bit line BL and the source line SL are formed so as to be alternately arranged.

7, for example, the silicon oxide film 202 is the insulating film 29, the polycrystalline silicon film 203 is the channel 30, the silicon oxide film 204 is the insulating film 14, the silicon oxide film 204a is the insulating film 17, and the silicon nitride. The film 205a is the insulating film 16, the polycrystalline silicon film 207 is the polycrystalline silicon film 31, the silicon oxide film 208 is the semiconductor pillar SP, the drain region 210 is the drain region portion 15, the tungsten film 213 is the word line WL, and the TEOS / O ₃ film. 215 becomes the insulating film 19.

  According to the present embodiment, the above-described nonvolatile memory device 2 can be efficiently manufactured. In this case, the bit line pitch can be halved compared to the word line pitch. Therefore, the bit density can be improved. This means that when the number of stacked layers is the same, a bit density of about 1.7 times that of the comparative example described above can be realized. Alternatively, when the bit density is equivalent, the number of stacked layers is approximately 1 / 1.7 as compared with the above-described comparative example. That is, it is possible to realize a higher bit density with a smaller number of stacks, that is, with a three-dimensional structure having a lower height. Therefore, it is possible to manufacture a nonvolatile memory device having a higher bit density without imposing a heavy burden on integration.

Heretofore, the present embodiment has been illustrated. However, the present invention is not limited to these descriptions.
As long as the features of the present invention are provided, those skilled in the art appropriately modified the design of the above-described embodiments are also included in the scope of the present invention.
For example, the film configuration of the laminate and the formation method thereof, the MONOS film structure, the processing method, and the like are not limited to those illustrated, and any combination is possible as long as the features of the present invention are provided. . It is also possible to use, as a semiconductor pillar SP (channel semiconductor), a known method not exemplified, for example, a polycrystalline silicon film crystallized by a laser annealing method or a Ni catalyst method, or a single crystal silicon film. . In this case, a semiconductor containing a different element such as germanium can be used. As the charge block film in the MONOS structure, in addition to Al ₂ O ₃ (alumina), a plurality of metal oxide films such as HfO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , or the above metal films are used. It is possible to use a membrane in which species are combined. In addition to the electrode film (word line WL) exemplified in the MONOS structure, TaN, W, WSi, CoSi, NiSi, PrSi, NiPtSi, PtSi, Pt, Ru, RuO ₂ or the like can be used. is there.

  Further, in the method of manufacturing the nonvolatile memory device according to the present embodiment, the memory cell is formed so as to be electrically connected to the silicon substrate immediately above the silicon substrate (the nonvolatile memory device according to the third embodiment Manufacturing method) as well as when a memory cell is formed on a silicon substrate via a dielectric film (insulating layer) and connected to a peripheral circuit via a multilayer wiring (nonvolatile memory according to the fourth embodiment) The present invention can also be applied to an apparatus manufacturing method. Particularly in the latter case, the bit density can be further improved by providing the memory cell immediately above the peripheral circuit. In this case, in order to realize a channel structure similar to that of the nonvolatile memory device according to the second embodiment, the upper part of the vertical channel may be connected with a polycrystalline silicon film doped with phosphorus or the like.

Further, it is apparent that the present invention can be applied not only to a smaller number than the illustrated number of stacked layers (6 layers) but also to a nonvolatile memory device having a multilayer (for example, 10 layers or more).
Further, by using the present invention, it is possible to continuously improve the degree of integration of the nonvolatile memory device in the future, and it is expected that various application fields will be expanded. Moreover, each element with which each embodiment mentioned above is combined can be combined as much as possible, and what combined these is also included in the scope of the present invention as long as the characteristics of the present invention are included.

  DESCRIPTION OF SYMBOLS 1 Nonvolatile memory | storage device, 2 Nonvolatile memory | storage device, 11 Silicon substrate, 14 Insulating film, 15 Drain region part, 16 Insulating film, 17 Insulating film, 18 Through-hole, 19 Insulating film, 20 Insulating layer, 22 Charge block film, 23 charge trap film, 24 tunnel oxide film, 29 insulating film, 30 channel, 31 polycrystalline silicon film, ML memory stack, SP semiconductor pillar, P1 plug, P2 plug, SL source line, WL word line, BL bit line

Claims (5)

A laminate in which a plurality of insulating films and electrode films are alternately laminated;
A semiconductor pillar penetrating the laminate,
A charge trap film provided between the electrode film and the semiconductor pillar;
With
The electrode film extends in one direction orthogonal to the stacking direction of the stack, and a plurality of electrode films are provided apart from each other,
The non-volatile memory device, wherein two semiconductor pillars adjacent to and intersecting the common electrode film intersect at different positions in the width direction of the electrode film.   The plurality of semiconductor pillars that intersect the common electrode film intersect alternately on one side and the other side in the width direction of the electrode film along the one direction, and with respect to the stacking direction. The plurality of semiconductor pillars arranged along the other direction orthogonal to each other and intersecting the one direction intersect each other on the same side in the width direction of the electrode film. Item 10. The nonvolatile memory device according to Item 1. A lower end portion of a first semiconductor pillar provided below the stacked body and formed at a position where the first electrode film intersects on the one side in the width direction, and a second adjacent to the first electrode film. A channel provided at a position where the lower end portion of the second semiconductor pillar formed at a position intersecting the other side in the width direction of the electrode film is in contact with each other;
A plurality of bit lines provided above the stacked body and extending in the other direction;
A plurality of source lines provided above the stacked body and extending in the other direction;
Further comprising
One upper end of the first semiconductor pillar or the second semiconductor pillar is connected to the bit line, and the other upper end of the first semiconductor pillar or the second semiconductor pillar. The nonvolatile memory device according to claim 1, wherein is connected to the source line. Forming a laminate in which a plurality of insulating films and sacrificial films are alternately laminated;
Forming a plurality of through holes extending in the stacking direction of the stacked body;
Forming a semiconductor pillar in the through hole;
Forming a trench extending in the stacking direction of the stack;
Selectively removing the sacrificial film through the trench;
Forming a charge trap film on the outer peripheral surface side of the semiconductor pillar;
Forming a plurality of electrode films between the insulating film and the insulating film in the stacking direction of the insulating films;
With
In the step of forming the electrode film, the electrode film extends in one direction orthogonal to the stacking direction of the insulating film and is formed in a plurality spaced apart from each other.
In the step of forming the through hole, the two through holes adjacent to each other in the one direction are formed so as to intersect at different positions in the width direction of the common electrode film. A method for manufacturing a storage device. A lower end portion of a first through hole formed at a position intersecting with the one side in the width direction of the first electrode film, and the other in the width direction of the second electrode film adjacent to the first electrode film. Forming a channel at a position where the lower end portion of the second through hole formed at a position where the second through holes are in contact with each other; and
Forming a plurality of bit lines provided above the semiconductor pillar and extending in the other direction;
Forming a plurality of source lines provided above the semiconductor pillar and extending in the other direction;
Further comprising
In the step of forming the bit line, an upper end of one of the semiconductor pillar formed by the first through hole and the semiconductor pillar formed by the second through hole is connected to the bit line,
In the step of forming the source line, the other upper end of the semiconductor pillar formed by the first through hole and the semiconductor pillar formed by the second through hole is connected to the source line. The method for manufacturing a nonvolatile memory device according to claim 4.

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