JP2011192363A - Power source switch circuit, nonvolatile storage device, integrated circuit device, and electronic apparatus - Google Patents

Abstract

To provide a power supply switching circuit, a nonvolatile memory device, an integrated circuit device, an electronic device, and the like that can prevent unintentional rewriting of data in a memory cell.
A power supply switching circuit selects one of a first high-potential power supply VPP and a second high-potential power supply VDD having a lower potential than the first high-potential power supply VPP, and outputs it as a supply power supply. A power supply selection circuit 100 and a control circuit 200 that controls the power supply selection circuit 100 based on a switching control signal SG are included. The control circuit 200 sets the power source selection circuit so that the power source selection circuit 100 does not output the first high potential power source VPP as a power source until both the first and second high potential power sources VPP and VDD rise. After the voltage levels of the first and second high potential power sources VPP and VDD rise, the power source selection circuit 100 determines whether the first and second high potential power sources VPP and VDD are based on the switching control signal SG. The power supply selection circuit 100 is controlled to output either one as the supply power.
[Selection] Figure 7

Description

  The present invention relates to a power supply switching circuit, a nonvolatile memory device, an integrated circuit device, an electronic device, and the like.

  In recent years, memory devices using nonvolatile memory cells such as MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type and floating gate type have been commercialized. In these nonvolatile memory devices, a power source for erasing and writing operations is used in addition to a normal power source, and a power source switching circuit for switching between the two power sources is required. In addition, there is a problem that data in the memory cell is unintentionally rewritten due to a malfunction or noise when the power is turned on.

  For example, Patent Document 1 discloses a technique for preventing an erroneous signal from being output from a memory circuit even if malfunction occurs due to noise.

  However, this technique has a problem in that rewriting of data in the memory cell due to malfunction of the power supply switching circuit cannot be prevented.

JP 2007-174492 A

  According to some embodiments of the present invention, it is possible to provide a power supply switching circuit, a nonvolatile memory device, an integrated circuit device, an electronic device, and the like that can prevent unintentional rewriting of data in a memory cell.

  One embodiment of the present invention is a power supply selection circuit that selects any one of a first high-potential power supply and a second high-potential power supply having a lower potential than the first high-potential power supply and outputs the selected power supply And a control circuit for controlling the power supply selection circuit based on a switching control signal, the control circuit until the voltage levels of the first high potential power supply and the second high potential power supply rise together. The power source selection circuit is controlled so that the power source selection circuit does not output the first high potential power source as the supply power source, and the voltage levels of the first high potential power source and the second high potential power source both rise. Later, based on the switching control signal, the power supply selection circuit controls the power supply selection circuit to output one of the first high potential power supply and the second high potential power supply as the supply power supply. Power switch Related to the road.

  According to one embodiment of the present invention, the first high potential power supply is not output until the voltage levels of the first high potential power supply and the second high potential power supply both rise. Therefore, when the first high potential power supply rises before the voltage level of the second high potential power supply rises due to an erroneous operation or static electricity, the first high potential power supply is prevented from being applied to the internal circuit. it can.

  In one embodiment of the present invention, the power supply selection circuit includes a first power supply switching transistor provided between a node of the first high potential power supply and the first node, the first node, and a power supply. And a second power supply switching transistor provided between the output node and the control circuit, wherein the control circuit may control the gates of the first power supply switching transistor and the second power supply switching transistor.

  According to this configuration, the power supply selection circuit turns on and off the first power supply switching transistor and the second power supply switching transistor by the control circuit, thereby supplying the first high-potential power supply to the first node and the first power supply switching transistor. It can be output to the power supply output node or can be non-output.

  In one embodiment of the present invention, the power supply selection circuit is provided between a node of the second high potential power supply and the first node, and a gate is connected to the node of the second high potential power supply. A third power source switching transistor, a fourth power source provided between the node of the second high potential power source and the power source output node and having a gate connected to the node of the second high potential power source The control circuit may operate using a voltage supplied from the first node as a power supply voltage.

  In this way, the power source selection circuit turns on the third power source switching transistor and the fourth power source switching transistor when the first high potential power source is not selected. A voltage based on the potential power supply can be output to the first node and the power supply output node. In addition, since the first high-potential power supply or the second high-potential power supply is output to the first node, the control circuit can operate using the voltage supplied from the first node as the power supply voltage.

  In one embodiment of the present invention, the power supply selection circuit is provided between a node of the second high potential power supply and the power supply output node, and a gate is controlled by the second high potential power supply control circuit. When the second high potential power source is selected, including the fifth power source switching transistor, the fifth power source switching transistor may be turned on.

  In this way, when the second high potential power source is selected, the fifth power source switching transistor is turned on, so that the second high potential power source is output to the power source output node at a predetermined voltage. can do.

  In one aspect of the present invention, the control circuit may be configured to switch the first power source when the voltage level of the first high potential power source rises before the voltage level of the second high potential power source rises. An initial setting voltage for turning off both the transistor and the second power source switching transistor may be set as a gate voltage of the first power source switching transistor and the second power source switching transistor.

  In this way, the first high-potential power supply is turned off before the voltage level of the second high-potential power supply rises by turning off both the first power supply switching transistor and the second power supply switching transistor. When the power supply rises, the first high potential power supply can be made non-output.

  In one embodiment of the present invention, the control circuit includes a first control circuit, the first control circuit is provided between the first node and the second node, and a gate has a low potential. A first transistor connected to a power supply node; a second transistor provided between the second node and the third node; and turned on / off by the switching control signal; and the third node And the low potential power supply node, and includes a third transistor having a gate connected to the node of the second high potential power supply, and the first control circuit includes a voltage of the second node. A first control signal for controlling the gates of the first power supply switching transistor and the second power supply switching transistor may be output based on the level.

  In this way, when the first high-potential power supply rises before the voltage level of the second high-potential power supply rises, the voltage level of the second node rises because the first transistor is on. To do. Then, as the voltage level of the second node increases, the first control signal becomes a low potential level. As a result, both the first power supply switching transistor and the second power supply switching transistor can be turned off. Further, after the voltage levels of the first high potential power source and the second high potential power source both rise, the second transistor is turned on / off by the switching control signal. As a result, the second node is set to a low potential level or a high potential level. Therefore, the first power supply switching transistor and the second power supply switching transistor can be turned on / off by the first control signal output based on the voltage level of the second node.

  In one embodiment of the present invention, the control circuit includes a second control circuit, and the second control circuit rises with a time constant that is slower than the rise of the voltage level of the first high-potential power supply. The control signal may be output.

  According to this configuration, the power source selection circuit outputs the first high potential power source after a predetermined time determined by the time constant has elapsed, that is, after the first high potential power source is applied and reaches a predetermined voltage level. can do. As a result, the first high potential power source can be stably supplied to the internal circuit.

  In one embodiment of the present invention, the control circuit includes a second control circuit, the second control circuit is provided between the first node and a fourth node, and a gate is the low level. A fourth transistor connected to a potential power supply node; and a capacitor provided between the fourth node and the low potential power supply node; and the second control circuit includes a voltage of the fourth node. A second control signal for controlling the gate of the second power supply switching transistor may be output based on the level.

  In this way, after the first high-potential power supply is applied, the fourth node becomes high after a lapse of time corresponding to the time constant determined by the current driving capability of the fourth transistor and the capacitance value of the capacitor. The potential level is set, and the second control signal is set to the high potential level. As a result, the second power supply switching transistor can be turned on after elapse of time corresponding to the time constant.

  In one embodiment of the present invention, the first high potential power source is a high potential power source for erasing and writing operations of electrically rewritable nonvolatile memory cells, and the second high potential power source is It may be a high potential power source for read operation of the nonvolatile memory cell.

  In this way, when the first high potential power supply rises before the voltage level of the second high potential power supply rises due to erroneous operation or static electricity, the first high potential power supply is applied to the nonvolatile memory cell. Can be prevented. As a result, it is possible to prevent the data in the nonvolatile memory cell from being rewritten unintentionally.

  Another aspect of the present invention relates to a nonvolatile memory device including the power supply switching circuit described above and a nonvolatile memory cell array.

  Another embodiment of the present invention relates to an integrated circuit device and an electronic device including the nonvolatile memory device described above.

An example of the structure of a non-volatile memory cell. 4A and 4B illustrate each operation of a nonvolatile memory cell. Detailed configuration example of memory cell array, word line, source line, etc. 2 shows a basic configuration example of a nonvolatile storage device. The comparative example of a power supply switching circuit. The figure explaining operation | movement of the comparative example of a power supply switching circuit. The 1st structural example of a power supply switching circuit. FIG. 8A to FIG. 8C are diagrams for explaining operations of the first to third configuration examples. The 2nd structural example of a power supply switching circuit. An example of the voltage waveform of each node of the 2nd example of composition. 3 shows a third configuration example of a power supply switching circuit. 12A and 12B illustrate configuration examples of an integrated circuit device and an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Nonvolatile Memory Device FIG. 1 shows a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type as an example of the structure of a nonvolatile memory cell in which data can be electrically written and erased. Note that the nonvolatile memory cell of the present embodiment is not limited to the structure shown in FIG.

  The memory cell shown in FIG. 1 includes a semiconductor layer 510, a source / drain region 520, a first gate insulating layer 530, a gate charge storage layer 540, a second gate insulating layer 550, a gate conductive layer 560, and an insulating layer 570. One of the source / drain regions 520 is connected to the source line SL, and the other is connected to the bit line BL. Gate conductive layer 560 is connected to word line WL.

  The gate charge storage layer 540 is formed by, for example, a silicon nitride layer (Si3N4 layer), the gate conductive layer 560 is formed by, for example, a polysilicon layer, and the first and second gate insulating layers 530 and 550 and the insulating layer 570 are formed by, for example, oxidation It is formed of a silicon layer (SiO2 layer). Thereby, a MONOS structure is realized.

  In the MONOS type memory cell, a part of the electrons traveling through the channel becomes hot electrons, and is trapped (trapped) by the gate charge storage layer 540 beyond the barrier of the first gate insulating layer 530. Data is written. In other words, the threshold voltage of the memory cell changes depending on the presence or absence of charges trapped in the gate charge storage layer 540, thereby determining 0 or 1 of the stored data. Specifically, in the state where negative charges are accumulated in the gate charge accumulation layer 540 by the write operation (for example, the state of data 0), the threshold voltage becomes high. On the other hand, in the erase operation, a part of holes (holes) generated by the band-to-band tunnel effect is accelerated by an electric field to become hot holes and injected into the gate charge storage layer 540. By electrically neutralizing the negative charge trapped by the injected holes, data is erased (for example, data 1 is entered).

  FIG. 2 is a diagram for explaining each operation (erasing, writing, reading) of the nonvolatile memory cell (MONOS type). As shown in FIG. 2, during the erase operation, the word line WL is set to a low potential power supply voltage VSS (for example, 0 V), the source line SL is set to a first high potential power supply voltage VPP, and the bit line BL is set to a floating state. Data 1 is stored by this erasing operation. During the write operation, the word line WL is set to VPP, the source line SL is set to VPP, and the bit line BL is set to VSS. Data 0 is stored by this write operation. In the read operation, the word line WL is set to the second high potential power supply voltage VDD, the source line SL is set to VSS, and the potential of the bit line BL is sensed by the sense amplifier to read data 1 or 0.

  Here, the first high-potential power supply voltage VPP is a voltage used at least for a write operation (data write), and can be used for an erase operation (data erase), for example. The first high-potential power supply voltage VPP is a voltage (for example, a voltage of 5 V or more) higher than the second high-potential power supply VDD that is a power supply voltage of a normal circuit. This is the voltage applied to the gate.

  FIG. 3 shows a detailed configuration example of the memory cell array, word line, source line, etc. in the nonvolatile memory device of this embodiment. Note that the nonvolatile memory device of the present embodiment is not limited to the configuration of FIG. 3, and various components such as omitting some of the components, replacing them with other components, and adding other components. Variations are possible.

  The power supply switching circuit of the present embodiment selects one of the first high-potential power supply VPP and the second high-potential power supply VDD based on the switching control signal SG and outputs it as a supply power supply. Specifically, at the time of erasing operation or writing operation, the switching control signal SG becomes H level (high potential level), and the power supply switching circuit outputs the first high potential power supply voltage VPP to the power supply output node VOUT. On the other hand, during the read operation, the switching control signal SG becomes L level (low potential level), and the power supply switching circuit outputs the second high potential power supply voltage VDD to the power supply output node VOUT. The switching control signal SG is generated by a memory control circuit (peripheral circuit) provided in the nonvolatile memory device.

  This supply power is supplied as power for the main word line drivers DM1 and DM2 and the inverter INV. The supplied power is supplied to the source switch circuits SS1 and SS2 via the power switch circuit SSC. The power supply is also supplied to other circuits related to the erase operation and the write operation, although not shown in FIG.

  The memory block MB1 includes a memory cell array MA1, a plurality of bit lines BL1, BL2,..., A plurality of word lines WL1, WL2,..., A plurality of source lines SL1, SL2,. Circuits SS1, SS2,. Note that the number of bit lines, word lines, and source lines and the number of source switch circuits are arbitrary. Further, the configuration of the other memory blocks is the same as that of the memory block MB1, and the description thereof is omitted here.

  The memory cell array MA1 is provided with a plurality of nonvolatile memory cells M11, M12, M21, M22. Each of these nonvolatile memory cells is provided at a location corresponding to the intersection position of each word line (each source line) and each bit line.

  Source lines SL1 and SL2 are provided corresponding to word lines WL1 and WL2. For example, the source line SL1 is provided corresponding to the word line WL1, and the source line SL2 is provided corresponding to the word line WL2.

  The main word line drivers DM1, DM2,... Are included in a later-described row decoder RDEC (FIG. 4), and drive the main word lines WL1X, WL2X,. The sub word line drivers DS1, DS2,... Are included in a word / source line driver WSDR11 (FIG. 4), which will be described later, and drive the sub word lines WS1, WS2,. The main word lines WL1X, WL2X,... Are inversion nodes of the word lines WL1, WL2,.

  The source switch circuits SS1 and SS2 are provided corresponding to the word lines WL1 and WL2 and the source lines SL1 and SL2. For example, the source switch circuit SS1 is provided corresponding to the word line WL1 and the source line SL1, and the source switch circuit SS2 is provided corresponding to the word line WL2 and the source line SL2.

  Each of the source switch circuits SS1 and SS2 has a nonvolatile memory in which the first high potential power supply voltage VPP is selected by the corresponding word line when the word line corresponding to each source switch circuit is selected. Supply to the source of the cell.

  For example, when the word line WL1 is selected and WL1 becomes H level (high potential level), the sub word line WS1 becomes H level (VPP, VDD), and the main word line WL1X which is an inversion node of WL1 becomes L level ( Low potential level, VSS). As a result, the source switch circuit SS1 (N-type and P-type transistors of the transfer gate) is turned on. At this time, since the word line WL2 is in a non-selected state and is at L level, WS2 becomes L level, WL2X becomes H level, and the source switch circuit SS2 is turned off.

  Then, the first high potential power supply voltage VPP is supplied to the source line SL1 of the nonvolatile memory cells M11 and M12 via the source switch circuit SS1. As a result, VPP is applied to the sources of the nonvolatile memory cells M11 and M12 selected by the word line WL1, and an erasing operation and a writing operation are performed.

  During the erase operation, the erase signal ER is at the H level (VPP), and the power supply node WSC of the sub word line driver DS1 is set to VSS by the inverter INV. Further, when the erasing transistor TE1 is turned on, the sub word line WS1 corresponding to the word line WL1 is set to VSS, and VSS is applied to the gates of the nonvolatile memory cells M11 and M12. At this time, the N-type transistor constituting the transfer gate of the source switch circuit SS1 is turned off. When the erase signal ER becomes H level, the power supply node WSC of the sub word line driver DS2 is also set to VSS by the inverter INV. Further, when the erasing transistor TE2 is turned on, the sub word line WS2 corresponding to the word line WL2 is set to VSS, and VSS is applied to the gates of the memory cells M21 and M22. At this time, the N-type transistor constituting the transfer gate of the source switch circuit SS2 is turned off.

  For example, when the word lines WL1 and WL2 are selected and the WL1 and WL2 become H level, the main word lines WL1X and WL2X which are inversion nodes of the WL1 and WL2 are set to VSS by the main word line drivers DM1 and DM2. As a result, the P-type transistors constituting the transfer gates of the source switch circuits SS1 and SS2 are turned on, and the source switch circuits SS1 and SS2 are turned on. Since the power supply switching circuit outputs VPP during the erasing operation, VPP is applied to the source lines SL1 and SL2 via the source switch circuits SS1 and SS2 that are turned on. As a result, VPP is applied to the sources of the selected nonvolatile memory cells M11, M12, M21, and M22, and the erase operation shown in FIG. 2 is executed. At this time, as shown in FIG. 2, the bit lines BL1 and BL2 are set in a floating state by, for example, a read & write circuit RWC1 (FIG. 4) described later.

  During the write operation, since the power supply switching circuit outputs VPP, when the word line WL1 is selected and becomes H level, the sub word line WS1 of WL1 is set to VPP by the sub word line driver DS1. On the other hand, the main word line WL1X is set to VSS by the main word line driver DM1. As a result, VPP is applied to the gates of the nonvolatile memory cells M11 and M12 selected by the word line WL1, and the source switch circuit SS1 is turned on. Therefore, VPP is applied to the source line SL1 through the source switch circuit SS1. Therefore, VPP is applied to the sources of the nonvolatile memory cells M11 and M12 selected by the word line WL1, and the write operation shown in FIG. 2 is executed. At this time, as shown in FIG. 2, the bit lines BL1 and BL2 are set to VSS by the read & write circuit RWC1. Specifically, when data is written to the memory cell M11, the bit line BL1 is set to VSS, and when data is written to the memory cell M12, the bit line BL2 is set to VSS.

  During the read operation, the power supply switching circuit outputs VDD instead of VPP. Therefore, VDD is supplied to the main word line drivers DM1, DM2 and the inverter INV instead of VPP. Thus, for example, when the word line WL1 is selected, the gates of the nonvolatile memory cells M11 and M12 are set to VDD. In the read operation, the voltage supplied to the source switch circuits SS1 and SS2 is set to VSS by the source voltage setting circuit SSC. Therefore, for example, when the word line WL1 is selected and the source switch circuit SS1 is turned on, the source line SL1 is set to VSS. In this way, the read operation shown in FIG. 3 is executed.

  FIG. 4 shows a basic configuration example of the nonvolatile memory device of the present embodiment. This nonvolatile memory device is, for example, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type or floating gate type nonvolatile memory device, and includes a power supply switching circuit, memory blocks MB1, MB2,. A buffer ADBF, a row address decoder RDEC, and a column decoder CDEC are included. Note that the storage device of the present embodiment is not limited to the configuration shown in FIG. 4, and various modifications may be made such as omitting some of the components, replacing them with other components, or adding other components. Is possible.

  The power supply switching circuit selects one of the first high-potential power supply VPP and the second high-potential power supply VDD based on the switching control signal SG, and outputs it as a supply power to the power supply output node VOUT. This power supply is supplied to the word / source line drivers WSDR11 and WSDR12.

  The memory block MB1 includes a memory cell array MA1, word / source line drivers WSDR11 and WSDR12, a read & write circuit RWC1, and an input / output buffer IO1. The memory block MB2 includes a memory cell array MA2, word / source line drivers WSDR21 and WSDR22, a read & write circuit RWC2, and an input / output buffer IO2.

  The memory cell array MA1 includes a plurality of nonvolatile memory cells that can electrically write and erase data. As this nonvolatile memory cell, for example, the memory cell having the MONOS structure shown in FIG. 1 can be used.

  The word / source line drivers WSDR11 and WSDR12 are circuits for applying voltages necessary for read, write, and erase operations to the word lines and source lines connected to each memory cell. The detailed configuration of the word source line driver is as shown in FIG. 3, for example.

  The read & write circuit RWC1 is a circuit for reading data from the memory block MB1 and writing data to the MB1, and includes a sense amplifier, a bit line write driver, and the like. For example, when data is read from the memory block MB1, the sense amplifier of the read & write circuit RWC1 senses and amplifies the potential of the bit line, thereby realizing data read. When writing data to the memory block MB1, the write driver of the read & write circuit RWC1 sets the bit line selected by, for example, the column decoder CDEC to VSS, thereby realizing the data write operation.

  The input / output buffer IO1 is a buffer for an external processing unit (CPU, control circuit, etc.) to write data or read data. For example, at the time of a write operation, the processing unit writes input data to be written in the memory block MB1 into the input / output buffer IO1 (write data register). In the read operation, data read by the read & write circuit RWC1 is read by the processing unit via the input / output buffer IO1 (read data register).

  The configuration and operation of the memory block MB2 are the same as those of the memory block MB1, and thus detailed description thereof is omitted.

  As described above, according to the nonvolatile memory device including the power supply switching circuit of the present embodiment, the circuit that requires the VPP by selecting the first high potential power supply VPP during the erase operation and the write operation ( A circuit related to an erasing operation and a writing operation). In a read operation that does not require VPP, the second high potential power supply VDD can be selected and supplied to the above circuit. In this way, since the high voltage VPP is not applied to the memory cell during the read operation, the stored data can be prevented from being rewritten.

2. Power Supply Switching Circuit As described above, in the electrically rewritable nonvolatile memory device, the first high potential power supply VPP is used during the erase and write operations of the memory cells, and the second high potential power supply VDD during the write operation. Is used. For this purpose, a power supply switching circuit is provided that selects one of VPP and VDD based on the switching control signal SG and outputs it as a power supply.

  FIG. 5 shows a comparative example of the power supply switching circuit. This comparative example includes a power supply selection circuit 100, a control circuit (for VPP) 201, and a control circuit (for VDD) 300. The power supply selection circuit 100 includes P-type first, second, and fifth power switching transistors TA1, TA2, and TA5 and N-type third and fourth power switching transistors TA3 and TA4. The output signal of the control circuit (for VPP) 201 is input to the gate input node G1 of TA1 and the gate input node G2 of TA2. The output signal of the control circuit (for VDD) 300 is input to the gate input node G5 of TA5.

  When G1 and G2 are both at the H level, TA1 and TA2 are both off, so that VPP is not output to the power supply output node VOUT. At this time, G5 becomes L level and TA5 is turned on, so that VDD is output to the power supply output node VOUT. Further, when TA3 is turned on, the potential of the node N1 is set to VDD-VTH (VTH is a threshold voltage of TA3).

  On the other hand, when both G1 and G2 are at the L level, both TA1 and TA2 are in the on state, so that VPP is output to the node N1 and the power supply output node VOUT. At this time, the node N1 serves as the drain of TA3, the power output node VOUT serves as the drain of TA4, and the node VDD serves as the sources of TA3 and TA4. Turns off. At this time, since G5 becomes H level, TA5 is in an OFF state.

  The control circuit (for VPP) 201 includes a level shifter circuit composed of four transistors TC1 to TC4 and an inverter IVA, and operates using a voltage (VDD-VTH or VPP) supplied from the node N1 as a power supply voltage. . That is, when the voltage at the node N1 is VDD, the VDD level is output as the H level, and the VSS level is output as the L level. When the voltage at the node N1 is VPP, the VPP level is set as the H level. The VSS level is output as the level. In this way, TA1 and TA2 can be reliably turned on / off.

  The control circuit (for VDD) 300 includes a level shifter circuit including four transistors TA6 to TA9 and an inverter IVB, and operates using a voltage (VDD or VPP) supplied from the power supply output node VOUT as a power supply voltage. . The control circuit (for VDD) 300 outputs an L level when the control signal SG is at an L level, and outputs an H level when the control signal SG is at an H level.

  FIG. 6 is a diagram for explaining the operation of the comparative example (FIG. 5) of the power supply switching circuit. FIG. 6 shows the voltage level of each node of the power supply switching circuit for four cases. Below, operation | movement of a circuit is demonstrated about each case.

  In Case 1, the second high-potential power supply VDD is applied to the VDD node, but no voltage is applied to the VPP node and the circuit is open. When the nonvolatile memory device performs only a read operation without rewriting data, the first high-potential power supply VPP is not necessary, and the VPP node may be open. When the switching control signal SG is at L level, that is, at the time of read operation, the gate input nodes G1 and G2 of TA1 and TA2 are both at H level, so both TA1 and TA2 are in the off state and G5 is at L level. Therefore, TA5 is turned on, and VDD is output to the power supply output node VOUT.

  In Case 2, the second high-potential power supply VDD is applied to the VDD node, the first high-potential power supply VPP is applied to the VPP node, and the switching control signal SG is at the L level, that is, during the read operation. In this case, since the gate input nodes G1 and G2 of TA1 and TA2 are both at the H level, both TA1 and TA2 are turned off, and VPP is not output to the power supply output node VOUT. On the other hand, since G5 becomes L level, TA5 is turned on and VDD is output.

  In case 3, the second high potential power supply VDD is applied to the VDD node, the first high potential power supply VPP is applied to the VPP node, and the switching control signal SG is at the H level, that is, during the erase or write operation. is there. In this case, since the gate input nodes G1 and G2 of TA1 and TA2 are both at the L level, both TA1 and TA2 are turned on, and VPP is output to the power supply output node VOUT.

  In Case 4, no voltage is applied to the VDD node, and the circuit is open, and the first high potential power supply VPP is applied to the VPP node. Case 4 is a state that does not occur in normal operation. However, for example, when the nonvolatile memory device is turned on, if the first high-potential power supply VPP rises after the second high-potential power supply VDD rises if it is normal, VPP is applied before VDD rises due to an erroneous operation or the like. It can be done. In this case, since the peripheral circuit that generates the switching control signal SG has not risen, the voltage level of SG is undefined, and therefore the voltage levels of G1 and G2 are also undefined. Therefore, in the initial state, when the voltage levels of G1 and G2 are L level (or a potential close to the L level), TA1 and TA2 are turned on, so that there is a possibility that VPP is output at least temporarily. is there.

  As described above, in the power supply switching circuit of the comparative example (FIG. 5), when VPP is applied before VDD rises due to an erroneous operation, for example, VPP is output at least temporarily, and as a result, data in the memory cell is stored. There is a risk of rewriting. Such a situation may occur due to, for example, external static electricity in addition to an erroneous operation.

  According to the power supply switching circuit of the present embodiment, VPP can be prevented from being output even if there is an erroneous operation or static electricity, and data in the memory cell can be protected.

  FIG. 7 shows a first configuration example of the power supply switching circuit of the present embodiment. The first configuration example includes a power supply selection circuit 100, a control circuit (for VPP) 200, and a control circuit (for VDD) 300. Note that the power supply switching circuit of the present embodiment is not limited to the configuration of FIG. 7, and various modifications such as omitting some of the components, replacing them with other components, and adding other components. Implementation is possible.

  The power supply selection circuit 100 selects either the first high-potential power supply VPP or the second high-potential power supply VDD having a lower potential than the first high-potential power supply VPP, and supplies the power supply output node VOUT as a supply power supply. Output.

  The control circuit (VPP control circuit, first high-potential power supply control circuit) 200 controls the power supply selection circuit 100 based on the switching control signal SG. Specifically, the control circuit (for VPP) 200 uses the first high-potential power supply VPP and the second high-potential power supply VDD as the power supply selection power supply 100 until the voltage levels of the first high-potential power supply VPP and the second high-potential power supply VDD rise. The power supply selection circuit 100 is controlled so as not to output the potential power supply VPP. In addition, after the voltage levels of the first high potential power supply VPP and the second high potential power supply VDD both rise, the power supply selection circuit 100 performs the first high potential power supply VPP and the second high potential power supply VPP based on the switching control signal SG. The power supply selection circuit 100 is controlled to output either one of the high potential power supply VDD as a supply power supply.

  The control circuit (VDD control circuit, second high-potential power supply control circuit) 300 has the same configuration as that of the above-described comparative example (FIG. 5), and is a level shifter including four transistors TA6 to TA9. The circuit includes a circuit and an inverter IVB, and operates with the voltage supplied from the power supply output node VOUT as the power supply voltage.

  The power supply selection circuit 100 has the same configuration as that of the above-described comparative example (FIG. 5), and includes first to fifth power supply switching transistors TA1 to TA5. A modification in which the fifth power supply switching transistor TA5 and the control circuit (for VDD) 300 are not provided is also possible.

  The first power supply switching transistor TA1 is a P-type transistor, and is provided between the node of the first high potential power supply VPP and the first node N1. The second power supply switching transistor TA2 is a P-type transistor and is provided between the first node N1 and the power supply output node VOUT. The control circuit (for VPP) 200 controls the gates of the first power supply switching transistor TA1 and the second power supply switching transistor TA2.

  The third power supply switching transistor TA3 is an N-type transistor and is provided between the node of the second high-potential power supply VDD and the first node N1, and the gate is a node of the second high-potential power supply VDD. Connected to. The fourth power supply switching transistor TA4 is an N-type transistor and is provided between the node of the second high potential power supply VDD and the power supply output node VOUT, and the gate is connected to the node of the second high potential power supply VDD. Connected.

  The fifth power supply switching transistor TA5 is a P-type transistor and is provided between the node of the second high potential power supply VDD and the power supply output node VOUT, and the gate thereof is output from the control circuit (for VDD) 300. Be controlled.

  The operation of the power supply selection circuit 100 is the same as that of the comparative example (FIG. 5) described above. That is, when both the gate input nodes G1 and G2 of TA1 and TA2 are at the H level, both TA1 and TA2 are in the off state, so that VPP is not output to the power supply output node VOUT. At this time, G5 becomes L level and TA5 is turned on, so that VDD is output to the power supply output node VOUT. Further, when TA3 is turned on, the potential of the node N1 is set to VDD-VTH (VTH is a threshold voltage of TA3).

  On the other hand, when both G1 and G2 are at the L level, both TA1 and TA2 are in the on state, so that VPP is output to the node N1 and the power supply output node VOUT. At this time, the node N1 serves as the drain of TA3, the power supply output node VOUT serves as the drain of TA4, and the node VDD serves as the sources of TA3 and TA4. Turns off. At this time, since G5 becomes H level, TA5 is in an OFF state.

  The control circuit (for VPP) 200 operates using the voltage supplied from the first node N1 as the power supply voltage. Specifically, VDD is supplied from N1 when both G1 and G2 are at the H level, and VPP is supplied from N1 when both G1 and G2 are at the L level.

  The control circuit (for VPP) 200 includes the first and second power supply switching transistors TA1 when the voltage level of the first high potential power supply VPP rises before the voltage level of the second high potential power supply VDD rises. The initial setting voltage for turning off both TA2 and TA2 is set as the gate voltage of TA1 and TA2. In this manner, when VPP rises before VDD rises, TA1 and TA2 can be turned off, so that VPP can be prevented from being output. The above initial setting voltage is a voltage for setting the gate-source voltage VGS for turning off TA1 and TA2, and the threshold voltage of TA1 and TA2 is set to VTH (<0) VGS> VTH.

  The control circuit (for VPP) 200 includes a first control circuit 210. The first control circuit 210 includes first to third transistors TB1 to TB3. The first transistor TB1 is a P-type transistor and is provided between the first node N1 and the second node N2, and has a gate connected to the low potential power supply node VSS. The second transistor TB2 is an N-type transistor, is provided between the second node N2 and the third node N3, and is turned on / off by a switching control signal SG. The third transistor TB3 is an N-type transistor and is provided between the third node N3 and the low potential power supply node VSS, and has a gate connected to a node of the second high potential power supply VDD.

  The first control circuit 210 outputs a first control signal SA1 for controlling the gates of the first and second power supply switching transistors TA1 and TA2 based on the voltage level of the second node N2. Inverter IV1 receives first control signal SA1 and outputs its inverted signal to gate input node G1, and inverter IV2 receives first control signal SA1 and receives its inverted signal to gate input node G2. Output. Note that IV2 may be omitted and the output of IV1 may be output to G1 and G2.

  In FIG. 7, the substrate of the P-type transistor is connected to the first node N1, and the substrate of the N-type transistor is connected to the low potential power supply node VSS.

  FIG. 8A is a diagram for explaining the operation of the first configuration example (FIG. 7). FIG. 8A shows the voltage level of each node of the power supply switching circuit for four cases. Below, operation | movement of a circuit is demonstrated about each case.

  In the first case, the second high potential power supply VDD is applied to the VDD node, but no voltage is applied to the VPP node and the circuit is open. When the nonvolatile memory device performs only a read operation without rewriting data, the first high-potential power supply VPP is not necessary, and the VPP node may be open. When the switching control signal SG is at L level, that is, at the time of read operation, TB2 is in the off state and TB1 is in the on state, so the second node N2 is at the H level. Accordingly, since the first control signal SA1 is at L level and G1 and G2 are at H level (initial setting voltage), TA1 and TA2 are both turned off, while G5 is at L level. The power supply output node VOUT is output with VDD.

  In the second case, the second high-potential power supply VDD is applied to the VDD node, the first high-potential power supply VPP is applied to the VPP node, and the switching control signal SG is at the L level, that is, during the read operation. is there. In this case, since TB2 is in an off state and TB1 is in an on state, the second node N2 becomes H level. Therefore, since the first control signal SA1 becomes L level and G1 and G2 become H level (initial setting voltage), both TA1 and TA2 are turned off, and VPP is not output to the power supply output node VOUT. On the other hand, since G5 becomes L level, TA5 is turned on and VDD is output.

  In the third case, the second high potential power supply VDD is applied to the VDD node, the first high potential power supply VPP is applied to the VPP node, and the switching control signal SG is at the H level, that is, the erase or write operation. It's time. In this case, TB1, TB2, and TB3 are all turned on, but N2 can be set to L level by setting the current driving capability of TB1 smaller than the current driving capability of TB2 and TB3. By doing this, the first control signal SA1 becomes H level, and G1 and G2 become L level. Therefore, both TA1 and TA2 are turned on, and VPP is output to the power supply output node VOUT.

  In the fourth case, no voltage is applied to the VDD node and the circuit is open, and the first high-potential power supply VPP is applied to the VPP node. As described above, the fourth case is a state that does not occur in normal operation. In this case, since the peripheral circuit for generating the switching control signal SG has not risen, the voltage level of SG is indefinite, but since TB1 is in the ON state, N2 becomes H level. Accordingly, since the first control signal SA1 becomes L level and both G1 and G2 become H level (initial setting voltage), both TA1 and TA2 are turned off, and the power output node VOUT is not output.

  As described above, according to the power supply switching circuit of the present embodiment, it is possible to prevent VPP from being output even when VPP is applied before VDD rises due to an erroneous operation or static electricity. As a result, it is possible to prevent the data in the memory cell from being rewritten unintentionally.

  FIG. 9 shows a second configuration example of the power supply switching circuit of the present embodiment. The second configuration example includes the first control circuit 210 and the second control circuit 220 described above. Note that the power supply switching circuit of the present embodiment is not limited to the configuration of FIG. 9, and various modifications such as omitting some of the components, replacing them with other components, and adding other components. Implementation is possible.

  The second control circuit 220 outputs a second control signal SA2 that rises with a time constant later than the rise of the voltage level of the first high potential power supply VPP. In this way, VPP can be output after the time corresponding to the time constant has elapsed, that is, after VPP is applied and reaches a predetermined voltage level. As a result, since VPP can be supplied stably, erasing and writing operations can be reliably performed.

  The second control circuit 220 includes a fourth transistor TB4 and a capacitor C1. The fourth transistor TB4 is a P-type transistor and is provided between the first node N1 and the fourth node N4, and has a gate connected to the low potential power supply node VSS. The capacitor C1 is provided between the fourth node N4 and the low potential power supply node VSS.

  The second control circuit 220 outputs a second control signal SA2 for controlling the gate of the second power supply switching transistor TA2 based on the voltage level of the fourth node N4. Specifically, the buffer circuit BF1 receives the voltage level of N4 and outputs the second control signal SA2 to the NAND gate ND1. The NAND gate ND1 receives the first and second control signals SA1 and SA2 and outputs a NAND output to the gate input node G2 of TA2.

  In FIG. 9, the substrate of the P-type transistor is connected to the first node N1, and the substrate of the N-type transistor is connected to the low potential power supply node VSS.

  FIG. 8B is a diagram for explaining the operation of the second configuration example (FIG. 9). Similarly to FIG. 8A, the voltage levels of the respective nodes of the power supply switching circuit are shown for the four cases. Since the operation of the first control circuit 210 is the same as that of the first configuration example already described, detailed description thereof is omitted here.

  In the first case, since N1 is at the H level and TB4 is in the ON state, the capacitor C1 is gradually charged, and the voltage level of N4 gradually increases. When the logical threshold value of the buffer circuit BF1 is exceeded, the second control signal SA2 changes from L level to H level. The time (time constant) from when VDD rises until the level of SA2 changes is determined by the current drive capability (ON resistance value) of TB4 and the capacitance value (capacitance value) of capacitor C1. On the other hand, since the first control signal SA1 holds the L level, both G1 and G2 are at the H level (initial setting voltage). On the other hand, since G5 becomes L level, TA5 is turned on, and therefore VDD is output to the power supply output node VOUT.

  In the second case, as in the first case, SA2 changes from the L level to the H level after a lapse of a predetermined time. However, since SA1 holds the L level, both G1 and G2 eventually become the H level (initial value). Set voltage). On the other hand, since G5 becomes L level, TA5 is turned on, and VDD is output to the power supply output node VOUT.

  In the third case, as described above, SA2 changes from the L level to the H level after a lapse of a predetermined time. Since SA1 is at the H level, G1 becomes the L level, and G2 changes from the H level to the L level after a lapse of a predetermined time. Therefore, VPP is output to the power supply output node VOUT after a predetermined time has elapsed.

  In the fourth case, as described above, SA2 changes from L level to H level after a lapse of a predetermined time, but since SA1 holds L level, both G1 and G2 are eventually H level (initial setting voltage). Thus, the power supply output node VOUT becomes non-output.

  FIG. 10 shows an example of the voltage waveform at each node in the second configuration example (FIG. 9). The waveform in FIG. 10 is a waveform during a period in which VPP rises in the fourth case. The VPP node rises from the VSS level to the VPP level (from A1 to A2 in FIG. 10). N1 rises following the VPP node (from A1 to A3 in FIG. 10). SA1 and SA2 also follow N1 and start to rise (from A1 to A4 in FIG. 10), but when N1 reaches the power supply voltage at which inverter IV3 and buffer circuit BF1 can operate (A5 in FIG. 10), it goes to L level. It goes down (A6 in FIG. 10). G1 and G2 initially follow N1 and rise (from A1 to A5 in FIG. 10). When the inverter IV1 and NAND gate ND1 become operable (A5 in FIG. 10), the inputs SA1 and SA2 become L level. Therefore, the outputs G1 and G2 become H level (initial setting voltage) and increase with N1 (from A5 to A3 in FIG. 10). Since G1 and G2 are at the H level, VOUT maintains the L level even after the VPP node rises. SA2 changes to the H level after elapse of a predetermined time (A7 in FIG. 10). However, since SA1 holds the L level, G2 does not change and therefore VOUT does not change.

  As described above, according to the second configuration example of the power supply switching circuit of this embodiment, VPP is output even when VPP is applied before VDD rises due to erroneous operation or static electricity. Can be prevented. Further, the VPP can be output after a predetermined time has elapsed since the VPP started up. As a result, since VPP can be supplied stably, erasing and writing operations can be reliably performed.

  FIG. 11 shows a third configuration example of the power supply switching circuit of the present embodiment. The third configuration example includes the first and second control circuits 210 and 220 described above, and further the third control circuit 230. Note that the power supply switching circuit of the present embodiment is not limited to the configuration of FIG. 11, and various modifications such as omitting some of the components, replacing them with other components, and adding other components. Implementation is possible.

  The third control circuit 230 includes a latch circuit composed of two inverters IV4 and IV5, three N-type transistors TB5, TB6 and TB7, and two capacitors C2 and C3. The gate of TB5 is controlled by the second control signal SA2, the gate of TB6 is controlled by the first control signal SA1, and the gate of TB7 is controlled by the inverted signal XSG of the switching control signal SG. The third control circuit 230 outputs a third control signal SA3 for controlling the gate of the second power supply switching transistor TA2 based on the output of the latch circuit. Specifically, SA3 is input to the 3-input NAND gate ND2 together with SA1 and SA2, and ND2 controls the gate of TA2 based on SA1, SA2, and SA3.

  In FIG. 11, the substrate of the P-type transistor is connected to the first node N1, and the substrate of the N-type transistor is connected to the low potential power supply node VSS.

  FIG. 8C is a diagram for explaining the operation of the third configuration example (FIG. 11). Similarly to FIGS. 8A and 8B, the voltage levels of the respective nodes of the power supply switching circuit are shown for the four cases. Since the operations of the first and second control circuits 210 and 220 are the same as those of the first and second configuration examples already described, detailed description thereof is omitted here.

  In the first case, since SG is at L level, that is, XSG is at H level, TB7 is turned on. Since SA1 and SA2 are both at the L level, TB5 and TB6 are both off. Since the fifth node N5 is connected to N1 via the capacitor C2, it becomes H level. In this way, SA3 which is the output of the latch circuit becomes L level. As described above, SA2 changes from L level to H level after elapse of a predetermined time, but since SA1 holds L level, the voltage level of N5 does not change, and therefore SA3 does not change and holds L level. . As a result, both G1 and G2 are at the H level (initial setting voltage), while G5 is at the L level, so TA5 is turned on and VDD is output to the power supply output node VOUT.

  In the second case, as in the first case, since SA3 maintains the L level, G1 and G2 are both at the H level (initial setting voltage), while G5 is at the L level, so TA5 is on. In this state, VDD is output to the power supply output node VOUT.

  In the third case, since SG is at the H level, that is, XSG is at the L level, TB7 is turned off. On the other hand, since SA1 is at the H level, TB6 is turned on, and after a predetermined time has elapsed, SA2 is at the H level, so that TB5 is also turned on. In this way, the voltage level of N5 is lowered to L level, so that the latch circuit is inverted and SA3 becomes H level. After all, since SA1, SA2, and SA3 all become H level, G1 and G2 both become L level, and VPP is output to the power supply output node VOUT.

  In the fourth case, the voltage level of SG is indefinite, and the inverted signal XSG is also indefinite. However, as described above, since SA1 is at L level, TB6 is turned off and N5 is at H level. Therefore, since the output of the latch circuit, that is, SA3 becomes L level, both G1 and G2 eventually become H level (initial setting voltage), and the power supply output node VOUT becomes non-output.

  According to the third control circuit 230, it is possible to prevent a malfunction immediately after the rise of VPP in the fourth case or the like. As shown in FIG. 10, there is a period in which the voltage levels of SA1 and SA2 temporarily rise immediately after the rise of VPP (from A1 to A4 in FIG. 10). For this reason, there is a possibility that the voltage level of G2 changes due to noise from the outside, transistor characteristic variations, etc., and VPP is temporarily output. In the third control circuit 230, in a state immediately after VPP is applied, the potential of the output node of the latch circuit (the node from which SA3 is output) is at the VSS level, and the potential of the fifth node N5 on the opposite side. Rises following N1. Accordingly, the state of the latch circuit is determined so as to output the L level. Thus, by determining the state of the latch circuit, SA3 can be held at the L level constantly. As a result, the operation of the power supply switching circuit can be made more reliable.

  As described above, according to the power supply switching circuit of the present embodiment, one of the first high potential power supply VPP and the second high potential power supply VDD used in the nonvolatile memory device is selected as a supply power supply. Can be output. Furthermore, even when VPP is applied before VDD rises due to erroneous operation or static electricity, it is possible to prevent VPP from being output, thus preventing memory cell data from being rewritten unintentionally. it can.

3. Integrated Circuit Device and Electronic Device FIGS. 12A and 12B show a configuration example of an integrated circuit device and an electronic device including the nonvolatile memory device of this embodiment. Note that the integrated circuit device and the electronic apparatus of this embodiment are not limited to the configurations in FIGS. 12A and 12B, and some of the components are omitted or other components are added. Various modifications of the above are possible.

  The electronic device in FIG. 12A includes an integrated circuit device 600, a sensor 700, and an antenna 710. The integrated circuit device 600 (such as a microcomputer) includes a processing unit 610, a storage unit 620, a nonvolatile storage device 630, a detection circuit 640, and a wireless circuit 650.

  The sensor 700 is, for example, a smoke sensor, an optical sensor, a human sensor, a pressure sensor, a biological sensor, a gyro sensor, or the like.

  The detection circuit of the integrated circuit device 600 performs various detection processes (physical quantity detection processes) based on sensor signals from the sensor 700 (physical quantity transducer). For example, processing for detecting a desired signal from the sensor signal is performed. The processing unit 610 of the integrated circuit device 600 performs various arithmetic processes and overall control of the integrated circuit device 600. The processing unit 610 is realized by a processor such as a CPU or an ASIC control circuit. The storage unit 620 stores various data and is realized by a RAM or the like. The nonvolatile storage device 630 is a storage device according to the present embodiment, and is a storage device that can electrically write data. The wireless circuit 650 performs wireless transmission processing of a signal to the antenna 710 and wireless reception processing of a signal from the antenna 710.

  The electronic apparatus in FIG. 12B includes an integrated circuit device 600, an external device 720, and an electro-optical panel 730. The integrated circuit device 600 includes a processing unit 610, a storage unit 620, a nonvolatile storage device 630, an external I / F unit 660, and a driver 670.

  The external device 720 is various devices provided in the electronic apparatus, and is, for example, an operation unit. The electro-optical panel 730 is, for example, a liquid crystal panel, an organic EL (Electro Luminescence) panel, an inorganic EL panel, or an electrophoretic display.

  An external I / F (interface) unit 660 of the integrated circuit device 600 performs control for various interfaces such as SPI and USB. A driver 670 controls the electro-optical panel 730 to display an image.

  In addition, as an electronic device of this embodiment, various apparatuses, such as a portable information terminal, a mobile telephone, PDA, a portable audio device, a clock, a remote control, various household appliances, can be assumed.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. In addition, the configurations and operations of the storage device, the integrated circuit device, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

VPP first high potential power supply, VDD second high potential power supply, VSS low potential power supply,
VOUT power supply output node, SG switching control signals SA1 to SA3 first to third control signals,
MB1, MB2 memory block, MA1, MA2 memory cell array,
M11 to M22 nonvolatile memory cells, WL1, WL2 word lines,
SL1, SL2 source lines, BL1, BL2 bit lines,
SS1, SS2 source switch circuit, TE1, TE2 erasing transistor,
WL1X, WL2X main word line, WS1, WS2 sub word line DM1, DM2 main word line driver,
DS1, DS2 sub word line driver,
WSDR11-WSDR22 word source line driver,
RWC1, RWC2 read & write circuit, IO1, IO2 input / output buffer,
ADBF address buffer, RDEC row address decoder,
CDEC column decoder,
100 power supply selection circuit, 200 control circuit (for VPP), 201 control circuit (comparative example),
210 first control circuit, 220 second control circuit, 230 third control circuit,
300 control circuit (for VDD),
510 semiconductor layer, 520 source / drain region, 530 first gate insulating layer,
540 gate charge storage layer, 550 second gate insulating layer, 560 gate conductive layer,
570 insulating layer;
600 integrated circuit device, 610 processing unit, 620 storage unit, 630 nonvolatile storage device,
640 detection circuit, 650 wireless circuit, 660 external I / F unit, 670 driver,
700 sensor, 710 antenna, 720 external device, 730 electro-optic panel

Claims (11)

A power supply selection circuit that selects one of the first high-potential power supply and the second high-potential power supply having a lower potential than the first high-potential power supply, and outputs the selected power supply power supply;
A control circuit for controlling the power supply selection circuit based on a switching control signal,
The control circuit includes:
Until the voltage levels of the first high potential power supply and the second high potential power supply rise together, the power supply selection circuit is configured so that the power supply selection circuit does not output the first high potential power supply as the supply power supply. Control
After the voltage levels of the first high-potential power supply and the second high-potential power supply rise together, the power supply selection circuit performs the first high-potential power supply and the second high-potential power supply based on the switching control signal. A power supply switching circuit that controls the power supply selection circuit to output any one of potential power supplies as the supply power supply. In claim 1,
The power supply selection circuit includes:
A first power supply switching transistor provided between a node of the first high potential power supply and the first node;
A second power source switching transistor provided between the first node and the power source output node;
The power supply switching circuit, wherein the control circuit controls gates of the first power supply switching transistor and the second power supply switching transistor. In claim 2,
The power supply selection circuit includes:
A third power supply switching transistor provided between the node of the second high potential power supply and the first node, and having a gate connected to the node of the second high potential power supply;
A fourth power supply switching transistor provided between the node of the second high potential power supply and the power supply output node and having a gate connected to the node of the second high potential power supply;
The power supply switching circuit, wherein the control circuit operates using a voltage supplied from the first node as a power supply voltage. In claim 2 or 3,
The control circuit includes:
When the voltage level of the first high potential power supply rises before the voltage level of the second high potential power supply rises, both the first power supply switching transistor and the second power supply switching transistor are turned off. An initial setting voltage for setting a state is set as a gate voltage of the first power source switching transistor and the second power source switching transistor. In any of claims 2 to 4,
The control circuit includes a first control circuit,
The first control circuit includes:
A first transistor provided between the first node and the second node and having a gate connected to a low potential power supply node;
A second transistor provided between the second node and the third node and turned on / off by the switching control signal;
A third transistor provided between the third node and the low potential power supply node and having a gate connected to the node of the second high potential power supply;
The first control circuit includes:
A power supply that outputs a first control signal for controlling the gates of the first power supply switching transistor and the second power supply switching transistor based on the voltage level of the second node. Switching circuit. In claim 5,
The control circuit includes a second control circuit,
The power supply switching circuit, wherein the second control circuit outputs a second control signal that rises with a time constant slower than the rise of the voltage level of the first high potential power supply. In claim 5,
The control circuit includes a second control circuit,
The second control circuit includes:
A fourth transistor provided between the first node and the fourth node and having a gate connected to the low potential power supply node;
A capacitor provided between the fourth node and the low potential power supply node;
The second control circuit includes:
A power supply switching circuit for outputting a second control signal for controlling a gate of the second power supply switching transistor based on a voltage level of the fourth node. In any one of Claims 1 thru | or 7,
The first high potential power source is a high potential power source for erasing and writing operations of electrically rewritable nonvolatile memory cells,
The power supply switching circuit, wherein the second high potential power source is a high potential power source for a read operation of the nonvolatile memory cell. A power supply switching circuit according to any one of claims 1 to 8,
A non-volatile memory device comprising: a non-volatile memory cell array.   An integrated circuit device comprising the nonvolatile memory device according to claim 9.   An electronic apparatus comprising the integrated circuit device according to claim 10.

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