JP2011182149A - Semiconductor integrated circuit, and information processing device with semiconductor integrated circuit - Google Patents

Abstract

To provide a semiconductor integrated circuit capable of improving efficiency of ADC performance evaluation without excessively increasing the scale of the semiconductor integrated circuit and an information processing apparatus including the semiconductor integrated circuit.
A semiconductor integrated circuit having an analog / digital conversion circuit for converting an analog signal into a digital signal, and performing an evaluation process of the analog / digital conversion circuit using an output signal of the analog / digital conversion circuit The test circuit is a semiconductor integrated circuit including spectral power calculation means for calculating a spectral power value of the output signal of the analog / digital conversion circuit.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that evaluates the performance of an analog / digital conversion circuit, and an information processing apparatus including the semiconductor integrated circuit.

  In recent years, in offices and homes, products using various wireless communication technologies, for example, wireless LAN communication conforming to the IEEE 802.11 standard, wireless LAN communication conforming to the wireless USB standard, and the like are used. Such a product incorporates a semiconductor integrated circuit (LSI) compatible with wireless communication. An LSI for wireless communication uses an internal or external RF circuit to down-convert the radio frequency band to the baseband frequency band, and then converts the analog signal that is the baseband signal into an analog-to-digital converter (ADC) that performs high-speed sampling. The digital signal is converted into a digital signal and demodulated by a digital modulation circuit. For this reason, the digital modulation circuit and ADC for baseband processing are usually built in the same LSI.

  The ADC used for the baseband processing has a wider signal band with the recent increase in communication speed, and it is necessary to increase the sampling frequency processing of the ADC. For example, IEEE802.11a requires a sampling frequency and frequency resolution of about 40 MHz / 9 bits, and UWB (ultra-wideband radio) using multiband orthogonal frequency division multiplexing technology (Multiband OFDM). In communication, a processing capability of about 528 MHz / 5 bits is required. In an LSI incorporating a high-speed ADC that processes such a broadband signal, how to improve the performance evaluation of the ADC exists as a manufacturing problem.

  Conventionally, when performing ADC performance evaluation, an analog circuit and a digital circuit are separated, and only the analog circuit or the digital circuit is directly controlled and observed from an external input / output terminal of the LSI. However, such an evaluation method requires a dedicated pin for controlling from the outside or a dedicated evaluation device, which is inefficient because the analog circuit test and the digital circuit test must be individually evaluated.

  Also, in recent high-speed ADCs, the generated digital data signals are output in parallel to the outside, so the evaluation device adjusts the timing of the output digital signals in consideration of the bus length over which the digital signals are conveyed. The function to do was needed.

  Furthermore, with the recent integration and miniaturization of LSIs, LSI I / O voltages have also been reduced, and high-speed ADC digital signals are high-frequency signal transmissions. It is necessary to use a signal line with high noise resistance such as voltage differential signaling. When using such a signal line, it is necessary to provide an I / O terminal dedicated to LVDS corresponding to twice the number of bits of ADC. was there.

  Furthermore, a high-speed ADC such as UWB has a configuration in which a plurality of samples can be processed in parallel by suppressing the operation clock of the digital circuit. For example, 528 MHz is integrated into a bus output for four samples, and the digital circuit Are operated at 134 MHz. For this reason, when externally outputting ADC digital signals, if I / Q 2-channel output is performed with LVDS, 80 (= 5 × 4 × 2 × 2) I / O terminals are required for 5-bit data. It becomes. Further, even when I / Q evaluation is performed individually, 40 I / O terminals are required.

  As described above, with the increase in the ADC evaluation terminals, it becomes more difficult to adjust the timing of the external evaluation apparatus, and the cost of the LSI package increases with the increase in the evaluation terminals.

  In order to solve these problems, Japanese Patent Application Laid-Open No. 2001-358586 (Patent Document 1) discloses a technique for temporarily fetching data into a built-in RAM and analyzing the fetched data offline. In Japanese Patent Laid-Open No. 2004-48383 (Patent Document 2), after calculating the SNR performance using a built-in Fast Fourier Transform (FFT) circuit, only the measurement result is obtained via the I / F. Disclosure technology is disclosed.

  However, in the technique disclosed in Patent Document 1, since the digital data itself converted by the ADC is stored in the RAM, it is necessary to provide a dedicated I / F and output the data to an external evaluation device. When the communication speed of / F cannot be sufficiently increased, it takes time to fetch the data of the evaluation device, and the evaluation time of the ADC increases. Further, in a normal evaluation test, evaluation is performed by averaging a plurality of data in consideration of the influence of noise or the like, so that the evaluation time further increases and the evaluation cost increases.

  On the other hand, in the technique disclosed in Patent Document 2, the SNR performance is calculated using an FFT circuit in the baseband circuit. Usually, the calculation accuracy of the FFT circuit in the baseband circuit is determined by the secondary modulation of the OFDM system, but based on the calculation accuracy of the FFT circuit suitable for the demodulation process, that is, the SNR required for the secondary modulation. The calculation accuracy with which the quantization noise amount can be calculated is low, and the number of effective bits of the ADC cannot be calculated. In order to calculate the number of effective bits of the ADC, it is necessary to mount an FFT circuit with high calculation accuracy. However, mounting a high-precision FFT circuit increases the circuit scale. For this reason, the technique disclosed in Patent Document 2 cannot calculate the effective number of bits of the ADC using the FFT in the baseband circuit without increasing the circuit scale.

  The present invention solves the above-described problems, and provides a semiconductor integrated circuit capable of improving the efficiency of ADC performance evaluation without excessively increasing the scale of the semiconductor integrated circuit and an information processing apparatus including the semiconductor integrated circuit. The purpose is to provide.

  That is, according to the present invention, a semiconductor integrated circuit having an analog-digital conversion circuit that converts an analog signal into a digital signal, and using the output signal of the analog-digital conversion circuit, the evaluation process of the analog-digital conversion circuit The test circuit provides a semiconductor integrated circuit that calculates the spectral power value of the output signal of the analog / digital conversion circuit.

  Moreover, the spectrum power calculation means of the present invention can calculate the spectrum power value of the output signal corresponding to each frequency Bin number in accordance with the test request signal received by the test circuit. The frequency bin number corresponds to the DFT bin number.

  Furthermore, the test circuit of the present invention calculates the effective bit number for calculating the effective bit number of the analog-digital conversion circuit using the spectral power value of the output signal corresponding to each frequency Bin number calculated by the spectral power calculation means. Means. As a result, the effective number of bits can be acquired without using an external evaluation device, and the performance evaluation of the ADC can be made more efficient.

  Furthermore, the semiconductor integrated circuit of the present invention comprises THD calculation means for calculating the THD of the analog / digital conversion circuit using the spectrum power value calculated by the spectrum power calculation means. The performance evaluation of the ADC can be made more efficient.

  Furthermore, the spectral power calculation means of the present invention may calculate the spectral power value of the output signal corresponding to each frequency Bin number specified by the test request signal received by the test circuit among the frequency components of the output signal. The spectrum power value of a specific frequency can be acquired individually.

  Furthermore, the semiconductor integrated circuit of the present invention includes digital processing means for processing the output signal of the analog / digital conversion circuit, and the digital processing means is configured as a circuit separate from the test circuit. Thereby, the spectral power value of the output signal of the analog / digital conversion circuit can be calculated without using the FFT circuit or DFT circuit inside the digital processing means, and without increasing the circuit scale of the digital processing means, The performance evaluation of the ADC can be made efficient while suppressing an increase in the scale of the entire semiconductor integrated circuit.

  Furthermore, according to the present invention, an information processing apparatus including the semiconductor integrated circuit can be provided.

1 is a diagram showing a semiconductor integrated circuit 100 according to an embodiment. 1 is a functional block diagram of a semiconductor integrated circuit 110 according to an embodiment. The figure which shows the circuit structure of the partial DFT circuit of this embodiment. It is a frequency characteristic figure of the partial DFT circuit of this embodiment, and is a figure showing the relation between a spectrum power value and a frequency Bin number. The figure which showed the radio | wireless communications system 500 containing the information processing apparatus 502 incorporating the semiconductor integrated circuit 100 of this embodiment.

  Hereinafter, although this invention is demonstrated with embodiment, this invention is not limited to embodiment mentioned later.

  FIG. 1 shows a semiconductor integrated circuit 100 of this embodiment. The semiconductor integrated circuit 100 includes a digital processing block 102 that processes a digital signal and an analog processing block 104 that processes an analog signal. The digital processing block 102 includes an analog / digital conversion circuit (hereinafter referred to as ADC) 112, an ADC test circuit 114, a baseband processing unit 116, and a digital / analog conversion circuit (hereinafter referred to as DAC). And a semiconductor integrated circuit 110 including the memory 118.

  The ADC 112 is a functional unit that converts an analog signal received from the analog processing block 104 into a digital signal. The ADC 112 of this embodiment includes two channels, and converts in-phase components (I component) and quadrature components (Q component) of received data including distorted waves and sine waves having various frequencies into digital signals, respectively. .

  The ADC test circuit 114 is a circuit that executes an evaluation process for evaluating the performance of the ADC 112 using the output signal of the ADC 112. The ADC test circuit 114 is a band-limited spectrum power of the output signal and the effective bit number (characteristic value of ADC) ENOB: Effective Number Of Bits), Total Harmonic Distortion (THD), etc. are calculated and provided as test result data. The ADC test circuit 114 will be described later in detail with reference to FIG.

  The baseband processing unit 116 is digital processing means for performing baseband processing such as modulation / demodulation processing of communication data, and is configured as a circuit including a modulation / demodulation circuit. The baseband processing unit 116 performs demodulation processing on the reception data A / D converted by the ADC 112 and also performs modulation processing on data to be transmitted to the outside, so that transmission data configured by an I component and a Q component is performed. Is generated.

  The DAC 118 is a functional unit that converts digital transmission data modulated by the baseband processing unit 116 into an analog signal. Similar to the ADC 112, the DAC 118 according to the present embodiment includes two channels, and converts each component of transmission data into an analog signal.

  The semiconductor integrated circuit 110 can further include a semiconductor memory (not shown) such as a RAM for storing test result data calculated by the ADC test circuit 114. In the present embodiment, the semiconductor memory can be provided in the ADC test circuit 114, and in other embodiments, the semiconductor memory can be provided as a circuit separate from the ADC test circuit 114.

  The analog processing block 104 performs filtering, attenuation, separation, and the like on analog data received from the outside by radio and passes it to the digital processing block 102. Also, the analog processing block 104 performs integration, oscillation, amplification, etc. of transmission data received from the digital processing block 102. The wireless communication circuit 120 is a semiconductor integrated circuit that transmits to the outside wirelessly. The wireless communication circuit 120 includes antennas 122a and 122b, a band pass filter (BPF) 124, and a low noise amplifier (LNA) 126. The antennas 122a and 122b are devices that mutually convert electromagnetic waves and high frequency energy and perform wireless communication using the electromagnetic waves. The BPFs 124a and 124b are filter circuits that attenuate high frequency energy converted by the antennas 122a and 122b or high frequency energy converted by the antennas 122a and 122b to extract frequency data in a necessary frequency band. The LNA 126 is a low noise amplification circuit, and amplifies the frequency data attenuated by the BPF 124a for subsequent processing.

  The analog processing block 104 includes voltage controlled oscillators (VCOs) 128a and 128b, low pass filters (LPFs) 130a, 130b, 130c, and 130d, and variable gain amplifiers (VGA). : Variable Gain Amplifier) 132a and 132b and a power amplifier (PA) 134.

  The VCO / Mixers 128a and 128b are circuits that oscillate by separating or integrating frequency data. The VCO / Mixer 128a oscillates by separating the frequency data attenuated by the BPF 124a into an I component and a Q component, while the VCO / Mixer 128b oscillates by integrating the I component and the Q component of the frequency data. The LPFs 130a, 130b, 130c, and 130d are filter circuits that extract low frequency components of the electric signal, and extract low frequency components from the frequency data received from the VCO / Mixer 128 and the frequency data received from the digital processing block 102. The VGAs 132a and 132b are circuits that adjust the gain according to the strength of the input signal, and adjust the gain of the frequency data received from the LPFs 130a and 130b to a size suitable for subsequent digital processing. The PA 134 is a circuit that amplifies the input signal, and amplifies the frequency data received from the VCO / Mixer 128b.

  FIG. 2 is a diagram showing functional blocks of the semiconductor integrated circuit 110 of the present embodiment. Hereinafter, the ADC test circuit 114 for evaluating the ADC 112 will be described with reference to FIG.

  The ADC test circuit 114 includes a spectrum power calculation unit 212, an ENOB calculation unit 214 that calculates the number of effective bits, and a THD calculation unit 216 that calculates THD. The spectrum power calculation unit 212 is a means for calculating the spectrum power of the output signals 210a and 210b of the ADC 112, and is realized by a partial discrete Fourier transform (DFT) circuit in this embodiment. The partial DFT circuit represents the output signals 210a and 210b as finite-length sample value sequences, performs discrete Fourier transform at discrete finite times, converts them to the frequency domain, and calculates the spectral power corresponding to an arbitrary frequency Bin number. To do. In this embodiment, a Goertzel Algorithm circuit is used as the partial DFT circuit, and the spectrum power corresponding to an arbitrary frequency Bin number of the partial DFT circuit is calculated. The frequency bin number is a number that can specify a frequency band obtained by dividing the frequency band determined by the sampling frequency by the number of DFT points.

  In the present embodiment, the ADC test circuit 114 calculates the spectral power using the internal partial DFT circuit, so that the baseband is higher than the technique of calculating the number of effective bits using the FFT circuit in the baseband processing unit. It is possible to improve the performance evaluation of the ADC while suppressing the increase in the scale of the entire semiconductor integrated circuit without increasing the scale of the processing circuit. The partial DFT circuit used in the present embodiment will be described in more detail with reference to FIG. 3 together with the circuit configuration and the transfer function to be realized.

  The ENOB calculation unit 214 is a means for calculating the ENOB of the ADC 112 and can be implemented as a circuit in the ADC test circuit 114. In the present embodiment, the ENOB calculation unit 214 identifies the frequency Bin number that maximizes the spectrum power value among the spectrum power values calculated by the spectrum power calculation unit 212. Then, the ENOB calculation unit 214 specifies the frequency Bin numbers before and after the frequency Bin number, and specifies the spectrum power value of the frequency Bin number. Further, the ENOB calculation unit 214 calculates a total value (hereinafter referred to as SP) of the maximum spectral power value and the spectral power values of the frequency Bin numbers before and after the maximum spectral power value, and other than these spectral power values. A noise power value (hereinafter referred to as NP), which is the sum of the spectrum power values, is calculated. Then, the ENOB calculation unit 214 calculates SINAD (SIgnal to Noise And Distortion) (= SP / NP) using SP and NP, and calculates ENOB (= (SINAD-1.76) /6.02). To do.

  In this embodiment, it is possible to evaluate the performance of the ADC using an input signal having an arbitrary frequency, but in other embodiments, the performance of the ADC is evaluated using an input signal having a known frequency. You can also. In this case, since the ENOB calculation unit 214 can use the frequency Bin number corresponding to the frequency of the input signal as the frequency Bin number that maximizes the spectrum power value, the spectrum power calculation unit 212 needs to be mounted. Therefore, the circuit scale can be reduced accordingly.

  The THD calculation unit 216 is a means for calculating the THD of the ADC 112 and can be implemented as a circuit in the ADC test circuit 114. The THD calculation unit 216 sums the SP calculated by the ENOB calculation unit 214 and the frequency component corresponding to an integral multiple of the frequency component having the maximum spectral power value, for example, the spectral power value of the frequency component of 2 to 9 times. THD (= TP / SP) is calculated using the value (hereinafter referred to as TP).

  Further, the ADC test circuit 114 includes two channels capable of receiving the output signals 210a and 210b A / D converted by the ADC 112 for each of the I component and the Q component, and a test request signal 220 input from the outside of the ADC test circuit 114. Including a receivable channel.

  The test request signal 220 of this embodiment includes a condition signal that can specify a spectrum power calculation mode and / or a frequency component for which spectrum power is to be calculated, and a trigger signal that starts the evaluation process of the ADC 112. The condition signal includes a calculation mode designation parameter for designating a spectrum power calculation mode and a frequency component designation parameter for designating a frequency component of the output signals 210a and 210b for which the spectrum power is to be calculated. In the present embodiment, the evaluation processing calculation mode executed by the ADC test circuit 114 corresponds to a mode for sequentially calculating the spectrum power of the output signals 210a and 210b corresponding to each frequency bin number and an arbitrary frequency bin number. There is a mode for calculating the spectral power of the output signals 210a and 210b, which can be specified by a calculation mode specifying parameter included in the condition signal. In this embodiment, the DFT point and the frequency Bin number of the DFT can be used as the frequency component designation parameter.

  In the present embodiment, when the mode for sequentially calculating the spectrum power is designated as the calculation mode, it is not necessary to designate the frequency component by the frequency component designation parameter, and the ADC test circuit 114 corresponds to each frequency Bin number. The spectral power of the output signal to be calculated is sequentially calculated. When the mode for calculating the spectrum power of the output signal corresponding to an arbitrary frequency Bin number is designated as the calculation mode, the ADC test circuit 114 corresponds to the frequency Bin number designated by the frequency component designation parameter. The spectral power value to be calculated is calculated. For this reason, when the frequencies of the output signals 210a and 210b are known in advance, the maximum value of the spectrum power value can be efficiently acquired. As described above, the ADC can be evaluated by appropriately specifying the optimum calculation mode according to the ADC evaluation environment and conditions.

  Upon receiving the condition signal, the ADC test circuit 114 analyzes the calculation mode designation parameter included in the condition signal, determines the type of the designated calculation mode, and outputs the output signals 210a and 210b in the designated calculation mode. Set to calculate spectral power. When the ADC test circuit 114 receives a trigger signal after the calculation mode is set, the ADC test circuit 114 starts an ADC evaluation process. That is, the ADC test circuit 114 causes the spectrum power calculation unit 212 to calculate the spectrum power from the output signals 210a and 210b. When the mode for sequentially calculating the spectrum power is designated, the spectrum power calculation unit 212 sequentially stores the calculated spectrum power value in the memory, calculates the spectrum power corresponding to each frequency Bin number, and then calculates the spectrum power. Output to an external evaluation device. As described above, in this embodiment, the test result data itself can be output to the outside, and the ADC performance evaluation can be performed as compared with the conventional technique in which the ADC output signal is stored in the RAM and output to the external evaluation apparatus. Efficiency can be improved. Further, since the spectrum power corresponding to each frequency Bin number can be calculated and output to the outside at one time by one condition signal and trigger signal, the ADC performance can be evaluated more efficiently.

  In the present embodiment, the condition signal and the trigger signal are configured as separate signals, but the condition signal and the trigger signal may be configured as one signal. In this case, when the ADC test circuit 114 receives the signal 1, the ADC test circuit 114 sets calculation conditions according to the designated calculation mode, and starts the ADC evaluation process without waiting for the reception of the trigger signal. be able to.

  In another embodiment, the ADC test circuit 114 uses the spectral power value calculated by the spectral power calculation unit 212 to the ENOB calculation unit 214 to the ENOB of the ADC 112 when the mode for sequentially calculating the spectral power is designated. Can be calculated. In this case, the spectrum power calculation unit 212 stores the calculated spectrum power value in the memory, and the ENOB calculation unit 214 calculates ENOB using the spectrum power value stored in the memory, and an external evaluation device or the like. Output to. This eliminates the need to output spectral power values corresponding to all frequency Bin numbers to an external evaluation device, and further eliminates the need to calculate ENOB using an external evaluation device. Evaluation can be performed even more efficiently.

  In still another embodiment, the ADC test circuit 114 uses the spectrum power value calculated by the spectrum power calculation unit 212 to calculate the THD in the THD calculation unit 216 when the mode for sequentially calculating the spectrum power is designated. Can be calculated. In this case, the spectrum power calculation unit 212 stores the calculated spectrum power value in the memory, and the THD calculation unit 216 calculates the THD using the spectrum power value stored in the memory to obtain an external evaluation device or the like. Output to. This eliminates the need to output spectral power values corresponding to all frequency Bin numbers to an external evaluation device, and further eliminates the need to calculate THD using an external evaluation device. Evaluation can be performed even more efficiently.

  In yet another embodiment, the frequency component designation parameter can be added as a condition signal even when the mode for sequentially calculating the spectrum power is designated as the calculation mode. Thus, when a constant frequency signal is input to the ADC and ADC performance evaluation is performed, the frequency component corresponding to the constant frequency is designated by the frequency component designation parameter, and the spectrum power calculation unit 212 determines the frequency. Since the spectrum power value of the frequency component specified by the component specification parameter can be calculated as a peak point, the circuit that identifies the frequency component that maximizes the spectrum power value can be omitted, and the circuit scale can be reduced. Can do.

FIG. 3 is a diagram showing a circuit configuration of the partial DFT circuit of the present embodiment. The partial DFT circuit of the present embodiment includes adders 310, 312, 314, coefficient multipliers 316, 318, 320, and delay units 322, 324. Adders 310, 312, and 314 add the input signals and output the result. Coefficient multipliers 316, 318, 320 multiply the input signal by the corresponding coefficient and output the result. The delay devices 322 and 324 delay the input signal and output it. A transfer function realized by the partial DFT circuit of the present embodiment is expressed by the following Equation 1 using a z-transform operator.

In Expression 1, fi indicates the target frequency, fs indicates the sampling frequency, and the parameter fi / fs used in the expression is a frequency Bin number / DFT point number that is a frequency component designation parameter.

  FIG. 4 is a frequency characteristic diagram of the partial DFT circuit of the present embodiment, showing the relationship between the spectral power value and the frequency Bin number. In the embodiment shown in FIG. 4, a partial DFT circuit having 512 points is used, and the frequency Bin number is 50 and the spectrum power value is maximum. The ADC test circuit 114 can calculate ENOB and THD using this spectral power value.

  FIG. 5 is a diagram showing a wireless communication system 500 including an information processing apparatus 502 incorporating the semiconductor integrated circuit 100 described with reference to FIG. Hereinafter, the system 500 will be described with reference to FIG. In addition, description is abbreviate | omitted about the content which is common in embodiment shown in FIG. 1, and the content which is different is demonstrated.

  The wireless communication system 500 includes an information processing apparatus 502, an image processing apparatus 540, and a network 550 that interconnects these apparatuses. The information processing apparatus 502 includes a semiconductor integrated circuit 510 similar to the semiconductor integrated circuit 110, a wireless communication circuit 520 similar to the wireless communication circuit 120, and an information processing unit 530. In the present invention, as an embodiment of the information processing apparatus 502, an information processing terminal having a wireless communication function such as a personal computer, a notebook personal computer, a mobile phone, a PDA, or a game machine can be employed. The information processing unit 530 stores a CPU that performs calculation of processing executed by the information processing device 502, a MAC (Media Access Control) that performs access control of the baseband processing unit 516, and a program executed by the information processing device. A network interface that enables data communication with an external device via a network 550, a memory such as a ROM or a RAM that provides an execution space for the program, an input device such as a touch panel or a mouse, a peripheral such as a display or a hard disk drive (I / F). The information processing unit 530 controls the semiconductor integrated circuit 510 and the wireless communication circuit 520 to realize wireless LAN communication in infrastructure mode and wireless LAN communication in ad hoc mode with other devices. The network 550 is configured as a local area network (LAN) using Ethernet (registered trademark), for example. The image processing device 540 receives print data from the information processing device 530 and executes print processing, performs copy processing using the built-in scanner device, or executes scan processing using the built-in scanner device. Then, the scan data can be transmitted to the information processing apparatus 502 via the network 550.

  The information processing apparatus 502 includes, as an operating system (hereinafter referred to as an OS), UNIX (registered trademark), LINUX (registered trademark), WINDOWS (registered trademark) series, WINDOWS (registered trademark) 200X server, and Mac (registered trademark). ) OS etc. can be adopted. Further, the information processing apparatus 502 executes a program written in a program language such as assembler, C, C ++, Java (registered trademark), Java (registered trademark) Script, PERL, RUBY, or PYTHON under the control of the OS described above. The processing executed by the information processing apparatus 502 is realized by reading the program into the RAM providing the execution space and executing the program by the CPU.

  Although the present embodiment has been described so far, the present invention is not limited to the above-described embodiment, and other embodiments, additions, changes, deletions, and the like can be conceived by those skilled in the art. It can be changed, and any aspect is within the scope of the present invention as long as the effects and effects of the present invention are exhibited.

DESCRIPTION OF SYMBOLS 100 ... Semiconductor integrated circuit, 102 ... Digital processing block, 104 ... Analog processing block, 110 ... Semiconductor integrated circuit, 112 ... ADC, 114 ... ADC test circuit, 116 ... Baseband processing part, 118 ... DAC, 120 ... Wireless communication circuit 122a, 122b ... Antenna, 124a, 124b ... BPF, 126 ... LNA, 128a, 128b ... VCO / Mixer, 130a, 130b, 130c, 130d ... LPF, 132a, 132b ... VGA, 134 ... PA, 500 ... Wireless communication system , 502 ... Information processing device, 510 ... Semiconductor integrated circuit, 512 ... ADC, 514 ... ADC test circuit, 516 ... Baseband processing unit, 518 ... DAC, 520 ... Wireless communication circuit, 530 ... Information processing unit, 540 ... Image processing Device, 550 ... Network

JP 2001-358586 A JP 2004-48383 A

Claims (7)

A semiconductor integrated circuit having an analog-digital conversion circuit for converting an analog signal into a digital signal,
A test circuit that performs an evaluation process of the analog-digital conversion circuit using an output signal of the analog-digital conversion circuit;
The test circuit includes:
A semiconductor integrated circuit comprising spectral power calculation means for calculating a spectral power value of an output signal of the analog / digital conversion circuit.   The semiconductor integrated circuit according to claim 1, wherein the spectrum power calculation unit calculates a spectrum power value of the output signal corresponding to each frequency Bin number in accordance with a test request signal received by the test circuit.   The test circuit uses the spectrum power value of the output signal corresponding to each of the frequency Bin numbers calculated by the spectrum power calculation means to calculate the effective bit number of the analog / digital conversion circuit. The semiconductor integrated circuit according to claim 2, further comprising means.   4. The semiconductor integrated circuit according to claim 1, further comprising a THD calculating unit that calculates a THD of the analog-digital conversion circuit using the spectral power value calculated by the spectral power calculating unit. 5. .   5. The spectrum power calculation unit according to claim 1, wherein the spectrum power calculation unit calculates a spectrum power value of the output signal corresponding to each frequency Bin number specified by a test request signal received by the test circuit. 6. Semiconductor integrated circuit. The semiconductor integrated circuit further includes digital processing means for processing an output signal of the analog-digital conversion circuit,
The semiconductor integrated circuit according to claim 1, wherein the digital processing unit is configured as a circuit separate from the test circuit.   An information processing apparatus comprising the semiconductor integrated circuit according to claim 1.