JP2011176174A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

A semiconductor device capable of realizing further integration without impairing reliability.
A linear first electrode including a gate electrode of a first transistor L1 and electrically connected to a source / drain diffusion layer 20 of a second transistor L2 via a first contact layer 48a. A gate wiring 16a and a first gate wiring including the gate electrode of the second transistor L2 and electrically connected to the source / drain diffusion layer 22 of the first transistor via the second contact layer 48b; A parallel linear second gate wiring 16b and an insulating film formed to cover the first gate wiring and the second gate wiring, and the source / source of the first gate wiring and the second transistor An insulating film in which a first opening 46a in which the drain diffusion layer is exposed and the long side direction is the longitudinal direction of the first gate wiring is formed, and the first contact layer embedded in the first opening The has.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  An SRAM (Static Random Access Memory) is a semiconductor device capable of high-speed operation in which memory cells are configured by flip-flop circuits.

  In a semiconductor device such as an SRAM, gate wirings, conductor plugs, and the like are arranged at a very high density in a memory cell portion. By arranging gate wirings, conductor plugs, and the like at an extremely high density, it becomes possible to reduce the size of the memory cell and contribute to an improvement in storage capacity.

  In recent years, further miniaturization and integration of memory cells are required in order to realize cost reduction and capacity increase.

JP 2008-16480 A

  However, when gate wirings and the like are arranged at a very high density, a short circuit or the like is likely to occur, and the reliability of the semiconductor device may be impaired.

  An object of the present invention is to provide a semiconductor device that can realize further integration without impairing reliability.

  According to one aspect of the embodiment, the source / drain diffusion layer of the second transistor is formed on the semiconductor substrate via the gate insulating film, includes the gate electrode of the first transistor, and passes through the first contact layer. A linear first gate wiring electrically connected to the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and including a gate electrode of the second transistor, through a second contact layer A second gate line in a straight line parallel to the first gate line, electrically connected to the source / drain diffusion layer of the first transistor, the first gate line, and the second gate line. An insulating film formed on the semiconductor substrate so as to cover the gate wiring, exposing the first gate wiring and the source / drain diffusion layer of the second transistor; There is provided a semiconductor device comprising: an insulating film in which a first opening which is the longitudinal direction of the gate wiring is formed; and the first contact layer embedded in the first opening. The

  According to another aspect of the embodiment, the gate electrode of the first transistor is formed on the semiconductor substrate via the gate insulating film, and is electrically connected to the source / drain diffusion layer of the second transistor. A linear first gate wiring and a gate insulating film formed on the semiconductor substrate, including a gate electrode of the second transistor, and formed in a source / drain diffusion layer of the first transistor. A linear second gate wiring parallel to the first gate wiring and the first gate wiring and the second gate wiring, which are electrically connected, are formed on the semiconductor substrate so as to cover the first gate wiring and the second gate wiring. A first opening that exposes the first gate wiring, and a second opening that exposes the source / drain diffusion layer of the second transistor. Gate wiring An insulating film arranged in a longitudinal direction, a first contact layer embedded in the first opening, a second contact layer embedded in the second opening, and formed on the insulating film And providing a semiconductor device comprising a first wiring for connecting the first contact layer and the second contact layer.

  According to still another aspect of the embodiment, a linear first gate wiring including the gate electrode of the first transistor; a gate electrode of the second transistor; and parallel to the first gate wiring. Forming a straight second gate wiring on a semiconductor substrate via a gate insulating film, forming a source / drain diffusion layer on each of the semiconductor substrates on both sides of the gate electrode, Forming an insulating film on the semiconductor substrate, on the first gate wiring and the second gate wiring; and on the first gate wiring and the source / drain diffusion layer of the second transistor. Forming a first opening in the insulating film that is exposed and whose long side direction is the longitudinal direction of the first gate wiring; and embedding the first contact layer in the first opening. Having The method of manufacturing a semiconductor device according to symptoms is provided.

  According to still another aspect of the embodiment, a linear first gate wiring including the gate electrode of the first transistor; a gate electrode of the second transistor; and parallel to the first gate wiring. Forming a straight second gate wiring on a semiconductor substrate via a gate insulating film, forming a source / drain diffusion layer on each of the semiconductor substrates on both sides of the gate electrode, Forming an insulating film on the semiconductor substrate, on the first gate wiring and the second gate wiring; a first opening exposing the first gate wiring; and the second transistor. Forming a second opening that exposes the source / drain diffusion layer in the insulating film so as to be arranged in a longitudinal direction of the first gate wiring; and a first opening in the first opening. Contact layer Embedding, embedding a second contact layer in the second opening, and forming a first wiring connecting the first contact layer and the second contact layer on the insulating film A method for manufacturing a semiconductor device is provided.

  According to the disclosed semiconductor device and the manufacturing method thereof, since the opening is formed so that the long side direction is the longitudinal direction of the gate wiring, the opening is in contact with the void generated in the insulating film embedded between the gate wirings. Absent. Since the opening is not connected via the void, the contact layer is not electrically short-circuited via the void. Therefore, it is possible to provide a semiconductor device that can be integrated without impairing reliability and a method for manufacturing the semiconductor device.

FIG. 3 is a plan view (part 1) illustrating the semiconductor device according to the first embodiment; It is sectional drawing which shows the semiconductor device by 1st Embodiment. FIG. 6 is a plan view (part 2) illustrating the semiconductor device according to the first embodiment; 1 is a circuit diagram showing a semiconductor device according to a first embodiment. FIG. FIG. 6 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment; It is a top view (the 1) which shows the semiconductor device by 2nd Embodiment. It is a top view (the 2) which shows the semiconductor device by 2nd Embodiment. It is a top view (the 1) which shows the semiconductor device by 3rd Embodiment. It is sectional drawing which shows the semiconductor device by 3rd Embodiment. It is a top view (the 2) which shows the semiconductor device by 3rd Embodiment. FIG. 11 is a plan view (part 3) illustrating the semiconductor device according to the third embodiment; It is process sectional drawing which shows the manufacturing method of the semiconductor device by 3rd Embodiment. It is a top view (the 1) which shows the semiconductor device by a reference example. It is sectional drawing of the semiconductor device by a reference example. It is a top view (the 2) which shows the semiconductor device by a reference example.

  FIG. 16 is a plan view (part 1) illustrating a semiconductor device according to a reference example. FIG. 17 is a cross-sectional view of a semiconductor device according to a reference example. 17 is a cross-sectional view taken along the line AA ′ of FIG. 16, and the right view of FIG. 17 is a cross-sectional view taken along the line BB ′ of FIG. FIG. 18 is a plan view (part 2) of the semiconductor device according to the reference example. FIG. 16 shows an example of the shape of a design pattern, and FIG. 18 shows an example of the shape of a pattern that is actually formed.

  In the semiconductor substrate 110, element isolation regions 112 that define element regions 111a to 111d are formed. Gate wirings 116 a to 116 d are formed on the semiconductor substrate 110 with a gate insulating film 114 interposed therebetween. A sidewall insulating film 18 is formed on the side walls of the gate wirings 116a to 116d.

  The gate wiring 116a is formed so as to intersect the element regions 111a and 111c. The gate wiring 116a extends to the vicinity of the source / drain diffusion layer 120 of the load transistor L2 formed in the element region 111b. Source / drain diffusion layers 122 and 124 are formed in the element region 111a on both sides of the gate wiring 116a. The gate transistor 116a and the source / drain diffusion layers 122 and 124 form a load transistor L1. Source / drain diffusion layers 126 and 128 are formed in the element region 111c on both sides of the gate wiring 116a. A driver transistor D1 is formed by the gate electrode 116a and the source / drain diffusion layers 126 and 128.

  The gate wiring 116b is formed so as to intersect the element regions 111b and 111d. The gate wiring 116b extends to the vicinity of the source / drain diffusion layer 122 of the load transistor L1 formed in the element region 111a. Source / drain diffusion layers 120 and 130 are formed in the element region 11b on both sides of the gate wiring 116b. The gate transistor 116b and the source / drain diffusion layers 120 and 130 form a load transistor L2. Source / drain diffusion layers 132 and 134 are formed in the element region 111d on both sides of the gate wiring 116b. A driver transistor D2 is formed by the gate electrode 116b and the source / drain diffusion layers 132 and 134.

  The gate wiring 116c is formed so as to intersect the element region 111c. Source / drain diffusion layers 126 and 136 are formed in the element region 111c on both sides of the gate wiring 116c. A transfer transistor T1 is formed by the gate electrode 116c and the source / drain diffusion layers 126 and 136.

  The gate wiring 116d is formed so as to intersect the element region 111d. Source / drain diffusion layers 132 and 138 are formed in the element region 111d on both sides of the gate electrode 116d. A transfer transistor T2 is formed by the gate electrode 116d and the source / drain diffusion layers 132 and 138.

  A source / drain electrode 152 of silicide is formed on the source / drain diffusion layers 120, 122, 124, 126, 128, 130, 132, 134, 136, 138. A silicide film 152 is formed on the gate wirings 116a to 116d.

  On the semiconductor substrate 10 on which these transistors L1, L2, D1, D2, T1, and T2 are formed, for example, an insulating film 140 of silicon nitride is formed so as to embed between the gate wirings 116a to 116d.

  On the semiconductor substrate 110 on which the insulating film 140 is formed, for example, an insulating film 142 of silicon dioxide is formed. The surface of the insulating film 142 is planarized by polishing. The insulating film 140 and the insulating film 142 form an interlayer insulating film 144.

  In the interlayer insulating film 144, an opening (contact hole) 146a that integrally exposes the end of the gate wiring 116a and the source / drain diffusion layer 120 of the load transistor L2 is formed. The shape of the cross section of the opening 146a in the direction parallel to the surface of the semiconductor substrate 110 is, for example, substantially elliptical (see FIG. 18). The long side direction of the opening 146a is perpendicular to the longitudinal direction of the gate wiring 116a. A contact layer 148a of tungsten, for example, is embedded in the opening 146a. A contact layer buried in such an opening that integrally exposes the gate wiring and the source / drain diffusion layer is called a share contact.

  In the interlayer insulating film 144, an opening 146b that integrally exposes the end of the gate wiring 116b and the source / drain diffusion layer 122 of the load transistor L1 is formed. The shape of the cross section of the opening 146b in the direction parallel to the surface of the semiconductor substrate 110 is, for example, substantially elliptical (see FIG. 18). The long side direction of the opening 146b is perpendicular to the longitudinal direction of the gate wiring 116b. A contact layer 148b of tungsten, for example, is embedded in the opening 146b.

  In the interlayer insulating film 144, an opening 146 c that exposes the source / drain diffusion layer 124 and an opening 146 d that exposes the source / drain diffusion layer 130 are formed. Further, in the interlayer insulating film 144, an opening 146e exposing the source / drain diffusion layer 28 and an opening 146f exposing the source / drain diffusion layer 26 are formed. The interlayer insulating film 144 has an opening 146g exposing the source / drain diffusion layer 136 and an opening 146h exposing the source / drain diffusion layer 134. The interlayer insulating film 144 has an opening 146 i that exposes the source / drain diffusion layer 32 and an opening 146 j that exposes the source / drain diffusion layer 138. The cross-sectional shape of the openings 146c to 146j in the direction parallel to the surface of the semiconductor substrate 110 is, for example, a substantially circular shape (see FIG. 18). For example, tungsten contact layers 148c to 148j are embedded in the openings 146c to 146j.

  When the distance between the gate wiring 116a and the gate wiring 116b is relatively narrow, in the process of growing the insulating film 140, the surface of the insulating film 140 is in contact with the gap between the gate wiring 116a and the gate wiring 116b. Holes, voids) 153 may occur. In the semiconductor device according to the reference example illustrated in FIG. 16, the opening 146 a and the opening 146 b may be in contact with the void 153. When the openings 146a and 146b are in contact with the void 153, the material of the contact layers 148a and 148b embedded in the openings 146a and 146b may enter the void 153, and the contact layer 148a and the contact layer 148b A short circuit may occur through the void 153.

  As described above, in the semiconductor device according to the reference example, when the gate wirings 146a to 146d are arranged at a very high density, a short circuit or the like is likely to occur, and the reliability of the semiconductor device may be impaired.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS. FIG. 1 is a plan view (part 1) of the semiconductor device according to the present embodiment. FIG. 2 is a sectional view of the semiconductor device according to the present embodiment. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, the center view of FIG. 2 is a cross-sectional view taken along the line BB ′ of FIG. 1, and the right side of FIG. FIG. FIG. 3 is a plan view (part 2) of the semiconductor device according to the present embodiment. FIG. 1 shows an example of the shape of a design pattern, and FIG. 3 shows an example of the shape of a pattern that is actually formed. FIG. 4 is a circuit diagram illustrating the semiconductor device according to the present embodiment.

(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  In the semiconductor substrate 10, element isolation regions 12 that define element regions 11a to 11d are formed. For example, a silicon substrate is used as the semiconductor substrate 10.

  Gate wirings 16 a to 16 d are formed on the semiconductor substrate 10 with a gate insulating film 14 interposed therebetween. Sidewall insulating films 18 are formed on the side walls of the gate wirings 16a to 16d.

  The gate wiring 16a is formed so as to intersect the element regions 11a and 11c. The gate wiring 16a includes the gate electrode of the load transistor L1 and the gate electrode of the driver transistor D1, and commonly connects the gate electrode of the load transistor L1 and the gate electrode of the driver transistor D1. The gate wiring 16a extends to the vicinity of the source / drain diffusion layer 20 of the load transistor L2 formed in the element region 11b.

  Source / drain diffusion layers 22 and 24 are formed in the element region 11a on both sides of the gate wiring 16a. A load transistor L1 is formed by the gate electrode 16a and the source / drain diffusion layers 22 and 24.

  Source / drain diffusion layers 26 and 28 are formed in the element region 11c on both sides of the gate wiring 16a. A driver transistor D1 is formed by the gate electrode 16a and the source / drain diffusion layers 26 and 28.

  The gate wiring 16b is formed so as to intersect the element regions 11b and 11d. The gate wiring 16b includes the gate electrode of the load transistor L2 and the gate electrode of the driver transistor D2, and commonly connects the gate electrode of the load transistor L2 and the gate electrode of the driver transistor D2. The gate wiring 16b extends to the vicinity of the source / drain diffusion layer 22 of the load transistor L1 formed in the element region 11a. The longitudinal direction of the gate wiring 16a is the longitudinal direction of the gate wiring 16b. The gate wiring 16a and the gate wiring 16b are opposed to each other in a part of the region. In such a region, the gate line 16a and the gate line 16b are relatively close to each other.

  Source / drain diffusion layers 20 and 30 are formed in the element region 11b on both sides of the gate wiring 16b. A load transistor L2 is formed by the gate electrode 16b and the source / drain diffusion layers 20 and 30.

  Source / drain diffusion layers 32 and 34 are formed in the element region 11d on both sides of the gate wiring 16b. A driver transistor D2 is formed by the gate electrode 16b and the source / drain diffusion layers 32 and.

  The gate wiring 16c is formed so as to intersect the element region 11c. The gate line 16c is located on an extension line of the gate line 16b. The gate wiring 16c includes the gate electrode of the transfer transistor T1. Source / drain diffusion layers 26 and 36 are formed in the element region 11c on both sides of the gate wiring 16c. A transfer transistor T1 is formed by the gate electrode 16c and the source / drain diffusion layers 26 and 36. One source / drain diffusion layer 26 of the transfer transistor T1 and one source / drain diffusion layer 26 of the driver transistor D1 are formed by a common source / drain diffusion layer 26.

  The gate wiring 16d is formed so as to intersect the element region 11d. The gate line 16d is located on an extension line of the gate line 16a. The gate wiring 16d includes the gate electrode of the transfer transistor T2. Source / drain diffusion layers 32 and 38 are formed in the element region 11d on both sides of the gate electrode 16d. A transfer transistor T2 is formed by the gate electrode 16d and the source / drain diffusion layers 32 and 38. One source / drain diffusion layer 32 of the transfer transistor T2 and one source / drain diffusion layer 32 of the driver transistor D2 are formed by a common source / drain diffusion layer 32.

  The width of the gate wirings 16a to 16d, that is, the gate length is, for example, about 35 to 60 nm. The height of the gate wirings 16a to 16d is, for example, about 70 to 100 nm. The distance between the gate lines 16a and 16d and the gate lines 16b and 16c, that is, the pitch of the gate lines is, for example, about 0.16 to 0.2 μm.

  On the source / drain diffusion layers 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, for example, a silicide film 52 of nickel silicide is formed. The silicide film 52 on the source / drain diffusion layers 20, 22, 24, 26, 28, 30, 32, 34, 36, and 38 functions as a source / drain electrode. A silicide film 52 of, for example, nickel silicide is formed on the gate wirings 16a to 16d.

  On the semiconductor substrate 10 on which these transistors L1, L2, D1, D2, T1, and T2 are formed, an insulating film 40 of, for example, silicon nitride is formed. The insulating film 40 is formed so as to be embedded between the gate wirings 16a to 16d. When the distance between the gate wiring 16a and the gate wiring 16b is relatively narrow, the surface of the insulating film 40 comes into contact with the gate wiring 16a and the gate wiring 16b in the process of growing the insulating film 40, In some cases, voids (voids, voids) 53 are generated.

  On the semiconductor substrate 10 on which the insulating film 40 is formed, for example, an insulating film 42 of silicon dioxide is formed. The surface of the insulating film 42 is planarized by polishing. The insulating film 40 and the insulating film 42 form an interlayer insulating film 44.

  In the interlayer insulating film 44, an opening (contact hole) 46a that integrally exposes the end portion of the gate wiring 16a and the source / drain diffusion layer 20 of the load transistor L2 is formed. The shape of the cross section of the opening 46a in the direction parallel to the surface of the semiconductor substrate 10 is, for example, substantially elliptical (see FIG. 3). The long side direction of the opening 46a is the longitudinal direction of the gate wiring 16a. The dimension of the long side (major axis) of the opening 46a, that is, the major axis is, for example, 70 to 100 nm. The dimension of the short side (short axis) of the opening 46a, that is, the short diameter is, for example, 50 to 70 nm. A contact layer 48a of tungsten, for example, is embedded in the opening 46a.

  The interlayer insulating film 44 is formed with an opening 46b that integrally exposes the end of the gate wiring 16b and the source / drain diffusion layer 22 of the load transistor L1. The shape of the cross section of the opening 46b in the direction parallel to the surface of the semiconductor substrate 10 is, for example, substantially elliptical (see FIG. 3). The long side direction of the opening 46b is the longitudinal direction of the gate wiring 16b. The dimension of the long side of the opening 46b is, for example, 70 to 100 nm. The dimension of the short side of the opening 46b is, for example, 50 to 70 nm. A contact layer 48b of tungsten, for example, is embedded in the opening 46b.

  In the interlayer insulating film 44, an opening 46c exposing the source / drain diffusion layer 24 of the load transistor L1 and an opening 46d exposing the source / drain diffusion layer 30 of the load transistor L2 are formed. Further, the interlayer insulating film 44 has an opening 46e exposing the source / drain diffusion layer 28 of the driver transistor D1, and an opening 46f exposing the common source / drain diffusion layer 26 of the driver transistor D1 and the transfer transistor T1. Is formed. The interlayer insulating film 44 is formed with an opening 46g exposing the source / drain diffusion layer 36 of the driver transistor T1 and an opening 46h exposing the source / drain diffusion layer 34 of the driver transistor D2. Further, the interlayer insulating film 44 has an opening 46i exposing the common source / drain diffusion layer 32 of the driver transistor D2 and the transfer transistor T2, and an opening 46j exposing the source / drain diffusion layer 38 of the driver transistor T2. Is formed.

  The cross-sectional shape of the openings 46c to 46j in the direction parallel to the surface of the semiconductor substrate 10 is, for example, a substantially circular shape (see FIG. 3). The diameter of the openings 46c to 46j is, for example, 90 nm. For example, tungsten contact layers 48c to 48j are embedded in the openings 46c to 46j.

  On the interlayer insulating film 44, wirings 50 (see FIG. 2) connected to the contact layers 48a to 48j, respectively, are formed.

  The contact layer 48a and the contact layer 48i are electrically connected by a wiring 50. The contact layer 48b and the contact layer 48f are electrically connected by a wiring 50.

  The wiring 50 connected to the contact layers 48c and 48d is electrically connected to the power supply voltage Vdd (see FIG. 4). The wiring 50 connected to the contact layers 48e and 48h is electrically connected to the ground voltage Vss (see FIG. 4).

  The wiring 50 connected to the contact layers 46g and 46j is electrically connected to the bit line BL (see FIG. 4). The gate lines 16a and 16b are electrically connected to the word line WL (see FIG. 4) via a contact layer and a line 50 (not shown).

  FIG. 4 is a circuit diagram of the memory cell of the semiconductor device according to the present embodiment.

  As shown in FIG. 4, an inverter 54a is formed by the load transistor L1 and the driver transistor D1. The load transistor L2 and the driver transistor D2 constitute an inverter 54b. A flip-flop circuit 56 is formed by the inverter 54a and the inverter 54b. The flip-flop circuit 56 is controlled by transfer transistors T1 and T2 connected to the bit line BL and the word line WL. A memory cell 58 is formed by the load transistors L1 and L2, the driver transistors D1 and D2, and the transfer transistors T1 and T2.

  In the semiconductor device according to the present embodiment, the long side direction of the openings 46a and 46b exposing the gate wirings 16a and 16b and the source / drain diffusion layers 20 and 22 is mainly the longitudinal direction of the gate wirings 16a and 16b. There is a special feature. In the present embodiment, since the long side direction of the openings 46 a and 46 b is the longitudinal direction of the gate wirings 16 a and 16 b, the openings 46 a and 46 b are not connected to the void 53. According to the present embodiment, since the openings 46 a and 46 b are not connected via the void 53, the contact layers 48 a and 48 b are not electrically short-circuited via the void 53. Therefore, according to the present embodiment, it is possible to provide a semiconductor device that can be integrated without impairing reliability.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 5 to 8 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, element isolation regions 12 that define element regions 11a to 11d (see FIG. 1) are formed in the semiconductor substrate 10 by, eg, STI (Shallow Trench Isolation) (see FIG. 5A). For example, a silicon substrate is used as the semiconductor substrate 10. For example, silicon dioxide is used as the element isolation region 12.

  Next, a gate insulating film 14 of, for example, silicon dioxide having a physical film thickness of 0.6 to 2 nm is formed on the entire surface by, eg, thermal oxidation.

  Next, a polysilicon film having a thickness of about 70 to 100 nm is formed on the entire surface by, eg, CVD (Chemical Vapor Deposition).

  Next, polysilicon gate wirings 16a to 16d are formed by patterning the polysilicon film using a photolithography technique. The gate wiring 16a is formed in a straight line so as to intersect the element regions 11a and 11c. The gate wiring 16b is formed in a straight line so as to intersect the element regions 11b and 11d. The gate wiring 16c is formed in a straight line so as to intersect the element region 11c. The gate wiring 16d is formed in a straight line so as to intersect the element region 11d. The longitudinal directions of the gate wirings 16a to 16d are the same direction. The gate wiring 16a and the gate wiring 16b are formed so as to be close to each other in a partial region. The gate line 16c is formed so as to be located on an extension line of the gate line 16b. The gate line 16d is formed so as to be located on an extension line of the gate line 16a. The width of the gate wirings 16a to 16d, that is, the gate length is, for example, about 35 to 60 nm. The distance between the gate lines 16a and 16d and the gate lines 16b and 16c, that is, the pitch of the gate lines is, for example, about 0.16 to 0.2 μm.

  Next, an extension region (not shown) for forming a shallow region of the extension source / drain structure is formed in the semiconductor substrate 10 on both sides of the gate wirings 16a to 16d by introducing dopant impurities by ion implantation. Form.

  Next, a silicon oxide film of, eg, a 30-60 nm-thickness is formed on the entire surface by, eg, CVD.

  Next, the silicon oxide film is etched by, for example, anisotropic etching. As a result, a sidewall insulating film 18 of silicon dioxide is formed on the sidewall portions of the gate wirings 16a to 16d (see FIG. 5B). The thickness of the sidewall insulating film 18 is, for example, about 30 to 60 nm. When forming the sidewall insulating film 18 by anisotropically etching the silicon oxide film, the surface layer portion of the element isolation region 12 of silicon dioxide is also etched. Therefore, a recess 19 as shown in FIG. 5B is formed on the surface of the element isolation region 12. Such a recess 19 formed in the element isolation region 12 is a factor that easily causes a void 53 (see FIG. 6B) between the gate wiring 16a and the gate wiring 16b when the insulating film 40 is formed. It becomes.

  Next, by introducing a dopant impurity by ion implantation, an impurity diffusion region for forming a deep region of the extension source / drain structure is formed in the semiconductor substrate 10 on both sides of the gate wirings 16a to 16d. As a result, source / drain diffusion layers 20, 22, 24, 26, 28, 30, 32, 34, 36, and 38 (see FIG. 1) having extension regions and deep impurity diffusion regions are formed.

  Next, a refractory metal film having a film thickness of 5 to 30 nm is formed on the entire surface by, eg, sputtering. For example, a nickel film is formed as the refractory metal film.

  Next, by performing heat treatment, the surface of the semiconductor substrate 10 and the refractory metal film are reacted, and the upper surfaces of the gate wirings 16a to 16d and the refractory metal film are reacted. Thereafter, the unreacted refractory metal film is removed by etching. Thereby, a silicide film 52 of, for example, nickel silicide is formed on the source / drain diffusion layers 20, 22, 24, 26, 28, 30, 32, 34, 36, and 38. The silicide film 52 on the source / drain diffusion layers 20, 22, 24, 26, 28, 30, 32, 34, 36, and 38 functions as a source / drain electrode. Further, for example, a silicide film 52 of nickel silicide is formed on the gate wirings 16a to 16d (see FIG. 6A).

Next, an insulating film 40 of silicon nitride having a thickness of, for example, about 30 to 80 nm is formed on the entire surface by, eg, plasma CVD (see FIG. 6B). The conditions for forming the insulating film 40 are, for example, as follows. That is, the frequency of the high frequency power to be applied is, for example, 13.56 MHz. The gas introduced into the deposition chamber is, for example, a mixed gas containing SiH ₄ gas, NH ₃ gas, and N ₂ gas. The temperature in the film forming chamber is set to 350 to 450 ° C., for example. The insulating film 40 is formed so as to embed between the gate wirings 16a to 16d. In locations where the gate wiring 16 a and the gate wiring 16 b are close to each other, the insulating film 40 may grow so that the surfaces of the insulating film 40 are in contact with each other, and a void 53 may be generated in the insulating film 40.

Next, an insulating film 42 of, for example, 400 to 700 nm of silicon dioxide is formed on the entire surface by, eg, plasma CVD (see FIG. 7A). The conditions for forming the insulating film 42 are, for example, as follows. That is, the frequency of the high frequency power to be applied is, for example, 13.56 MHz. The gas introduced into the deposition chamber is a mixed gas containing SiH ₄ gas and N ₂ O gas. The temperature in the film forming chamber is set to 350 to 450 ° C., for example.

Next, the surface of the insulating film 42 is planarized by, for example, CMP (Chemical Mechanical Polishing). Next, an interlayer insulating film 44 is formed by the insulating film 40 and the insulating film 42. Next, openings 46a to 46j are formed in the interlayer insulating film 44 using a photolithography technique (see FIG. 7B). The opening 46a is formed so as to integrally expose the end of the gate wiring 16a and the source / drain diffusion layer 20 of the load transistor L2. The opening 46b is formed so as to integrally expose the end of the gate wiring 16b and the source / drain diffusion layer 22 of the load transistor L1. The cross-sectional shape of the openings 46a and 46b in the direction parallel to the surface of the semiconductor substrate 10 is, for example, substantially elliptical (see FIG. 3). The long side direction of the openings 46a and 46b is the longitudinal direction of the gate wiring 16a. The dimension (major axis) in the long side direction of the openings 46a and 46b is, for example, about 70 to 100 nm. The dimension (minor axis) in the short side direction of the openings 46a and 46b is, for example, about 50 to 70 nm. The opening 46c is formed so as to expose the source / drain diffusion layer 24 of the load transistor L1. The opening 46d is formed so as to expose the source / drain diffusion layer 30 of the load transistor L2. The opening 46e is formed so as to expose the source / drain diffusion layer 28 of the driver transistor D1. The opening 46f is formed so as to expose the common source / drain diffusion layer 26 of the driver transistor D1 and the transfer transistor T1. The opening 46g is formed so as to expose the source / drain diffusion layer 36 of the driver transistor T1. The opening 46h is formed so as to expose the source / drain diffusion layer 34 of the driver transistor D2. The opening 46i is formed so as to expose the common source / drain diffusion layer 32 of the driver transistor D2 and the transfer transistor T2. The opening 46j is formed so as to expose the source / drain diffusion layer 38 of the driver transistor T2. The cross-sectional shape of the openings 46c to 46j in the direction parallel to the surface of the semiconductor substrate 10 is, for example, a substantially circular shape (see FIG. 3). The diameters of the openings 46c to 46j are, for example, about 50 to 70 nm.

  Next, a glue layer is formed on the entire surface by sequentially forming, for example, a Ti film having a thickness of 2 to 10 nm and a TiN film having a thickness of 2 to 10 nm, for example, by sputtering or CVD.

  Next, a tungsten film with a film thickness of, for example, 40 to 60 nm is formed on the entire surface by, eg, sputtering.

  Next, the tungsten film is polished by CMP, for example, until the surface of the interlayer insulating film 44 is exposed. As a result, tungsten contact layers 48a to 48j are embedded in the openings 46a to 46j, respectively.

  Next, a conductive film is formed on the entire surface by, eg, sputtering.

  Next, by using the photolithography technique, the conductive film is patterned to form the wiring 50 connected to the contact layers 48a to 48j.

  Thus, the semiconductor device according to the present embodiment is manufactured.

  Thus, according to the present embodiment, the long sides of the openings 46 a and 46 b are the longitudinal directions of the gate wirings 16 a and 16 b, so that the openings 46 a and 46 b are not connected to the void 53. According to the present embodiment, since the openings 46 a and 46 b are not connected via the void 53, the contact layers 48 a and 48 b are not electrically short-circuited via the void 53. Therefore, according to the present embodiment, it is possible to provide a semiconductor device that can be integrated without impairing reliability.

[Second Embodiment]
A semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 9 is a plan view (part 1) of the semiconductor device according to the present embodiment. FIG. 10 is a plan view (part 2) of the semiconductor device according to the present embodiment. FIG. 9 shows an example of the shape of the design pattern, and FIG. 10 shows an example of the shape of the pattern that is actually formed. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 8 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The semiconductor device according to the present embodiment is mainly characterized in that the end of the gate line 16a is bent so as to be away from the gate line 16b, and the end of the gate line 16b is bent so as to be away from the gate line 16a. .

  As shown in FIGS. 9 and 10, the end portion of the gate wiring 16a is bent in the vicinity of the source / drain diffusion layer 20 so as to be away from the gate wiring 16b.

  Further, the end of the gate line 16b is bent in the vicinity of the source / drain diffusion layer 22 so as to be away from the gate line 16a.

  The long side direction of the openings 46a and 46b formed in the interlayer insulating film 44 is the longitudinal direction of the gate wirings 16a and 16b. The opening 46a integrally exposes the gate wiring 16a and the source / drain diffusion layer 20. The opening 46b integrally exposes the gate wiring 16b and the source / drain diffusion layer 22. The cross sections of the openings 46a and 46b in the direction parallel to the surface of the semiconductor substrate 10 are substantially elliptical. The long side direction of the openings 46a and 46b is the longitudinal direction of the gate wirings 16a and 16b.

  In the present embodiment, since the end of the gate line 16a is bent so as to be away from the gate line 16b, and the end of the gate line 16b is bent so as to be away from the gate line 16a, the gate line 16a and the gate line 16b are Are very close to each other. For this reason, according to the present embodiment, as shown in FIGS. 9 and 10, the portion where the void 53 is formed becomes extremely small. For this reason, according to this embodiment, it can prevent more reliably that the opening parts 46a and 46b are connected with the void 53. FIG.

  Thus, the end of the gate line 16a may be bent so as to be away from the gate line 16b, and the end of the gate line 16b may be bent so as to be away from the gate line 16a.

[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment will be described with reference to FIGS. FIG. 11 is a plan view (part 1) of the semiconductor device according to the present embodiment. FIG. 12 is a sectional view of the semiconductor device according to the present embodiment. FIG. 13 is a plan view (part 2) of the semiconductor device according to the present embodiment. FIG. 14 is a plan view (part 3) of the semiconductor device according to the present embodiment. FIG. 11 shows an example of the shape of the design pattern, and FIGS. 13 and 14 show examples of the shape of the pattern that is actually formed. The same components as those of the semiconductor device and the manufacturing method thereof according to the first or second embodiment shown in FIGS. 1 to 10 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The semiconductor device according to the present embodiment is mainly characterized in that at least the opening 46k exposing the gate wiring 16a and the opening 46l exposing at least the source / drain diffusion layer 20 are arranged in the longitudinal direction of the gate wiring 16a. There is one. In the semiconductor device according to the present embodiment, at least the opening 46m exposing the gate wiring 16b and the opening 46n exposing at least the source / drain diffusion layer 22 are arranged in the longitudinal direction of the gate wiring 16b. There is one of the features.

  As shown in FIGS. 11 and 12, the interlayer insulating film 44 has an opening 46k exposing at least the gate wiring 16a and an opening 46l exposing at least the source / drain diffusion layer 20 in the longitudinal direction of the gate wiring 16a. It is arranged. The cross-sectional shape of the openings 46k and 46l in the direction parallel to the surface of the semiconductor substrate 10 is, for example, a substantially circular shape (see FIG. 13). The diameters of the openings 46k and 46l are, for example, about 50 to 70 nm. Contact layers (conductor plugs) 48k and 48l are embedded in the openings 46k and 46l, respectively.

  In the interlayer insulating film 44, at least an opening 46m exposing the gate wiring 16b and an opening 46m exposing at least the source / drain diffusion layer 22 are arranged in the longitudinal direction of the gate wiring 16b. The cross-sectional shape of the openings 46m and 46n in the direction parallel to the surface of the semiconductor substrate 10 is, for example, a substantially circular shape (see FIG. 13). The diameters of the openings 46m and 46n are, for example, about 50 to 70 nm. Contact layers 48m and 48n are embedded in the openings 46m and 46n, respectively.

  A wiring 50 is formed on the interlayer insulating film 44. The contact layer 48k and the contact layer 48l are connected by a wiring 50. The contact layer 48m and the contact layer 48n are connected by a wiring 50.

  As described above, the opening 46k exposing at least the gate wiring 16a and the opening 46l exposing at least the source / drain diffusion layer 20 may be arranged in the longitudinal direction of the gate wiring 16a. Further, the opening 46m exposing at least the gate wiring 16b and the opening 46n exposing at least the source / drain diffusion layer 22 may be arranged in the longitudinal direction of the gate wiring 16b. Since the contact layer 48k and the contact layer 48l are connected by the wiring 50, the gate wiring 16a and the source / drain diffusion layer 20 are electrically connected even when the openings 46k and 46l are arranged in this way. Can connect. Further, since the contact layer 48m and the contact layer 48n are connected by the wiring 50, the gate wiring 16b and the source / drain diffusion layer 22 are electrically connected even when the openings 46m and 46n are arranged in this way. Can be connected. Therefore, according to this embodiment, it is possible to provide a semiconductor device that can be integrated without impairing reliability.

  When the pattern for forming the opening 46k and the pattern for forming the opening 46l are close to each other, the opening 46k and the opening 46l are connected, and the opening 46o as shown in FIG. Sometimes it becomes. In addition, when the pattern for forming the opening 46m and the pattern for forming the opening 46n are close to each other, the opening 46m and the opening 46n are connected, and the opening as shown in FIG. It may be 46p. When such an opening 46o is formed, the gate wiring 16a and the source / drain diffusion layer 20 are integrally exposed as in the first and second embodiments. Further, when such an opening 46p is formed, the gate wiring 16b and the source / drain diffusion layer 22 are integrally exposed as in the first and second embodiments. Accordingly, the openings 46o and 46p may be formed as shown in FIG.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 15 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment.

  First, from the step of forming the element isolation region 12 to the step of forming the interlayer insulating film 44 on the semiconductor substrate 10, the semiconductor device according to the first embodiment described above with reference to FIGS. 5A to 7A is used. Since this is the same as the manufacturing method, the description is omitted.

  Next, openings 46e to 46n are formed in the interlayer insulating film 44 by using a photolithography technique (see FIG. 15A). Since the openings 46e to 46j are the same as those in the method for manufacturing the semiconductor device according to the first embodiment, the description thereof is omitted. The opening 46k is formed so as to expose at least the gate wiring 16a. The opening 46l is formed so as to expose at least the source / drain diffusion layer 20. The opening 46m is formed so as to expose at least the gate wiring 16b. The opening 46n is formed so as to expose at least the source / drain diffusion layer 22. The cross-sectional shape of the openings 46e to 46n in the direction parallel to the surface of the semiconductor substrate 10 is, for example, a substantially circular shape (see FIG. 14). The diameters of the openings 46e to 46n are, for example, about 50 to 70 nm.

  Next, a glue layer (not shown) is formed on the entire surface by sequentially forming, for example, a Ti film having a thickness of 5 to 20 nm and a TiN film having a thickness of 5 to 20 nm, for example, by sputtering or CVD. Form.

  Next, a tungsten film with a film thickness of, for example, 40 to 60 nm is formed on the entire surface by, eg, CVD.

  Next, the tungsten film is polished by CMP, for example, until the surface of the interlayer insulating film 44 is exposed. As a result, tungsten contact layers 48a to 48j are embedded in the openings 46a to 46j, respectively.

  Next, a conductive film is formed on the entire surface by, eg, sputtering.

  Next, by using the photolithography technique, the conductive film is patterned to form the wiring 50 connected to the contact layers 48a to 48j. The contact layer 48k and the contact layer 48l are connected by a wiring 50. The contact layer 48m and the contact layer 48n are connected by a wiring 50.

  Thus, the semiconductor device according to the present embodiment is manufactured.

  Thus, according to the present embodiment, the opening 46k exposing at least the gate wiring 16a and the opening 46l exposing at least the source / drain diffusion layer 20 may be arranged in the longitudinal direction of the gate wiring 16a. Further, the opening 46m exposing at least the gate wiring 16b and the opening 46n exposing at least the source / drain diffusion layer 22 may be arranged in the longitudinal direction of the gate wiring 16b. Since the contact layer 48k and the contact layer 48l are connected by the wiring 50, the gate wiring 16a and the source / drain diffusion layer 20 are electrically connected even when the openings 46k and 46l are arranged in this way. obtain. Further, since the contact layer 48m and the contact layer 48n are connected by the wiring 50, the gate wiring 16b and the source / drain diffusion layer 22 are electrically connected even when the openings 46m and 46n are arranged in this way. Can connect. Therefore, according to this embodiment, it is possible to provide a semiconductor device that can be integrated without impairing reliability.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the first embodiment, the case where the long side direction of the opening 46a is the longitudinal direction of the gate wiring 16a and the long side direction of the opening 46b is the longitudinal direction of the gate wiring 16b has been described as an example. It is not limited to this. For example, the long side direction of the opening 46a may be set to the longitudinal direction of the gate wiring 16a, and the long side direction of the opening 46b may be set to a direction perpendicular to the longitudinal direction of the gate wiring 16b. In this case, the opening 46 b may contact the void 53, but the opening 46 a does not contact the void 53. Therefore, also in this case, the contact layer 48a and the contact layer 48b are not electrically short-circuited via the void 53. Further, the long side direction of the opening 46b may be set as the longitudinal direction of the gate wiring 16b, and the long side direction of the opening 46a may be set in a direction perpendicular to the longitudinal direction of the gate wiring 16a. In this case, the opening 46 a may contact the void 53, but the opening 46 b does not contact the void 53. Therefore, also in this case, the contact layer 48a and the contact layer 48b are not electrically short-circuited via the void 53.

  In the third embodiment, the opening 46k and the opening 46l are arranged in the longitudinal direction of the gate wiring 16a, and the opening 46m and the opening 46n are arranged in the longitudinal direction of the gate wiring 16b. Although described, the present invention is not limited to this. The opening 46k and the opening 46l may be arranged in the longitudinal direction of the gate wiring 16a, and the opening 46m and the opening 46n may be arranged perpendicular to the longitudinal direction of the gate wiring 16b. In this case, the openings 46 m and 46 n may contact the void 53, but the openings 46 k and 46 l do not contact the void 53. Accordingly, also in this case, the contact layers 48k and 48l and the contact layers 48m and 48n are not electrically short-circuited via the void 53. Further, the opening 46k and the opening 46l may be arranged in a direction perpendicular to the longitudinal direction of the gate wiring 16a, and the opening 46m and the opening 46n may be arranged in the same direction as the longitudinal direction of the gate wiring 16b. Good. In this case, the openings 46k and 46l may contact the void 53, but the openings 46m and 46n do not contact the void 53. Accordingly, also in this case, the contact layers 48k and 48l and the contact layers 48m and 48n are not electrically short-circuited via the void 53.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
A straight line formed on the semiconductor substrate via a gate insulating film, including the gate electrode of the first transistor, and electrically connected to the source / drain diffusion layer of the second transistor via the first contact layer A first gate wiring having a shape;
A gate insulating film is formed on the semiconductor substrate, includes a gate electrode of the second transistor, and is electrically connected to a source / drain diffusion layer of the first transistor through a second contact layer. A linear second gate line parallel to the first gate line;
An insulating film formed on the semiconductor substrate so as to cover the first gate wiring and the second gate wiring, the first gate wiring and the source / drain diffusion layer of the second transistor And an insulating film in which a first opening whose long side direction is the longitudinal direction of the first gate wiring is formed;
A semiconductor device comprising: the first contact layer embedded in the first opening.

(Appendix 2)
In the semiconductor device according to attachment 1,
A second opening in which the second gate wiring and the source / drain diffusion layer of the first transistor are exposed in the insulating film, and a long side direction is a longitudinal direction of the second gate wiring. Is further formed,
The second contact layer is formed in a second opening. A semiconductor device, wherein:

(Appendix 3)
In the semiconductor device according to attachment 1 or 2,
The end portion of the first gate wiring is bent away from the second gate wiring;
The semiconductor device, wherein the end portion of the second gate wiring is bent away from the first gate wiring.

(Appendix 4)
A linear first gate wiring formed on a semiconductor substrate via a gate insulating film, including a gate electrode of the first transistor and electrically connected to a source / drain diffusion layer of the second transistor; ,
The first gate wiring formed on the semiconductor substrate via a gate insulating film, including the gate electrode of the second transistor, and electrically connected to the source / drain diffusion layer of the first transistor A linear second gate wiring parallel to
An insulating film formed on the semiconductor substrate so as to cover the first gate wiring and the second gate wiring, the first opening exposing the first gate wiring; and the second An insulating film in which a second opening exposing the source / drain diffusion layer of the transistor is arranged in a longitudinal direction of the first gate wiring;
A first contact layer embedded in the first opening;
A second contact layer embedded in the second opening;
A semiconductor device comprising: a first wiring formed on the insulating film and connecting the first contact layer and the second contact layer.

(Appendix 5)
In the semiconductor device according to attachment 4,
The insulating film includes a third opening that exposes the second gate wiring, and a fourth opening that exposes the source / drain diffusion layer of the first transistor. It is further arranged in the longitudinal direction of the wiring,
A third contact layer embedded in the third opening;
A fourth contact layer embedded in the fourth opening;
A semiconductor device, further comprising: a second wiring formed on the insulating film and connecting the third contact layer and the fourth contact layer.

(Appendix 6)
In the semiconductor device according to any one of appendices 1 to 5,
The first transistor is a first load transistor;
The second transistor is a second load transistor;
The first gate wiring further includes a gate electrode of a first driver transistor,
The second gate wiring further includes a gate electrode of a second driver transistor;
A memory cell having a first inverter including the first load transistor and the first driver transistor; and a second inverter including the second load transistor and the second driver transistor. A semiconductor device characterized by the above.

(Appendix 7)
A linear first gate wiring including a gate electrode of a first transistor; a linear second gate wiring including a gate electrode of a second transistor and parallel to the first gate wiring; Forming a gate insulating film on the substrate;
Forming source / drain diffusion layers on the semiconductor substrate on both sides of the gate electrode,
Forming an insulating film on the semiconductor substrate, on the first gate wiring and the second gate wiring;
The first gate wiring and the source / drain diffusion layer of the second transistor are exposed, and a first opening whose long side direction is the longitudinal direction of the first gate wiring is formed in the insulating film. And a process of
Burying a first contact layer in the first opening. A method for manufacturing a semiconductor device, comprising:

(Appendix 8)
In the method for manufacturing a semiconductor device according to attachment 7,
In the step of forming the first opening in the insulating film, the second gate wiring and the source / drain diffusion layer of the first transistor are exposed, and a long side direction is the second gate wiring. And further forming a second opening that is the longitudinal direction of
The method of manufacturing a semiconductor device, wherein in the step of embedding the first contact layer in the first opening, a second contact layer is further embedded in the second opening.

(Appendix 9)
A linear first gate wiring including a gate electrode of a first transistor; a linear second gate wiring including a gate electrode of a second transistor and parallel to the first gate wiring; Forming a gate insulating film on the substrate;
Forming source / drain diffusion layers on the semiconductor substrate on both sides of the gate electrode,
Forming an insulating film on the semiconductor substrate, on the first gate wiring and the second gate wiring;
A first opening exposing the first gate wiring and a second opening exposing the source / drain diffusion layer of the second transistor are arranged in the longitudinal direction of the first gate wiring. Forming the insulating film so as to
Embedding a first contact layer in the first opening and embedding a second contact layer in the second opening;
Forming a first wiring connecting the first contact layer and the second contact layer on the insulating film. A method of manufacturing a semiconductor device, comprising:

(Appendix 10)
In the method for manufacturing a semiconductor device according to attachment 9,
In the step of forming the first opening and the second opening in the insulating film, a third opening exposing the second gate wiring and the source / drain diffusion of the first transistor A fourth opening exposing the layer is further formed in the insulating film so as to be arranged in a longitudinal direction of the second gate wiring;
In the step of embedding the first contact layer and the second contact layer, a third contact layer is further embedded in the third opening, and a fourth contact layer is further embedded in the fourth opening,
In the step of forming the first wiring, a second wiring for connecting the third contact layer and the fourth contact layer is further formed. A method for manufacturing a semiconductor device, comprising:

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 11a-11d ... Element area | region 12 ... Element isolation region 14 ... Gate insulating film 16a-16d ... Gate wiring 18 ... Side wall insulating film 19 ... Concave part 20, 22, 24, 26, 28, 30, 32, 34 36, 38 ... Source / drain diffusion layer 40 ... Insulating film 42 ... Insulating film 44 ... Interlayer insulating films 46a-46p ... Openings 48a-48p ... Contact layer 50 ... Wiring 52 ... Silicide film, source / drain electrodes 53 ... 54a, 54b ... Inverter 56 ... Flip-flop circuit 58 ... Memory cell 110 ... Semiconductor substrate 111a-111d ... Element region 112 ... Element isolation region 114 ... Gate insulating film 116a-116d ... Gate wiring 118 ... Side wall insulating films 120, 122, 124, 126, 128, 130, 132, 134, 136, 138 ... source Drain diffusion layer 140 ... insulating film 142 ... insulating film 144 ... interlayer insulating films 146a to 146j ... openings 148a to 148j ... contact layer 152 ... silicide film, source / drain electrodes 153 ... pots L1, L2 ... load transistors D1, D2 ... Driver transistors T1, T2 ... Transfer transistors

Claims (5)

A straight line formed on the semiconductor substrate via a gate insulating film, including the gate electrode of the first transistor, and electrically connected to the source / drain diffusion layer of the second transistor via the first contact layer A first gate wiring having a shape;
A gate insulating film is formed on the semiconductor substrate, includes a gate electrode of the second transistor, and is electrically connected to a source / drain diffusion layer of the first transistor through a second contact layer. A linear second gate line parallel to the first gate line;
An insulating film formed on the semiconductor substrate so as to cover the first gate wiring and the second gate wiring, the first gate wiring and the source / drain diffusion layer of the second transistor And an insulating film in which a first opening whose long side direction is the longitudinal direction of the first gate wiring is formed;
A semiconductor device comprising: the first contact layer embedded in the first opening. The semiconductor device according to claim 1,
The end portion of the first gate wiring is bent away from the second gate wiring;
The semiconductor device, wherein the end portion of the second gate wiring is bent away from the first gate wiring. A linear first gate wiring formed on a semiconductor substrate via a gate insulating film, including a gate electrode of the first transistor and electrically connected to a source / drain diffusion layer of the second transistor; ,
The first gate wiring formed on the semiconductor substrate via a gate insulating film, including the gate electrode of the second transistor, and electrically connected to the source / drain diffusion layer of the first transistor A linear second gate wiring parallel to
An insulating film formed on the semiconductor substrate so as to cover the first gate wiring and the second gate wiring, the first opening exposing the first gate wiring; and the second An insulating film in which a second opening exposing the source / drain diffusion layer of the transistor is arranged in a longitudinal direction of the first gate wiring;
A first contact layer embedded in the first opening;
A second contact layer embedded in the second opening;
A semiconductor device comprising: a first wiring formed on the insulating film and connecting the first contact layer and the second contact layer. A linear first gate wiring including a gate electrode of a first transistor; a linear second gate wiring including a gate electrode of a second transistor and parallel to the first gate wiring; Forming a gate insulating film on the substrate;
Forming source / drain diffusion layers on the semiconductor substrate on both sides of the gate electrode,
Forming an insulating film on the semiconductor substrate, on the first gate wiring and the second gate wiring;
The first gate wiring and the source / drain diffusion layer of the second transistor are exposed, and a first opening whose long side direction is the longitudinal direction of the first gate wiring is formed in the insulating film. And a process of
Burying a first contact layer in the first opening. A method for manufacturing a semiconductor device, comprising: A linear first gate wiring including a gate electrode of a first transistor; a linear second gate wiring including a gate electrode of a second transistor and parallel to the first gate wiring; Forming a gate insulating film on the substrate;
Forming source / drain diffusion layers on the semiconductor substrate on both sides of the gate electrode,
Forming an insulating film on the semiconductor substrate, on the first gate wiring and the second gate wiring;
A first opening exposing the first gate wiring and a second opening exposing the source / drain diffusion layer of the second transistor are arranged in the longitudinal direction of the first gate wiring. Forming the insulating film so as to
Embedding a first contact layer in the first opening and embedding a second contact layer in the second opening;
Forming a first wiring connecting the first contact layer and the second contact layer on the insulating film. A method of manufacturing a semiconductor device, comprising:

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