JP2011171916A - Flip-flop circuit and latch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flip-flop circuit and a latch circuit capable of reducing current consumption accompanying a level change of a clock signal.
In a flip-flop circuit including a master latch 1 and a slave latch 2, the master latch 1 includes a PMOS transistor to which a clock signal CK is input between two OR-NAND composite gates connected to each other. The P15 and the NMOS transistor N15 are shared, and the slave latch 2 shares the PMOS transistor P25 and the NMOS transistor N25 to which the clock signal CK is input between the two AND-NOR type composite gates that are connected to each other.
[Selection] Figure 1

Description

  The present invention relates to a flip-flop circuit and a latch circuit.

  Since the flip-flop circuit and the latch circuit are basic circuits constituting the sequential circuit, many flip-flop circuits and latch circuits are used in the semiconductor integrated circuit. Therefore, if the number of gates for forming the flip-flop circuit or the latch circuit can be reduced, the effect of reducing the number of gates of the semiconductor integrated circuit is great. When the number of gates of the semiconductor integrated circuit is reduced, the current consumption of the semiconductor integrated circuit can be reduced.

  Therefore, conventionally, a flip-flop circuit has been proposed in which the number of gates is reduced by sharing a part of the feedback circuit that constitutes each latch between the master latch and the slave latch that constitute the flip-flop circuit. (For example, refer to Patent Document 1).

  By the way, the current consumption during the operation of the CMOS flip-flop circuit is mainly the charge / discharge current of the gate capacitance and drain capacitance of the MOS transistor constituting the circuit. This charge / discharge current depends on the frequency of the input clock and the rate of change of the input data.

  In general, in a logic LSI, the rate at which data input to a flip-flop circuit changes every clock cycle is often about 10% to 30%. Therefore, the average frequency of the input data is about 5% to 15% of the clock frequency. That is, the average frequency of the input data is generally much lower than the clock frequency. As a result, the ratio of current consumed in the flip-flop circuit is increased as the charge / discharge current of the MOS transistor to which the clock is input.

  Therefore, when reducing the number of gates of the flip-flop circuit, reducing the number of MOS transistors to which a clock is input has a greater effect of reducing current consumption than reducing the number of transistors in the data circuit.

  From this point of view, the above-described proposed method for reducing the number of gates in the flip-flop circuit is a method for reducing the number of gates in the data system circuit, and the number of MOS transistors to which a clock is input is not reduced. Therefore, the above-described proposed flip-flop circuit has a problem that the reduction in the number of gates has little effect on the reduction in current consumption of the entire semiconductor integrated circuit.

JP-A-7-135449 (page 3-4, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-flop circuit and a latch circuit that can reduce current consumption associated with a level change of a clock signal.

  According to one embodiment of the present invention, a first gate circuit to which a data signal and a clock signal are input and a second gate circuit to which an inverted signal of the data signal and the clock signal are input are connected to each other. A master latch configured as described above, a third gate circuit to which a normal output signal and a clock signal of the master latch are input, and a fourth gate circuit to which an inverted output signal of the master latch and the clock signal are input A slave latch configured to be connected to each other, the first gate circuit and the second gate circuit share a transistor to which the clock signal is input, and the third gate A flip-flop circuit in which a transistor to which the clock signal is input is shared between the circuit and the fourth gate circuit It is provided.

  According to another aspect of the present invention, a first gate circuit to which a data signal and a clock signal are input, an inverted signal of its own output signal, and a second gate circuit to which the clock signal is input Are connected to each other, a third gate circuit to which a normal output signal and a clock signal of the master latch are input, and an inverted output signal and the clock signal of the master latch are input to a fourth gate circuit. A slave latch configured to be connected to each other, and the first gate circuit and the second gate circuit share a transistor to which the clock signal is input, A flip-flop having a transistor to which the clock signal is input is shared between the third gate circuit and the fourth gate circuit. -Up circuit is provided.

  According to still another aspect of the present invention, a first gate circuit to which a data signal and a clock signal are input, a second gate circuit to which an inverted signal of the data signal and the clock signal are input, Are connected to each other, and a transistor to which the clock signal is input is shared between the first gate circuit and the second gate circuit.

  According to still another aspect of the present invention, a first gate circuit to which a data signal and a clock signal are input, and a second gate circuit to which an inverted signal of its own output signal and the clock signal are input Are connected to each other and a transistor to which the clock signal is input is shared between the first gate circuit and the second gate circuit.

  According to the present invention, it is possible to reduce the current consumption accompanying the level change of the clock signal.

1 is a transistor level circuit diagram showing an example of the configuration of a flip-flop circuit according to Embodiment 1 of the present invention; FIG. 2 is a circuit diagram of a logic gate level of the flip-flop circuit of FIG. 1. FIG. 3 is an explanatory diagram of transistor sharing in a latch circuit used for a master latch of the flip-flop circuit according to the first embodiment. FIG. 3 is an explanatory diagram of transistor sharing in a latch circuit used for a slave latch of the flip-flop circuit according to the first embodiment. FIG. 6 is a circuit diagram of a logic gate level showing an example of the configuration of a flip-flop circuit according to Embodiment 2 of the present invention. FIG. 6 is a transistor level circuit diagram of the flip-flop circuit of FIG. 5. FIG. 6 is a transistor level circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a third embodiment of the present invention. FIG. 6 is a transistor level circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a fourth embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  FIG. 1 is a transistor level circuit diagram showing an example of the configuration of the flip-flop circuit according to the first embodiment of the present invention, and here, an example when configured as a CMOS circuit is shown. FIG. 2 is a circuit diagram of the logic gate level.

  The flip-flop circuit of the present embodiment is a D-type flip-flop circuit composed of a master latch 1 and a slave latch 2.

  The master latch 1 includes PMOS transistors P11 and P12 connected in parallel, PMOS transistors P13 and P14 connected in parallel, a PMOS transistor P15 connected in common to the source terminal of the PMOS transistor P12 and the source terminal of the PMOS transistor P14, NMOS transistors N11 and N12 connected in series to the drain terminal of the PMOS transistor P12, NMOS transistors N13 and N14 connected in series to the drain terminal of the PMOS transistor P14, and between the drain terminal of the NMOS transistor N12 and the drain terminal of the NMOS transistor N14 And an NMOS transistor N15 connected to.

  The data signal D is input to the gate terminal of the PMOS transistor P14 and the gate terminal of the NMOS transistor N14, and the data signal D is inverted by the inverter IV1 to the gate terminal of the PMOS transistor P12 and the gate terminal of the NMOS transistor N12. A data signal DN is input.

  The output signal A output from the drain terminal of the PMOS transistor P12 is input to the gate terminal of the PMOS transistor P13 and the NMOS transistor N13, and the gate terminal of the PMOS transistor P11 and the gate terminal of the NMOS transistor N11 are input to the gate terminal of the PMOS transistor P13. The output signal B output from the drain terminal of the PMOS transistor P14 is input.

  The clock signal CK is input to the gate terminal of the PMOS transistor P15 and the gate terminal of the NMOS transistor N15.

  When the clock signal CK is at a low level, the master latch 1 outputs an output signal A having the same polarity as that of the data signal D and an output signal B having the opposite polarity, and the output signal A while the clock signal CK is at a high level. And the level of the output signal B is held.

  The slave latch 2 includes PMOS transistors P21 and P22 connected in series, PMOS transistors P23 and P24 connected in series, a PMOS transistor P25 connected between the drain terminal of the PMOS transistor P21 and the drain terminal of the PMOS transistor P23, NMOS transistors N21 and N22 connected in parallel to the drain terminal of the PMOS transistor P22, NMOS transistors N23 and N24 connected in parallel to the drain terminal of the PMOS transistor P24, the source terminal of the NMOS transistor N21, and the source of the NMOS transistor N23 And an NMOS transistor N25 connected in common to the terminals.

  The output signal A of the master latch 1 is input to the gate terminal of the PMOS transistor P23 and the gate terminal of the NMOS transistor N23, and the output signal B of the master latch 1 is input to the gate terminal of the PMOS transistor P21 and the gate terminal of the NMOS transistor N21. Is done.

  The output signal F output from the drain terminal of the PMOS transistor P22 is input to the gate terminal of the PMOS transistor P24 and the gate terminal of the NMOS transistor N24, and the gate terminal of the PMOS transistor P22 and the gate terminal of the NMOS transistor N22 are input to the gate terminal. The output signal E output from the drain terminal of the PMOS transistor P24 is input.

  The clock signal CK is input to the gate terminal of the PMOS transistor P25 and the gate terminal of the NMOS transistor N25.

  The slave latch 2 outputs the output signal F having the same polarity as the output signal A of the master latch 1 and the output signal E having the opposite polarity in synchronization with the rising edge of the clock signal CK. While the clock signal CK is at a low level, the output signal E And the level of the output signal F is held.

  A signal obtained by inverting the output signal E of the slave latch 2 by the inverter INV2 is output as the output signal Q of the flip-flop.

  When the flip-flop circuit of the present embodiment is expressed by a logic gate circuit, as shown in FIG. 2, the master latch 1 is composed of OR-NAND type composite gates OND11 and OND12, and the slave latch 2 is ANDed. A NOR type composite gate ANR21 and an ANR22 crossover circuit are used.

  In the master latch 1, the inverted data signal DN and the clock signal CK are input to the OR gate of the composite gate OND11, and the data signal D and the clock signal CK are input to the OR gate of the composite gate OND12. The output signal A of the composite gate OND11 is input to the NAND gate of the composite gate OND12, and the output signal B of the composite gate OND12 is input to the NAND gate of the composite gate OND11.

  In the slave latch 2, the output signal A and the clock signal CK of the composite gate OND11 are input to the AND gate of the composite gate ANR21, and the output signal B and the clock signal CK of the composite gate OND12 are input to the AND gate of the composite gate ANR22. The output signal E of the composite gate ANR21 is input to the NOR gate of the composite gate ANR22, and the output signal F of the composite gate ANR22 is input to the NOR gate of the composite gate ANR21.

  In general, when a latch circuit having an OR-NAND type composite gate stack structure used for the master latch 1 is designed as a CMOS circuit, a circuit configuration as shown in FIG.

  In the case of the general latch circuit configuration shown in FIG. 3A, the composite gate ANR21 and the composite gate ANR22 are formed by individually combining PMOS transistors and NMOS transistors in a complementary manner.

  In the circuit configuration of FIG. 3A, the clock signal CK is input to the PMOS transistor P15A and NMOS transistor N15A of the composite gate ANR21 and to the PMOS transistor P15B and NMOS transistor N15B of the composite gate ANR22.

  Here, attention is focused on the PMOS transistor P15A and the PMOS transistor P15B. The PMOS transistor P15A and the PMOS transistor P15B are both turned on when the clock signal CK is at a low level, the PMOS transistor P15A supplies the high potential voltage VDD to the PMOS transistor P12, and the PMOS transistor P15B is the high potential voltage to the PMOS transistor P14. Supply VDD.

  The inverted data signal DN and the data signal D are input to the PMOS transistor P12 and the PMOS transistor P14, respectively. Therefore, the PMOS transistor P12 and the PMOS transistor P14 do not conduct at the same time.

  Therefore, the functions of the PMOS transistor P15A and the PMOS transistor P15B can be integrated into one PMOS transistor.

  Therefore, as shown in FIG. 3B, in this embodiment, the PMOS transistor P15 is shared by the composite gate ANR21 and the composite gate ANR22. When the clock signal CK is at a low level, the PMOS transistor P15 conducts and supplies the high potential voltage VDD to the PMOS transistor P12 and the PMOS transistor P14.

  Similarly, the aggregation of the NMOS transistor N15A and the NMOS transistor N15B will be considered. The NMOS transistor N15A and the NMOS transistor N15B are both turned on when the clock signal CK is at a high level, the NMOS transistor N15A supplies the low potential voltage VSS to the NMOS transistor N11, and the NMOS transistor N15B receives the low potential voltage to the NMOS transistor N13. Supply VSS.

  Here, paying attention to the NMOS transistor N12 and the NMOS transistor N14, the inverted data signal DN is input to the gate terminal of the NMOS transistor N12, and the data signal D is input to the gate terminal of the NMOS transistor N14. Since the inverted data signal DN and the data signal D have opposite signal polarities, one of the NMOS transistor N12 and the NMOS transistor N14 is always turned on and transmits the low potential voltage VSS to its drain terminal.

  Therefore, as shown in FIG. 3B, in this embodiment, an NMOS transistor N15 for connecting the drain terminal of the NMOS transistor N12 and the drain terminal of the NMOS transistor N14 is provided, and the clock signal CK is supplied to the gate terminal of the NMOS transistor N15. To be entered. That is, the NMOS transistor N15 is shared by the composite gate ANR21 and the composite gate ANR22.

  When the clock signal CK is at a high level, the NMOS transistor N15 conducts and supplies the low potential voltage VSS to either the NMOS transistor N11 or the NMOS transistor N13 via either the NMOS transistor N12 or the NMOS transistor N14. can do.

  Similarly, in the latch circuit of the AND-NOR type composite gate stacking configuration used for the slave latch 2, the commonality of the transistor to which the clock signal CK is input is shared with the configuration of the general CMOS circuit. It can be performed.

  FIG. 4 shows how transistors are shared in a latch circuit having a AND-NOR type composite gate stacking structure.

  In this case, the technique used on the PMOS transistor side in FIG. 3 is applied to sharing on the NMOS transistor side, and the technique used on the NMOS transistor side in FIG. 3 is applied to sharing on the PMOS transistor side.

  That is, in contrast to the PMOS transistor P25A and the PMOS transistor P25B in the configuration of the general latch circuit shown in FIG. 4A, in the latch circuit of this embodiment shown in FIG. 4B, the drain terminal of the PMOS transistor P21 A PMOS transistor P25 that connects the drain terminal of the PMOS transistor P23 is provided.

  When the clock signal CK is at a low level, the PMOS transistor P25 conducts, and the high potential voltage VDD is supplied to either the PMOS transistor P22 or the PMOS transistor P24 via either the PMOS transistor P21 or the PMOS transistor P23. To do.

  Further, in contrast to the NMOS transistor N25A and the NMOS transistor N25B in the configuration of the general latch circuit shown in FIG. 4A, in the latch circuit of this embodiment shown in FIG. 4B, the source terminal of the NMOS transistor N21 An NMOS transistor N25 connected in common to the source terminal of the NMOS transistor N23 is provided.

  When the clock signal CK is at a high level, the NMOS transistor N25 conducts and supplies the low potential voltage VSS to the NMOS transistor N21 and the NMOS transistor N23.

  According to this embodiment, the number of MOS transistors to which a clock signal is input can be reduced as compared with a latch circuit having a general configuration. Thereby, in the latch circuit and the flip-flop circuit of this embodiment, the current consumed by the change in the level of the clock signal can be reduced.

  In the first embodiment, an example in which different types of composite gates are used for the master latch 1 and the slave latch 2 has been described. On the other hand, this embodiment shows an example of a flip-flop circuit in which the master latch 1 and the slave latch 2 are composed of the same type of composite gate.

  FIG. 5 is a logic gate level circuit diagram showing an example of the configuration of the flip-flop circuit according to the second embodiment of the present invention.

  In this embodiment, both the master latch 1A and the slave latch 2 are composed of AND-NOR type composite gates. Since the slave latch 2 has the same configuration as that of the first embodiment, detailed description thereof is omitted here.

  Master latch 1A is configured by AND-NOR type composite gates ANR11 and ANR12 that are connected to each other and inverter IV11 connected to the output of composite gate ANR12.

  The clock signal CK and the output signal A of the composite gate ANR12 are input to the AND gate of the composite gate ANR11, and the data signal D is input to the NOR gate of the composite gate ANR11.

  The clock signal CK and the output signal C of the inverter IV11 that is an inverted signal of the output signal A are input to the AND gate of the composite gate ANR12, and the output signal B of the composite gate ANR11 is input to the NOR gate of the composite gate ANR12. Is entered.

  Similarly to the master latch 1, the master latch 1A outputs a signal having the opposite polarity to the data signal D as the output signal B when the clock signal CK is at a low level, and outputs the signal having the same polarity as the data signal D as the output signal A. Output as. Since the output signal C of the inverter IV11 is an inverted signal of the output signal A, a signal having a polarity opposite to that of the data signal D is output when the clock signal CK is at a low level. Further, while the clock signal CK is at a high level, the levels of the output signal A, the output signal B, and the output signal C are maintained.

  Master latch 1 </ b> A outputs output signal A and output signal C to slave latch 2.

  In the slave latch 2, the output signal A of the master latch 1A is input to the AND gate of the composite gate ANR21, and the output signal C of the master latch 1A is input to the AND gate of the composite gate ANR22.

  FIG. 6 is a transistor level circuit diagram when the flip-flop circuit of this embodiment is configured as a CMOS circuit.

  In the circuit shown in FIG. 6, in the master latch 1A, the composite gates ANR11 and ANR12 are composed of PMOS transistors P111 to P115 and NMOS transistors N111 to N115, and the inverter IV11 is composed of a PMOS transistor P116 and an NMOS transistor N116.

  The composite gates ANR11 and ANR12 have the same circuit configuration as that of the slave latch 2, and share the PMOS transistor P115 and the NMOS transistor N115.

  The PMOS transistor P115 conducts when the clock signal CK is at a low level, and supplies the high potential voltage VDD to either the PMOS transistor P112 or the PMOS transistor P114 via either the PMOS transistor P111 or the PMOS transistor P113. To do.

  On the other hand, the NMOS transistor N115 becomes conductive when the clock signal CK is at a high level, and supplies the low potential voltage VSS to the NMOS transistor N111 and the NMOS transistor N113.

  According to this embodiment, the master latch and slave latch of the flip-flop circuit can be configured using the same type of composite gate. Further, the MOS transistors to which the clock signal is input can be shared between the composite gates of the respective latch circuits, and the current consumed by the change in the level of the clock signal can be reduced.

  In the second embodiment, the master latch 1A and the slave latch 2 are composed of the same type of composite gate. Therefore, as can be seen from the transistor level circuit diagram of FIG. 6, the master latch 1A and the slave latch 2 have the same circuit configuration and the same function. Therefore, in this embodiment, an example of a flip-flop circuit in which the circuit is shared between the master latch and the slave latch is shown.

  FIG. 7 is a transistor level circuit diagram showing an example of the configuration of the flip-flop circuit according to the third embodiment of the present invention.

  The master latch 1B of the present embodiment deletes the part constituted by the PMOS transistors P111, P113, P115 from the circuit of the master latch 1A shown in FIG. 6, and the PMOS transistors P21, P23, P25 of the slave latch 2 are deleted in the deleted part. The circuit comprised by these is connected.

  That is, in the present embodiment, the circuit constituted by the PMOS transistors P21, P23, and P25 is shared by the slave latch 2 and the master latch 1B.

  As shown in FIG. 7, the source terminal of the PMOS transistor P112 of the master latch 1B is connected to the connection point between the drain terminal of the PMOS transistor P21 and one end of the PMOS transistor P25, and the source terminal of the PMOS transistor P114 of the master latch 1B is connected to the PMOS transistor. It is connected to the connection point between the drain terminal of P23 and the other end of the PMOS transistor P25.

  With this connection, when the clock signal CK is at a low level, the PMOS transistor P25 is turned on, and the PMOS transistor P112 of the master latch 1B is supplied similarly to the supply of the high potential voltage VDD to the PMOS transistor P22 and the PMOS transistor P24 of the slave latch 2. The high potential voltage VDD is supplied to either the PMOS transistor P114 or the PMOS transistor P114 via either the PMOS transistor P21 or the PMOS transistor P23.

  According to this embodiment, the number of MOS transistors to which a clock signal is input can be further reduced by sharing the circuit between the master latch and the slave latch. Thereby, the current consumed by the change in the level of the clock signal can be further reduced.

  In the third embodiment, an example in which a circuit constituted by the PMOS transistors P21, P23, and P25 is shared by the master latch 1B and the slave latch 2 is shown. By sharing the circuit, the number of transistors used can be reduced, and current consumption can be reduced.

  However, by sharing the circuit, there is an aspect in which the load of the circuit configured by the PMOS transistors P21, P23, and P25 increases. In particular, since the PMOS transistor P25 operates as a pass transistor, the operation speed decreases greatly as the load increases. In particular, the influence is large in low voltage operation.

  Therefore, in this embodiment, an example of a flip-flop circuit capable of preventing performance degradation at a low voltage is shown.

  FIG. 8 is a transistor level circuit diagram showing an example of the configuration of the flip-flop circuit according to the fourth embodiment of the present invention.

  The slave latch 2A of the present embodiment is provided with PMOS transistors P25A and P25B that supply a high voltage to the source terminal instead of the PMOS transistor P25 of the slave latch 2 shown in FIG. 7, and the drain terminal of the PMOS transistor P25A is provided. This is connected to the source terminal of the PMOS transistor P22, and the drain terminal of the PMOS transistor P25B is connected to the source terminal of the PMOS transistor P24. Clock signal CK is input to the gate terminals of PMOS transistors P25A and P25B.

  In this embodiment, the PMOS transistors P25A and P25B are shared with the master latch 1B, the drain terminal of the PMOS transistor P25A is connected to the source terminal of the PMOS transistor P112, and the drain terminal of the PMOS transistor P25B is connected to the source terminal of the PMOS transistor P114. Is done.

  With this connection, when the clock signal CK is at a low level, the PMOS transistor P25A is turned on, a high voltage is supplied to the PMOS transistor P22 and the PMOS transistor P112, and the PMOS transistor P25B is turned on, so that the PMOS transistor P24 and the PMOS transistor are turned on. A high voltage is supplied to the transistor P114.

  That is, in this embodiment, the PMOS transistors P25A and P25B directly supply the high-level voltage to the PMOS transistors P22, P112, P24, and P114 without passing through the pass transistor. As a result, the number of transistors to which the clock signal CK is input is increased by one as compared with the third embodiment, but it is possible to prevent performance degradation in low voltage operation.

  According to such a present embodiment, it is possible to prevent a decrease in performance in a low voltage operation while reducing a current consumed by a change in the level of the clock signal.

  Note that the type of the composite gate used for the flip-flop circuit and the latch circuit is not limited to those shown in the above embodiments. For example, the configurations of the master latch 1 and the slave latch 2 of the first embodiment may be interchanged so that the master latch 1 is configured with an AND-NOR type composite gate, and the slave latch 2 is configured with an OR-NAND type composite gate.

1, 1A, 1B Master latch 2, 2A Slave latch IV1, IV2, IV11 Inverter OND11, OND12 OR-NAND type composite gate ANR11, ANR12, ANR21, ANR22 AND-NOR type composite gates P11-P15, P15A, P15B, P21-P25 , P25A, P25B,
P111-P116 PMOS transistors N11-N15, N15A, N15B, N21-N25,
N111 to N116 NMOS transistors

Claims (5)

A master latch configured by connecting a first gate circuit to which a data signal and a clock signal are input and a second gate circuit to which an inverted signal of the data signal and the clock signal are input;
A third gate circuit to which the normal output signal of the master latch and the clock signal are input and a fourth gate circuit to which the inverted output signal of the master latch and the clock signal are input are connected to each other. And a slave latch
The first gate circuit and the second gate circuit share a transistor to which the clock signal is input, and the third gate circuit and the fourth gate circuit share the clock. A flip-flop circuit characterized by sharing a transistor to which a signal is input. A master latch configured by stakingly connecting a first gate circuit to which a data signal and a clock signal are input and an inverted signal of its own output signal and a second gate circuit to which the clock signal is input;
A third gate circuit to which the normal output signal of the master latch and the clock signal are input and a fourth gate circuit to which the inverted output signal of the master latch and the clock signal are input are connected to each other. And a slave latch
The first gate circuit and the second gate circuit share a transistor to which the clock signal is input, and the third gate circuit and the fourth gate circuit share the clock. A flip-flop circuit characterized by sharing a transistor to which a signal is input. The logic gate configuration of the first to fourth gate circuits is the same,
3. The flip-flop circuit according to claim 2, wherein a transistor to which the clock signal is input is further shared between the master latch and the slave latch. A first gate circuit to which a data signal and a clock signal are input and a second gate circuit to which an inverted signal of the data signal and the clock signal are input are connected to each other;
A latch circuit, wherein the transistor to which the clock signal is input is shared between the first gate circuit and the second gate circuit. A first gate circuit to which a data signal and a clock signal are input and a second gate circuit to which an inverted signal of the output signal and the clock signal are input are connected to each other;
A latch circuit, wherein the transistor to which the clock signal is input is shared between the first gate circuit and the second gate circuit.

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