JP2011171900A - Electromagnetic band gap structure element and printed circuit substrate - Google Patents

Abstract

【Task】
Provided is an EBG structure and a substrate that can easily control the band gap characteristics of a desired frequency band with a small and thin EBG structure.
[Solution]
The unit structure of the EBG shown in one embodiment of the present invention includes a first conductor 101 formed in the AA ′ plane and a second conductor (102.1 formed in a plane different from the AA ′ plane. 102.2) and the third conductor (103.1, 103.2) connecting the first conductor 101 and the adjacent second conductor (102.1, 102.2) in series; Since the chip capacitor 104 connected to the first conductor 101 and the conductive layer 105 connected to the chip capacitor 104 are provided, the capacitance C of the EBG structure can be easily adjusted.
[Selection] Figure 1

Description

  The present invention relates to a printed circuit board, and more particularly to an electromagnetic bandgap structure (EBG) that removes electromagnetic waves in a specific frequency band that propagates on the printed circuit board.

  2. Description of the Related Art In recent years, research and development of electronic devices and mobile communication devices with built-in antennas and tuners that receive video signals have been promoted to be small and thin for convenience of installation and carrying. In these electronic devices, a plurality of electronic circuits such as analog circuits, digital circuits such as LSIs and memories are mounted on the same printed circuit board in order to realize various functions. The plurality of electronic circuits on the printed circuit board have different operating frequencies, and electromagnetic interference occurs between the circuits due to unnecessary electromagnetic radiation generated from the plurality of electronic circuits. Since electromagnetic interference propagates to the signal input unit as noise and interferes with signal reception in the reception frequency band, measures to suppress noise propagation are required.

  Therefore, as one of noise countermeasure methods related to unnecessary electromagnetic radiation, a countermeasure by an electromagnetic bandgap structure (EBG: electromagnetic bandgap hereinafter referred to as “EBG structure”) is attracting attention. The EBG structure is a structure for obtaining a characteristic (band gap characteristic) for suppressing propagation of electromagnetic waves and noise currents in a specific frequency band by forming a dielectric or conductor as a two-dimensional or three-dimensional periodic structure. Since it can be applied to a conventional substrate design without using new materials and processes to prevent noise, it is considered promising as a low-cost shielding method.

  Further, it is known that the EBG structure has a high impedance in the frequency band of a resonance circuit composed of an inductance L and a capacitance C, so that a band gap characteristic proportional to the reciprocal of L and C can be obtained. That is, in order to obtain a band gap characteristic in a low frequency band necessary for recent digital equipment, it is required to set the inductance L and the capacitance C to be high.

  For example, Patent Document 1 discloses an EBG structure in which a wiring shape having a current path straddling two layers is periodically formed. In order to obtain a band gap characteristic in a low frequency band, the wiring path is formed so as to straddle two layers, thereby increasing the shielding path and increasing the values of the inductance L and the capacitance C.

JP 2009-44151 A

Shawn D. Rogers, “Electromagnetic-Bandgap Layers for Broad-Band Suppression of TEM Modes in Power Planes,” IEEE TRANS. ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 8, AUG. 2005

  However, in order to obtain the band gap characteristics in the low frequency band (10 MHz to 1 GHz) using the above-described conventional technology, it is necessary to set higher inductance L and capacitance C values. Therefore, it is necessary to extend the length of the conductor formed in a direction perpendicular to the substrate, and to increase the area of the conductor formed in the substrate direction in order to obtain a high capacitance C value. Become. As a result, the problem that the EBG structure becomes large is inherent. Thus, there is a trade-off relationship between the reduction in bandwidth and the reduction in size of the EBG structure.

  Further, in order to obtain the band gap characteristics of a desired frequency band using the above-described conventional technology, it is necessary to change the shape of the EBG structure itself and change the stacking process, and the design can be easily changed. It has the problem of impossible.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an EBG structure capable of easily controlling the band gap characteristics of a desired frequency band with a structure that can be reduced in size and thickness. It is to provide a substrate.

  An EBG structure element according to the present invention includes a first conductor, a plurality of second conductors formed on a plane different from the plane on which the first conductor is formed, the first conductor, A third conductor that connects the adjacent second conductors in series and a conductive layer that is connected to a ground layer are provided, and the first conductor and the conductive layer are connected via a capacitor. It is characterized by that.

  According to said structure, the capacitance of the capacitor | condenser provided in the conductor can be increased / decreased easily and there exists an effect that a desired band gap characteristic can be acquired with a small structure.

  The conductive layer is preferably formed on a plane close to the first conductor.

  In the above configuration, a relatively short wiring or a direct connection can be made to the connection between the first conductor and the capacitor and the connection between the capacitor and the conductive layer, and the fixed values of the inductance L and the capacitance C due to the new wiring. A great increase can be prevented. For this reason, by changing the value of the capacitor C, the band gap characteristic can be easily controlled.

  The conductive layer is preferably formed in the same layer as the first conductor, and the conductive layer preferably forms a clearance hole so as to accommodate the third conductor.

  In the above configuration, the first conductor and the capacitor, and the capacitor and the conductive layer can be connected at the top of the multilayer substrate, and the capacitor can be easily replaced. For this reason, there is an additional effect that it is possible to cope with various design changes.

  A chip capacitor having a terminal is provided as the capacitor, and at least a width of the conductive pattern in a connection portion between the chip capacitor and the first conductor is equal to or less than a width of a terminal of the chip capacitor. It is preferable to arrange so that.

  In the above configuration, the noise current propagating through the first conductor can be reliably propagated to the chip capacitor. For this reason, the noise current can be efficiently removed.

  An EBG structure element according to the present invention includes a plurality of first conductors formed on a first plane, a plurality of second conductors formed on a plane different from the first plane, and the first A third conductor for connecting the second conductor adjacent to the second conductor in series, a conductive layer connected to the ground layer, and connecting the plurality of first conductors and the conductive layer And at least two adjacent chip capacitors have different capacitances.

  According to the above configuration, the arrangement of at least two adjacent capacitors having different capacitances has an effect of having at least two band gap characteristics and suppressing electromagnetic waves in a wide frequency band.

  An EBG structure element according to the present invention includes a first conductor formed on a first plane, a plurality of second conductors formed on a plane different from the first plane, and the first conductor A third conductor that connects the conductor and the second conductor adjacent to each other in series; and a conductive layer that is connected to a ground layer; and the first conductor and the conductive layer include a plurality of conductors. It is characterized by being connected in parallel via a chip capacitor.

  According to said structure, there exists an effect that a wide band gap characteristic can be more effectively controlled by the combination of the chip capacitor electrically connected in parallel.

  The printed circuit board according to the present invention is characterized in that the EBG structure element is formed at least in a part around the electric circuit.

  According to said structure, there exists an effect of suppressing that the noise current which propagates a printed circuit board propagates to an electric circuit.

  Since the EBG structure according to the present invention includes the capacitor connected to the first conductor as described above and can easily increase the value of the capacitance C, the EBG structure includes a small and thin structure, and There is an effect of having a band gap characteristic in a low frequency range.

  In addition, since the EBG structure element according to the present invention can adjust the capacitance C of the EBG structure simply by exchanging capacitors having different capacitances C, it is easy without changing the stacking process for forming the EBG structure. There is an effect that the design can be changed.

1 represents a first embodiment of the present invention and shows a cross-sectional view of an EBG structure. (A), (b) represents the 1st Embodiment of this invention, respectively, and is the top view on the AA 'line and BB' line of the EBG structure shown by FIG. (A)-(d) relates to the EBG element according to the present invention, and is a detailed plan view of the capacitor shown in FIG. 2, (e), (f) relates to the EBG element according to the present invention, It is a top view of the capacitor which has arranged the 3 terminal chip capacitor to the capacitor. FIG. 2 is a diagram representing the first embodiment of the present invention and is an equivalent circuit diagram of the EBG structure shown in FIG. 1. It represents the first embodiment of the present invention and is a simulation model diagram of an EBG structure. It is a figure which shows the periodic characteristic of the EBG structure analyzed based on the simulation model shown by FIG. It is a figure which shows the band gap characteristic of the EBG structure analyzed by arrange | positioning the chip capacitor from which a capacitance differs based on the simulation model shown by FIG. FIG. 3 shows a second embodiment of the present invention and shows a cross-sectional view of an EBG structure. It is a figure showing the simulation result of the 2nd Embodiment of this invention. FIG. 4 shows a third embodiment of the present invention and shows a cross-sectional view of an EBG structure. (A), (b) represents the 3rd Embodiment of this invention, respectively, and is the top view on the AA 'line of the EBG structure shown by FIG. 10, and the top view on the BB' line. It is a figure showing the simulation result of the 3rd Embodiment of this invention, and is a simulation result figure which has arrange | positioned two chip capacitors which have the same capacitance in one EBG unit structure. It is a figure showing the simulation result of the 3rd Embodiment of this invention, and is a simulation model figure which has arrange | positioned two chip capacitors which have different capacitance in one EBG unit structure. FIG. 9 is a cross-sectional view of a printed circuit board connected to an LSI circuit board on which an EBG structure element is arranged, representing a fourth embodiment of the present invention. FIG. 9 is a cross-sectional view of a printed circuit board on which an EBG structure element is arranged, representing a fourth embodiment of the present invention.

[First Embodiment]
The first embodiment of the present invention will be described with reference to FIGS. 1 to 4 as follows.

  FIG. 1 is a cross-sectional view showing a unit structure of an EBG structure element according to the first embodiment of the present invention. 2A is a plan view showing an AA 'plane of the EBG structure shown in FIG. 1, and FIG. 2B is a plan view showing a BB' plane of the EBG structure shown in FIG.

  The unit structure of the EBG structure shown in FIG. 1 includes a first conductor 101 formed in the AA ′ plane and a second conductor (102.1, 102... Formed in a plane different from the AA ′ plane. 2) and the third conductor (103.1, 103.2) connecting the first conductor 101 and the second conductor (102.1, 102.2) adjacent to each other in series; The chip capacitor 104 connected to the conductor 101 and the conductive layer 105 connected to the chip capacitor 104 are included. Here, the conductive layer 105 is formed as a ground layer around or in the vicinity of the same layer of the first conductor 101.

  Even if the dielectric layer 106 is interposed between the AA ′ plane where the first conductor 101 is formed and the BB ′ plane where the second conductor (102.1, 102.2) is formed. Good.

  Here, the dielectric layer 106 is formed between the AA ′ plane where the first conductor 101 is formed and the BB ′ plane where the second conductor (102.1, 102.2) is formed. In the case, the dielectric layer 106 is formed with a through hole and accommodates a third conductor (103.1, 103.2).

  In addition, the conductive layer 105 is preferably formed in the adjacent layer and the same layer of the first conductor 101. In the case where the conductive layer 105 and the first conductor 101 are formed at a distance, a new conductor needs to be formed as a connection wiring for connecting the conductive layer 105 and the first conductor 101, and the fixed value is set. As a result, an inductance L is generated. For this reason, when setting the lower limit frequency, the dependence on the chip capacitor is reduced, and it becomes difficult to easily control the desired frequency characteristics. For this reason, it is preferable to prevent the generation of the fixed inductance L and the capacitance C by forming the conductive layer 105 in the proximity layer and the same layer of the first conductor 101.

  Further, in the case where the conductive layer 105 and the first conductor 101 are formed in the same layer, a clearance hole 107 is formed in the conductive layer 105 and the first conductor 101 is accommodated.

  In the plan view of the EBG structure shown in FIGS. 2 a and 2 b, a first conductor 101 and a conductive layer 105 are formed around the first conductor 101. Third conductors (103.1, 103.2) are formed at both ends of the first conductor 101. The first conductor 101 and the conductive layer 105 are connected via a chip capacitor 104.

  Here, although the conductor is illustrated in a linear shape in the drawings, it may be formed in any shape including a polygon, a circle, and an ellipse. In the drawings, the second conductors (102.1, 102.2) are formed on the same plane, but may be formed in different layers.

  FIGS. 3A and 3B are plan views showing detailed connection portions of the chip capacitor shown in the plan view of the AA ′ plane of FIG. 2. The first conductor 101 and the conductive layer 105 are connected via a chip capacitor 104, and the width s of the first conductor 101 is larger than the terminal width t of the chip capacitor 105 connected to the first conductor 101. They are arranged to be the same or shorter. For this reason, the noise current flowing through the first conductor 101 is reliably transmitted to the chip capacitor 104, and the noise current can be efficiently removed. For example, when the chip capacitor terminals are arranged as shown in FIG. 3C, the noise current flowing through the first conductor bypasses the chip capacitor terminals and propagates to the adjacent EBG element without being suppressed. For this reason, the width s of the first conductor 101 is preferably arranged to be the same or shorter than the terminal width t of the chip capacitor 104 connected to the first conductor 101.

  Here, the terminal width to which the chip capacitor 104 is connected does not have to be long over the entire range with respect to the width of the first conductor 101. For example, a configuration in which only the width of the connection portion of the chip capacitor 104 is shortened as in the conductive layer 105 in FIG.

  More preferably, a three-terminal chip capacitor is arranged as the chip capacitor as shown in FIG. By disposing a three-terminal chip capacitor, it is possible to form a current path that more reliably transmits noise current to the chip capacitor. In addition, since the three-terminal chip capacitor increases the current path through which the noise current flows to the ground layer, the inductance L as a fixed value can be kept lower, and the band gap characteristics can be easily controlled.

  Here, since the three-terminal capacitor is a chip capacitor called a feedthrough capacitor, the first conductor 101 may be shaped as shown in FIG. The first conductor 101 in FIG. 3F is physically separated, and the two separated first conductors are connected by a feedthrough capacitor. The feedthrough capacitor connected to the first conductor 101 is connected to the conductive layer 105 through a connection wiring. For this reason, since the current path of the noise current is a path that penetrates the feedthrough capacitor, the noise current can be reliably propagated into the chip capacitor.

  The structure of the first embodiment of the present invention has a current path (second conductor 102.1 → third conductor 103.1 → first conductor 101 → third conductor flowing through a periodic conductor). A current path through which the current flows to the conductive layer 105 via the conductor 103.2 → second conductor 102.2 →) and the terminal of the chip capacitor 104 connected to the first conductor 101. Conductor 101 → chip capacitor 104 → conductive layer 105). By periodically arranging the unit structures of the first embodiment of the present invention described above, the band gap characteristics are remarkably exhibited.

FIG. 4 is an equivalent circuit diagram showing the unit structure of the EBG structure according to the first embodiment of the present invention as a circuit model. C ₀ is the capacitance of the current path of the unit structure (second conductor 102.1 → third conductor 103.1 → first conductor 101 → third conductor 103.2 → second conductor 102.2), _{L 0} is the current path of unit structures inductance (expressed as dividing the current path into two _{L 0/2), C 1} is the capacitance held by the chip capacitor, the parasitic inductance _{L 1} is held by the chip capacitor It is.

  The EBG structure according to the first embodiment of the present invention has band gap characteristics by periodically arranging the unit structures, and the following upper limit frequency, lower limit frequency, and resonance frequency can be expressed as mathematical expressions. That is, it can be said that the band gap characteristic of the first embodiment is a characteristic that suppresses electromagnetic waves in a frequency band between the lower limit frequency and the upper limit frequency.

  Here, electromagnetic waves caused by unnecessary electromagnetic radiation generated on the printed circuit board are generated in a complex manner due to interference between a plurality of circuits, and therefore do not have a certain frequency band for each printed circuit board. For this reason, in order to suppress a wide variety of electromagnetic waves, it is necessary to control the upper limit frequency and the lower limit frequency of the EBG structure. However, since the first embodiment of the present invention can replace the chip capacitor 104, It is possible to easily form an EBG structure having a desired band gap characteristic that satisfies the following equation.

Here, in order to perform more precise control of the upper limit frequency and the lower limit frequency, it is necessary to depend on the capacitance C ₁ of the chip capacitor 104 whose value can be changed and the inductance L ₁ . For this reason, in order to prevent the generation of the inductance L and the capacitance C due to the new connection wiring having a fixed value, it is preferable that the conductive layer 105 and the first conductor 101 are arranged close to each other.

  FIG. 5 is a simulation model diagram applied to the simulation analysis of the first embodiment of the present invention. It is possible to periodically arrange the EBG unit structures represented in the first embodiment and to propagate signals in the arrangement direction.

FIG. 6 is a graph obtained by analyzing the periodic characteristics of the unit structure of the EBG according to the first embodiment of the present invention based on the simulation model shown in FIG. The comparison is shown when one to five EBG unit structures are periodically arranged with the frequency (GHz) on the X axis and the attenuation (db) on the Y axis. In the simulation, the following values were applied as the capacitance and reactance shown in the equivalent circuit of FIG. C ₀ = 10 pF, L ₀ = 1.4 n, C ₁ = 0.1 μF, L ₁ = 0.45 nH.

  Referring to FIG. 6, it can be confirmed that the absolute value of the attenuation amount increases as the number of periods of the unit structure increases.

  FIG. 7 is a graph obtained by analyzing the band gap characteristics in the case where chip capacitors having different capacitances C are arranged in the EBG structure according to the first embodiment of the present invention based on the simulation model shown in FIG. This shows the change in band gap characteristics when five unit structures of EBG are arranged and the capacitance C of the chip capacitor is changed from 1000 p to 0.1 μF. As the capacitance C of the capacitor is increased, the low frequency side Indicates that the lower limit frequency is shifted.

  From the above, it can be confirmed that desired band gap characteristics can be obtained by changing the capacitance C of the chip capacitor provided in the first embodiment of the present invention.

[Second Embodiment]
A second embodiment of the present invention will be described with reference to FIG.

  FIG. 8 is a sectional view showing a unit structure of an EBG structure according to the second embodiment of the present invention. The unit structure of the EBG structure shown in FIG. 8 is formed on a first conductor (101.1, 101.2) formed on the first plane AA ′ plane and on a plane different from the AA ′ plane. The second conductor (102.1, 102.2, 102.3) and the second conductor (102.1, 102.2) adjacent to the first conductor (101.1, 101.2). , 102.3) in series with the third conductor (103.1, 103.2) and the chip capacitor (104.101.2) connected with the first conductor (101.1, 101.2). 1, 104.2) and a conductive layer 105 connected to the chip capacitors (104.1, 104.2). Here, the capacitance of the chip capacitor (104.1) arranged adjacent to the capacitance of the chip capacitor (104.2) is arranged differently. The conductive layer 105 is formed as a ground layer around or in the vicinity of the same layer of the first conductor (101.1, 101.2).

  Also, the AA ′ plane on which the first conductor (101.1, 101.2) is formed and the BB ′ plane on which the second conductor (102.1, 102.2, 102.3) is formed, A dielectric layer 109 may be interposed therebetween. Here, the AA ′ plane on which the first conductor (101.1, 101.2) is formed and the BB ′ plane on which the second conductor (102.1, 102.2, 102.3) is formed. When the dielectric layer 106 is formed between the first and second dielectric layers 106, through holes are formed in the dielectric layer 106 and the third conductors (103.1, 103.2) are accommodated.

  Here, in the second embodiment, since it may be considered that two EBG unit structures of the first embodiment are arranged adjacent to each other, detailed description is omitted, but the shape and size of the conductor are omitted. In addition, the layers to be arranged may be arbitrarily different from each other. In the drawings, the second conductors (102.1, 102.2, 102.3) are formed on the same plane, but may be formed in different layers. Further, since the formation of the conductive layer 105 and the dielectric layer 106 is the same as that of the first embodiment, the detailed description is omitted, but the conductive layer may have a multi-layer structure as the adjacent conductors are formed. Needless to say.

  Here, since it is the same as that of the first embodiment, a detailed description of the first conductor (101.1, 101.2) and the conductive layer 105 connected via the chip capacitor is omitted. 3 (a) to 3 (f) may be arranged so that the width of the first conductor (101.1, 101.2) is equal to or smaller than the terminal width of the chip capacitor at the connection portion of the chip capacitor. It is preferable to arrange in.

  FIG. 9 is a diagram showing the result of a simulation comparing the band gap characteristics of the second embodiment and the first embodiment of the present invention. Here, the simulation model used in FIG. 9 is the same as the simulation model used in FIG. 5, and the simulation was performed by arranging five unit structures of EBG. In the simulation of the first embodiment, five chip capacitors having a capacitance C value of 0.1 μF are arranged. In the simulation of the second embodiment, three chip capacitors having a capacitance C value of 0.1 μF and two chip capacitors having a capacitance C value of 100 pF were alternately arranged. That is, the chip capacitors of the EBG structure element showing the second embodiment are arranged in the order of 0.1 μF, 100 pF, 0.1 μF, 100 pF, and 0.1 μF.

  Referring to FIG. 9, it can be confirmed that the upper limit frequency is shifted to the low frequency band in the simulation model of the second embodiment in which the chip capacitors of 0.1 μF and 100 pF are arranged adjacent to each other. Moreover, the shift of the lower limit frequency of 1st Embodiment and 2nd Embodiment was not seen.

  That is, the EBG structure of the second embodiment has a band gap characteristic due to the unit structure of the EBG including the first chip capacitor and a band gap characteristic due to the unit structure of the EBG including the second chip capacitor. There is an effect that electromagnetic waves can be suppressed.

  Here, in the second embodiment, a structure in which two types of chip capacitors having different capacitances C are arranged adjacent to each other is used as an EBG unit structure. However, three or more types of chip capacitors having different capacitances C may be adjacent to each other. The structure arranged in the above may be an EBG unit structure. For example, when capacitors having different capacitances C arranged in the unit structure of EBG are C1, C2, and C3, respectively, a periodic arrangement of C1, C2, C3, C1, C2, C3, C1,. It is good also as a periodic arrangement of C2, C1, C3, C2, C1,.

  In the periodic array, different capacitances C are not necessarily arranged adjacent to each other. That is, a group of EBG structure elements in which at least two EBG unit structures in which the capacitor C1 is disposed are disposed adjacently and two or more EBG unit structures in which the capacitor C2 is disposed are disposed adjacently. A periodic array including a group of EBG structure elements may be used. For example, C1, C1, C1, C2, C2, C2, C1, C1,... Periodic arrangement, C1, C1, C1, C3, C3, C3, C2, C2, C2, C1, C1,. It may be a periodic array.

[Third Embodiment]
The third embodiment of the present invention will be described below with reference to FIGS.

  FIG. 10 is a sectional view showing a unit structure of an EBG structure element according to the third embodiment of the present invention. 11A is a plan view showing an AA ′ plane of the EBG structure shown in FIG. 10, and FIG. 11B is a plan view showing a BB ′ plane of the EBG structure shown in FIG.

  The unit structure of the EBG structure shown in FIG. 10 includes a first conductor 101 formed on the first plane AA ′ plane and a second conductor (102... 102 formed on a plane different from the AA ′ plane. 1, 102.2) and the third conductor (103.1, 103.2) connecting the first conductor 101 and the adjacent second conductor (102.1, 102.2) in series. ), At least two chip capacitors (104.1, 104.2) connected in parallel to the first conductor 101, and a conductive layer 105 connected to the chip capacitors (104.1, 104.2) included.

  Here, the conductive layer 105 is formed as a ground layer around or in the vicinity of the same layer of the first conductor 101.

  Even if the dielectric layer 106 is interposed between the AA ′ plane where the first conductor 101 is formed and the BB ′ plane where the second conductor (102.1, 102.2) is formed. Good.

  Here, the dielectric layer 106 is formed between the AA ′ plane where the first conductor 101 is formed and the BB ′ plane where the second conductor (102.1, 102.2) is formed. In the case, the dielectric layer 106 is formed with a through hole and accommodates a third conductor (103.1, 103.2).

  In addition, the conductive layer 105 is preferably formed in the adjacent layer and the same layer of the first conductor 101. When the conductive layer 105 and the first conductor 101 are formed at a distance from each other, it is necessary to form a new conductor as a connection wiring, and an inductance L is generated as a fixed value. For this reason, when setting the lower limit frequency, the dependence on the chip capacitor is reduced, and it becomes difficult to easily control the desired frequency characteristics. For this reason, by forming the conductive layer 105 in the proximity layer and the same layer of the first conductor 101, generation of a fixed inductance L and capacitance C is prevented.

  Further, in the case where the conductive layer 105 and the first conductor 101 are formed in the same layer, a clearance hole 107 is formed in the conductive layer 105 and the first conductor 101 is accommodated.

  In the plan view of the EBG structure shown in FIGS. 11 a and 11 b, a first conductor 101 and a conductive layer 105 are formed around the first conductor 101. Third conductors (103.1, 103.2) are formed at both ends of the first conductor 101. The first conductor 101 and the conductive layer 105 are connected via a chip capacitor 104.

  Here, although the linear shape is described in the drawings, the conductor may be formed in any shape including a polygon, a circle, and an ellipse. In the drawings, for the sake of explanation, a plurality of second conductors (102.1, 102.2) are formed on the same plane, but may be formed on different layers.

  Here, since it is the same as the description of the first embodiment, detailed description of the first conductor and the conductive layer connected via the chip capacitor is omitted, but each chip capacitor is shown in FIG. It may be arranged in the same manner as in f), and is preferably arranged so that the width of the first conductor 101 is equal to or less than the terminal width of the chip capacitor at the connection portion of the chip capacitor.

  12 and 13 are diagrams showing the results of a simulation comparing the band gap characteristics of the third embodiment and the first embodiment of the present invention.

  FIG. 12 is a diagram of simulation results comparing the band gap characteristics of the third embodiment and the first embodiment in which two chip capacitors having the same capacitor value are arranged in one EBG unit structure. The simulation model of the third embodiment used in FIG. 12 is the same as the simulation model used in FIG. 5, and five unit structures of EBG are arranged. In the simulation of the first embodiment, five chip capacitors having a capacitor value of 0.1 μF were arranged. In the simulation of the third embodiment, two chip capacitors having the same capacitor value of 0.1 μF are connected in parallel to one EBG unit structure, and five unit structures are arranged adjacent to each other.

  The simulation model of the third embodiment used in FIG. 13 is the same as the simulation model used in FIG. 5, and five EBG unit structures are arranged. In the simulation of the first embodiment, five chip capacitors having a value of 0.1 μF of capacitor are arranged as in FIG. In the simulation of the third embodiment, one chip capacitor having a capacitance of 0.1 μF and one chip capacitor having a capacitance of 100 pF are connected in parallel to one EBG unit structure. Five were arranged adjacent to each other.

  Referring to FIG. 12, it can be confirmed that the simulation model in which two capacitors of the same capacitor C are arranged in one unit structure has a higher upper limit frequency.

  Referring to FIG. 13, it can be confirmed that the simulation model using capacitors having different values of the capacitor C in one unit structure not only forms a wider frequency band but also exhibits an anti-resonance frequency. Further, it can be confirmed that the frequency of the pass band depends on the resonance frequency of the chip capacitor 100 pF having a low value of the capacitor C, and the lower limit frequency depends on the value of the chip capacitor of 0.1 μF having a high value of the capacitor C. That is, by changing the value of the capacitor C of the arranged chip capacitor, it is possible to control not only a wider frequency band but also a desired band gap characteristic.

  Since the EBG structure of the third embodiment suppresses a wide variety of electromagnetic waves by combining chip capacitors connected in parallel, a bandgap characteristic having a wider frequency band can be obtained.

[Fourth Embodiment]
The following describes the fourth embodiment of the present invention with reference to FIG. 14 and FIG.

  14 and 15 are cross-sectional views of a printed circuit board on which an EBG structure element according to the first to third embodiments of the present invention is formed.

  In FIG. 14, an LSI circuit board 110 connected by a connection unit 109 is arranged on a printed circuit board 108, and an LSI 111 is installed on the LSI circuit board 110. An EBG structure element 112 is formed around the LSI 111 of the LSI circuit board 110. For this reason, it is possible to suppress the noise current propagating through the printed circuit board from propagating to the LSI.

  In FIG. 15, the LSI 111 is arranged on the printed circuit board 108 via the connection unit 109. An EBG structure element 112 is formed around the LSI 111 of the printed circuit board 108. For this reason, it is possible to suppress the noise current propagating through the printed circuit board from propagating to the LSI.

  Here, the EBG structure elements shown in FIGS. 14 and 15 do not have to be arranged over the entire periphery of the LSI, and may be formed in a part of the periphery of the LSI that can block the path of the noise current. Further, the number of periods of the unit structure of the EBG may be appropriately changed according to the noise current.

  Although FIG. 14 and FIG. 15 show an embodiment in which LSIs are arranged, they may be formed around or part of an electric circuit that needs to suppress electrical noise propagation.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. Embodiments obtained by appropriately combining technical means disclosed in different embodiments respectively. Is also included in the technical scope of the present invention.

  According to the present invention, since the capacitance C of the chip capacitor can be changed regardless of the size of the EBG structure, it can be used for any electronic devices and substrates that generate electromagnetic noise.

101, 101.1, 101.2 First conductor 102.1, 102.2, 102.3 Second conductor 103.1, 103.2 Third conductor
104, 104.1, 104.2 Chip capacitor 105 Conductive layer 106 Dielectric layer 107 Clearance hole 108 Printed circuit board 109 Connection part 110 LSI circuit board 111 LSI
112 EBG structure element

Claims (7)

A first conductor;
A plurality of second conductors formed on a plane different from the plane on which the first conductor is formed;
A third conductor for connecting the first conductor and the adjacent second conductor in series;
A conductive layer connected to the ground layer,
An EBG structure element, wherein the first conductor and the conductive layer are connected via a capacitor.   The EBG structure element according to claim 1, wherein the conductive layer is formed on a plane close to the first conductor.   The said conductive layer is formed in the same layer as the said 1st conductor, The clearance hole is formed in the said conductive layer so that the said 3rd conductor may be accommodated, The Claim 1 characterized by the above-mentioned. EBG structure element.   The capacitor is a chip capacitor having a terminal, and the width of the first conductor at least at the connection portion between the chip capacitor and the first conductor is equal to the width of the terminal of the chip capacitor. The EBG structure element according to claim 2, wherein: A plurality of first conductors formed in a first plane;
A plurality of second conductors formed in a plane different from the first plane;
A third conductor for connecting the first conductor and the adjacent second conductor in series;
A conductive layer connected to the ground layer;
A chip capacitor connecting the plurality of first conductors and the conductive layer;
An EBG structure element, wherein at least two adjacent chip capacitors have different capacitances. A first conductor formed in a first plane;
A plurality of second conductors formed in a plane different from the first plane;
A third conductor for connecting the first conductor and the adjacent second conductor in series;
A conductive layer connected to the ground layer,
An EBG structure element, wherein the first conductor and the conductive layer are connected in parallel via a plurality of chip capacitors. 7. A printed circuit board, wherein the EBG structure element according to claim 1 is formed on at least a part of the periphery of an electric circuit.