JP2011164688A - Cumulative addition circuit - Google Patents

Abstract

The power consumption of a cumulative adder circuit is reduced.
A cumulative addition circuit includes an addition circuit, a counter, and a clock gating control circuit. The adder circuit cumulatively adds predetermined bits of data, and activates a carry signal when a carry occurs. The counter counts up when the carry signal is activated, and outputs the N-bit count value as the upper digit of the cumulative addition result. The counter includes an N-bit register that latches each bit of the count value. A register holding a bit whose value changes in response to activation of the carry signal is an active register. The clock gating control circuit receives the carry signal from the adder circuit and the count value from the counter. When the carry signal is activated, the clock gating control circuit refers to the count value received from the counter, and activates only the clock supply to the activation register and deactivates other clock supplies. .
[Selection] Figure 1

Description

  The present invention relates to a cumulative addition circuit in a semiconductor integrated circuit.

  In a semiconductor integrated circuit, a cumulative addition circuit that cumulatively adds a plurality of digital data may be used.

  For example, in an apparatus that performs image processing such as a digital TV or a disk player, image analysis such as image motion analysis is performed in order to display an image more clearly. In the image analysis, a result obtained by accumulating a plurality of pixel data is used. For example, it is assumed that 8-bit pixel data is cumulatively added 1920 times for an HD size image having 1920 pixels in one horizontal line. In that case, a 19-bit configuration cumulative addition circuit is required. The number of pixels to be processed increases with an increase in image quality, which causes a further increase in power consumption of the cumulative addition circuit.

  Patent Document 1 describes a counter for the purpose of reducing power consumption. In the counter, a clock gating control circuit is interposed between the lower digit counter and the upper digit counter. The low-order digit counter is a ripple counter and counts up the clock. When the count value of the lower digit counter is the upper limit value and carry is to be performed, the clock gating control circuit supplies the clock CLKa to the upper digit counter. The upper digit counter is a synchronous counter, and counts up the clock CLKa supplied in this way.

JP 2008-109563 A

  It is desired to reduce the power consumption of the cumulative addition circuit. According to the technique described in Patent Document 1, the clock CLKa is supplied to all the registers of the upper digit counter when a carry occurs. That is, the clock CLKa is also supplied to a register whose retained data does not change due to up-counting. In this case, the load capacity of the circuit constituting the register consumes power due to the change of the clock CLKa. That is, power consumption increases unnecessarily. Such an increase in power consumption becomes more remarkable as the number of data bits and the cumulative number of additions increase.

  In one aspect of the invention, a cumulative adder circuit is provided. The cumulative addition circuit includes an addition circuit, a counter, and a clock gating control circuit. The adder circuit cumulatively adds data of predetermined bits, outputs a lower digit of the cumulative addition result, and activates a carry signal when a carry occurs. The counter counts up when the carry signal is activated, and outputs a count value of N bits (N is an integer of 2 or more) as an upper digit of the cumulative addition result. The clock gating control circuit controls clock supply to the counter.

  The counter includes an N-bit register that latches each bit of the count value in response to a supplied clock. Of the N-bit count value, a bit whose value changes in response to activation of the carry signal is a change bit. Of the N-bit registers, the register holding the change bit is an active register. The clock supplied to the activation register is the target clock.

  The clock gating control circuit receives the carry signal from the adder circuit and the count value from the counter. When the carry signal is activated, the clock gating control circuit refers to the count value received from the counter to activate only the supply of the target clock and deactivate the other clock supplies.

  According to the present invention, it is possible to reduce the power consumption of the cumulative addition circuit.

FIG. 1 is a block diagram showing a cumulative addition circuit according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of the 11-bit register in the first embodiment of the present invention. FIG. 3 is a truth table of the clock gating control circuit according to the first embodiment of the present invention. FIG. 4 is a circuit diagram showing a configuration example of the clock gating control circuit according to the first embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration example of the clock gate according to the first embodiment of the present invention. FIG. 6 is a timing chart showing an operation example of the cumulative addition circuit according to the first embodiment of the present invention. FIG. 7 is a block diagram showing a cumulative addition circuit according to the second embodiment of the present invention. FIG. 8 is a circuit diagram showing a configuration example of an 11-bit register in the second embodiment of the present invention. FIG. 9 is a truth table of the clock gating control circuit according to the second embodiment of the present invention. FIG. 10 is a circuit diagram showing a configuration example of the clock gating control circuit according to the second embodiment of the present invention.

1. 1. First embodiment 1-1. Configuration FIG. 1 is a block diagram showing a cumulative addition circuit according to a first embodiment of the present invention. The cumulative addition circuit cumulatively adds the input data 111 of predetermined bits and outputs a cumulative addition result. In the following description, it is assumed that the input data 111 is 8-bit data, and the cumulative addition result is represented as 19-bit data A [18: 0]. A [18: 0] represents that A [18], A [17],... A [0] are arranged in the order of the numbers in [].

  As shown in FIG. 1, the cumulative addition circuit according to the present embodiment includes a lower digit addition circuit 61, an upper digit counter 62, and a clock gating control circuit 63. The lower digit addition circuit 61 calculates and outputs 8-bit data A [7: 0], which is the lower digit of the cumulative addition result. On the other hand, the upper digit counter 62 calculates and outputs 11-bit data A [18: 8], which is the upper digit of the cumulative addition result. The clock gating control circuit 63 is connected to the lower digit adding circuit 61 and the upper digit counter 62. The clock gating control circuit 63 controls the clock supply to the upper digit counter 62. Details of each circuit are as follows.

(Lower digit addition circuit 61)
The lower digit addition circuit 61 continuously receives a plurality of input data 111 and cumulatively adds the input data 111. Then, the lower digit addition circuit 61 outputs 8-bit data A [7: 0], which is the lower digit of the cumulative addition result. Further, the lower digit addition circuit 61 is connected to the clock gating control circuit 63 and outputs a carry signal 112 to the clock gating control circuit 63. When a carry from the lower digit occurs, the lower digit addition circuit 61 activates the carry signal 112. In the present embodiment, regarding the carry signal 112, “1 (High)” represents an active state, and “0 (Low)” represents an inactive state.

  More specifically, as shown in FIG. 1, the lower digit addition circuit 61 includes an 8-bit addition circuit 71 and an 8-bit register 72. The 8-bit addition circuit 71 sequentially receives 8-bit input data 111. The 8-bit addition circuit 71 adds each input data 111 and the lower 8-bit data A [7: 0] of the cumulative addition result, and outputs the addition result to the 8-bit register 72. The 8-bit addition circuit 71 activates the carry signal 112 every time a carry occurs.

  The 8-bit register 72 is connected to the output of the 8-bit addition circuit 71. The 8-bit register 72 is supplied with a clock 100 from the outside. In response to the rising edge of the clock 100, the 8-bit register 72 latches the output data from the 8-bit addition circuit 71 as lower 8-bit data A [7: 0]. The lower 8-bit data A [7: 0] is output to the outside and fed back to the 8-bit addition circuit 71.

(Upper digit counter 62)
The upper digit counter 62 performs a count operation and outputs a count value of N bits (N is an integer of 2 or more). More specifically, the initial value of the count value is 0, and the upper digit counter 62 counts up by one each time the carry signal 112 is activated by the lower digit addition circuit 61. Therefore, this N-bit count value becomes the upper digit of the cumulative addition result. In this embodiment, N = 11, and the upper digit counter 62 outputs an 11-bit count value as upper 11-bit data A [18: 8] of the cumulative addition result.

  More specifically, as shown in FIG. 1, the upper digit counter 62 includes an 11-bit addition circuit 81 and an 11-bit register 82. The 11-bit addition circuit 81 receives the upper 11-bit data A [18: 8]. The 11-bit addition circuit 81 generates addition data D [10: 0] by adding “1” to the upper 11-bit data A [18: 8], and the addition data D [10: 0] is 11 Output to the bit register 82.

  The 11-bit register 82 is connected to the output of the 11-bit adder circuit 81. The 11-bit register 82 is supplied with clocks (310 to 320) from the clock gating control circuit 63. In response to the clock supply, the 11-bit register 82 latches the addition data D [10: 0] as the upper 11-bit data A [18: 8]. The upper 11-bit data A [18: 8] is output to the outside and fed back to the 11-bit addition circuit 81. As will be described later, the clock supply from the clock gating control circuit 63 is activated when the above carry signal 112 is activated. Therefore, the upper 11-bit data A [18: 8] is counted up when the carry signal 112 is activated.

  FIG. 2 is a circuit diagram showing a configuration example of the 11-bit register 82 in the present embodiment. The 11-bit register 82 includes 11 registers (first to eleventh registers) that hold the respective bits of the upper 11-bit data A [18: 8]. In the example of FIG. 2, the first to eleventh registers are flip-flops FF0 to FF10. The flip-flops FF0 to FF10 hold and output bits A [8] to A [18] (first to Nth bits) from the lower side to the upper side. More specifically, the respective bits D [0] to D [10] of the addition data D [10: 0] are input to the flip-flops FF0 to FF10. Separate clocks 310 to 320 are supplied to the flip-flops FF0 to FF10 via separate clock wirings. The flip-flops FF0 to FF10 latch and output the latest upper 11-bit data A [18: 8] (that is, the addition data D [10: 0]) in response to the rise of the clocks 310 to 320, respectively. .

(Clock gating control circuit 63)
The clock gating control circuit 63 is connected to the lower digit adding circuit 61 and the upper digit counter 62. The clock gating control circuit 63 receives the clock 100, receives the carry signal 112 from the lower digit addition circuit 61, and further receives the upper 11-bit data A [18: 8] from the upper digit counter 62. The clock gating control circuit 63 controls the supply of the clocks 310 to 320 to the upper digit counter 62 based on the carry signal 112 and the upper 11 bit data A [18: 8].

  More details are as follows. Of the upper 11-bit data A [18: 8], a bit whose value changes in response to the activation of the carry signal 112 is hereinafter referred to as a “change bit”. Of the 11-bit register 82 (flip-flops FF0 to FF10), the register holding the change bit is hereinafter referred to as “active register”. The clock supplied to the active register is hereinafter referred to as “target clock”. When the carry signal 112 is activated, the clock gating control circuit 63 refers to the upper 11-bit data A [18: 8] (count value before counting up) received from the upper digit counter 62. The change bit, active register, and target clock can be recognized. Thereby, the clock gating control circuit 63 can activate only the supply of the target clock to the active register and deactivate the clock supply to the other registers. As a result, the power consumption of the upper digit counter 62 is reduced.

  FIG. 3 shows a correspondence relationship between the carry signal 112, the upper 11-bit data A [18: 8], and the activation / deactivation of the clocks 310 to 320. With respect to the carry signal 112, “1” represents an active state (carry occurrence) and “0” represents an inactive state. For the upper 11-bit data A [18: 8], the leftmost end represents the most significant bit A [18], the rightmost end represents the least significant bit A [8], and “x” is “0” or “1”. Indicates that either is acceptable. Regarding the clocks 310 to 320, “ON” represents activation (supply) and “OFF” represents deactivation (stop).

  As shown in FIG. 3, the ON / OFF pattern of the clocks 310 to 320 is determined depending on the carry signal 112 and the pattern of the upper 11-bit data A [18: 8]. In particular, paying attention to the “least significant 0 bit” in A [18: 8], which has a value of 0 and is located on the lowest side, when the carry signal 112 = “1”, It can be seen that the ON / OFF pattern of the clocks 310 to 320 is determined by the position. That is, in the upper 11-bit data A [18: 8], the bits from the least significant bit A [8] to the least significant 0 bit are the above-described “change bits”. Therefore, it is only necessary to supply the corresponding clock only to the register holding the least significant bit A [8] to the least significant 0 bit.

  Thus, the ON / OFF pattern of the clocks 310 to 320 can be determined based on the position of the least significant 0 bits in the upper 11-bit data A [18: 8]. For this purpose, as shown in FIG. 1, the clock gating control circuit 63 includes a clock gating circuit 91 and a zero position detection circuit 92. The 0 position detection circuit 92 receives the upper 11-bit data A [18: 8] from the upper digit counter 62, and detects the position of the least significant 0 bit in the upper 11-bit data A [18: 8]. Based on the detection result, the clock gating circuit 91 controls the supply of the clocks 310 to 320 according to the correspondence relationship shown in FIG.

  FIG. 4 is a circuit diagram showing a configuration example of the clock gating control circuit 63 in the present embodiment. The clock gating control circuit 63 includes eleven clock gates CG0 to CG10 (first to eleventh clock gates). The clock gates CG0 to CG10 are connected to the flip-flops FF0 to FF10 (first to eleventh registers), respectively, and control the supply of the clocks 310 to 320 to the flip-flops FF0 to FF10.

  Each of the clock gates CG0 to CG10 has a configuration as shown in FIG. Specifically, the clock gate has a latch circuit 51 and an AND gate 52. An input clock CLK1 and an enable signal EN1 are input to the clock gate. The latch circuit 51 passes the enable signal EN1 when the input clock CLK1 is at the L level (“0”), and latches the enable signal EN1 at the rising edge of the input clock CLK1. The output of the latch circuit 51 is an enable signal EN2. The AND gate 52 receives the input clock CLK1 and the enable signal EN2, and outputs a logical product of them as the output clock CLK2.

  The clock gate having such a configuration operates as follows. When the input clock CLK1 is inactivated, that is, when the input clock CLK1 remains “0”, the output clock CLK2 remains “0” and is deactivated. That is, the clock supply is deactivated (cut off). When the enable signal EN1 is inactivated, that is, when the enable signal EN1 is “0”, the enable signal EN2 is also “0”. As a result, the output clock CLK2 remains “0” and remains inactive. That is, the clock supply is deactivated (cut off). On the other hand, when both the input clock CLK1 and the enable signal EN1 are activated, the input clock CLK1 is output as the output clock CLK2. That is, the clock supply is activated.

  Referring to FIG. 4 again, the first clock gate (clock gate CG0) receives the clock 100 as the input clock CLK1 and receives the carry signal 112 as the enable signal EN1. When the parameter i is 2 to N, the i-th clock gate (clock gate CG (i-1)) uses the output clock CLK2 output from the (i-1) -th clock gate as the input clock CLK1. receive. Further, the i-th clock gate receives the (i−1) -th bit among the bits A [8] to A [17] (first to 10th bits) as the enable signal EN1. With such a configuration, the correspondence shown in FIG. 3 is realized.

1-2. Operation Example FIG. 6 is a timing chart showing an operation example of the cumulative addition circuit according to the present embodiment. More specifically, FIG. 6 shows an example in which the count value (upper 11-bit data A [18: 8]) in the upper digit counter 62 increases from the initial value “0” to “8”.

  At the rising edge of clock 100 at time t1, carry signal 112 changes from “0” to “1”. This carry signal 112 is input to clock gate CG0 as enable signal EN1.

  At time t2, the enable signal EN2 of the clock gate CG0 changes from “0” to “1”. As a result, the supply of the clock 310 is activated.

  At time t3, the clock 310 rises. Other clocks are stopped. The flip-flop FF0 latches the addition data D [0] = “1”, and the bit A [8] becomes “1”. That is, the count value A [18: 8] becomes “1”.

  Bit A [8] = “1” is input to the clock gate CG1 as the enable signal EN1, and the activated clock 310 is input as the input clock CLK1. Therefore, at time t4, the enable signal EN2 of the clock gate CG1 changes from “0” to “1”. As a result, the supply of the clock 311 is activated.

  At time t5, the clock 310 and the clock 311 rise. Other clocks are stopped. The flip-flop FF0 latches the addition data D [0] = “0”, and the bit A [8] becomes “0”. The flip-flop FF1 latches the addition data D [1] = “1”, and the bit A [9] becomes “1”. That is, the count value A [18: 8] is “2”.

  Bit A [8] = “0” is input to clock gate CG1 as enable signal EN1. Therefore, at time t6, the enable signal EN2 of the clock gate CG1 changes from “1” to “0”, and the clock 311 is deactivated. At this time, the bit A [9] = “1” is input to the clock gate CG2 as the enable signal EN1, but the clock 312 remains stopped because the input clock 311 has been deactivated.

  At time t7, the clock 310 rises. The flip-flop FF0 latches the addition data D [0] = “1”, and the bit A [8] becomes “1”. That is, the count value A [18: 8] becomes “3”.

  The bit A [8] = “1” is input again to the clock gate CG1 as the enable signal EN1. Accordingly, at time t8, the enable signal EN2 of the clock gate CG1 changes from “0” to “1”. As a result, the supply of the clock 311 is activated again. Since the clock 311 is activated, the supply of the clock 312 by the clock gate CG2 is also activated.

  At time t9, clocks 310, 311 and 312 rise. Other clocks are stopped. The flip-flop FF0 latches the addition data D [0] = “0”, and the bit A [8] becomes “0”. The flip-flop FF1 latches the addition data D [1] = “0”, and the bit A [9] becomes “0”. The flip-flop FF1 latches the addition data D [1] = “1”, and the bit A [10] becomes “1”. That is, the count value A [18: 8] becomes “4”. The same applies thereafter.

1-3. Effect As described above, according to the present embodiment, a necessary clock is supplied only to the active register that holds the change bits in the count value A [18: 8]. On the other hand, the clock supply is deactivated (blocked) for a register whose retained data does not change due to the up-count. Therefore, power consumption is reduced.

  As a comparative example, let us consider a case where all of the clocks 310 to 320 are activated when the carry signal 112 is activated, as in the above-mentioned Patent Document 1 (Japanese Patent Laid-Open No. 2008-109563). During the up-counting of 2048 times, the number of clocks supplied to the 11-bit register 82 of the upper digit counter 62 is 22528 (= 2048 × 11) times. The clock gate in the clock gating control circuit 63 is shared, and the clock 100 is supplied 2048 times to the common clock gate. In the clock gate, a clock is supplied to the two circuits of the latch circuit 51 and the AND gate 52, and the number of clocks is 4096 (= 2048 × 2). Therefore, the total number of clocks is 26624 (= 22528 + 4096) times.

On the other hand, this embodiment is as follows. As can be seen from FIG. 6, the number of clocks 311 is half of the number of clocks 310, and the number of clocks 312 is half of the number of clocks 311. The same applies to other cases, and the number of clocks in a certain stage is half the number of clocks in the preceding stage. Therefore, the number of clocks supplied to the 11-bit register 82 of the upper digit counter 62 during 2048 times (2 ¹¹ times) is 4094 (= 2 ¹¹ +2 ¹⁰ +... +2 ¹ ) times. . Regarding the clock gate control circuit 63, the clock 100 is supplied 2048 times to the clock gate CG0. Clocks 310 to 319 are supplied to the clock gates CG1 to CG10, respectively. Therefore, the number of clocks supplied to the clock gates CG0 to CG11 is 6140 (= 2 ¹¹ +2 ¹¹ +2 ¹⁰ +2 ⁹ +... +2 ² ) times. Within each clock gate, a clock is supplied to two circuits, a latch circuit 51 and an AND gate 52. Therefore, the total number of clocks is 16374 (= 4094 + 6140 × 2) times. This is 62% or less of the comparative example, and the power consumption is reduced accordingly.

2. Second Embodiment FIG. 7 is a block diagram showing a cumulative addition circuit according to a second embodiment of the present invention. As compared with the first embodiment, the clock gating control circuit 63 is replaced with the clock gating control circuit 63B, and the 11-bit register 82 is replaced with the 11-bit register 82B. The clock gating control circuit 63B controls the supply of the clocks 810 to 812 to the 11-bit register 82B. Others are the same as those in the first embodiment, and redundant description is omitted as appropriate.

  FIG. 8 shows a circuit configuration example of the 11-bit register 82B. The 11-bit register 82B includes flip-flops FF0 to FF10 (first to eleventh registers) that hold bits A [8] to A [18] (first to eleventh bits), respectively. In the present embodiment, the flip-flops FF0 to FF10 are divided into M groups (M is an integer of 2 or more and N or less). In the example of FIG. 8, M = 3, the first group includes flip-flops FF0 to FF3, the second group includes flip-flops FF4 to FF7, and the third group includes flip-flops FF8 to FF10.

  Separate clocks 810 to 812 are supplied to each of the first to third groups via separate clock wirings. However, the same clock is commonly supplied to flip-flops in the same group. That is, the clock 810 is supplied to the flip-flops FF0 to FF3 of the first group, the clock 811 is supplied to the flip-flops FF4 to FF7 of the second group, and the clock 812 is supplied to the flip-flops FF8 to FF10 of the third group. Supplied.

  FIG. 9 is the same as FIG. 3 described above, and correspondence between the carry signal 112, the upper 11-bit data A [18: 8], and the activation / deactivation of the clocks 810 to 812 in the present embodiment. Showing the relationship. The clock gating control circuit 63B is configured to realize the correspondence shown in FIG.

  FIG. 10 is a circuit diagram showing a configuration example of the clock gating control circuit 63B in the present embodiment. The clock gating control circuit 63B includes three clock gates CG0 to CG2 (first to third clock gates). The clock gates CG0 to CG2 are connected to the first to third groups, respectively, and control the supply of the clocks 810 to 812 to the first to third groups. Each of the clock gates CG0 to CG2 has the configuration shown in FIG.

  The clock gating control circuit 63B further includes AND gates 93B and 94B. The AND gate 93B outputs a logical product 813 of bits A [8] to A [11] held by the flip-flops FF0 to FF3 belonging to the first group. The AND gate 94B outputs a logical product 814 of bits A [12] to A [15] held by the flip-flops FF4 to FF7 belonging to the second group.

  The first clock gate (clock gate CG0) receives the clock 100 as the input clock CLK1, and receives the carry signal 112 as the enable signal EN1. The second clock gate (clock gate CG1) receives the clock 810 as the input clock CLK1, and receives the logical product 813 output from the AND gate 93B as the enable signal EN1. The third clock gate (clock gate CG2) receives the clock 811 as the input clock CLK1, and receives the logical product 814 output from the AND gate 94B as the enable signal EN1. Generalizing using the parameter j (j is each of 2 to M) is as follows. The jth clock gate (clock gate CG (j-1)) receives the output clock CLK2 output from the (j-1) th clock gate as the input clock CLK1. Further, the j-th clock gate receives the logical product of the respective bits held by the flip-flop belonging to the (j−1) -th group as the enable signal EN1. With such a configuration, the correspondence shown in FIG. 9 is realized.

  According to the second embodiment, as in the case of the first embodiment, it is possible to reduce power consumption. Furthermore, according to the second embodiment, the clocks supplied from the clock gating control circuit 63B to the 11-bit register 82B are collected for each of a plurality of bits. Thereby, the number of clock gates in the clock gating control circuit 63B is reduced as compared with the first embodiment. As a result, the area of the cumulative addition circuit is reduced.

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, and can be appropriately changed by those skilled in the art without departing from the scope of the invention.

61 Lower digit addition circuit 62 Upper digit counter 63 Clock gating control circuit 71 8-bit addition circuit 72 8-bit register 81 11-bit addition circuit 82 11-bit register 91 clock gating circuit 92 0 position detection circuit 100 clock 111 input data 112 digits Raise signal 310-320 clock

Claims (4)

An addition circuit that cumulatively adds data of predetermined bits, outputs a lower digit of the cumulative addition result, and activates a carry signal when a carry occurs;
A counter that counts up when the carry signal is activated and outputs a count value of N bits (N is an integer of 2 or more) as an upper digit of the cumulative addition result;
A clock gating control circuit for controlling clock supply to the counter,
The counter includes an N-bit register that latches each bit of the count value in response to a supplied clock;
Of the N-bit count value, a bit whose value changes in response to the activation of the carry signal is a change bit,
Of the N-bit registers, the register holding the change bit is an active register,
The clock supplied to the active register is a target clock,
The clock gating control circuit receives the carry signal from the adder circuit, and receives the count value from the counter,
When the carry signal is activated, the clock gating control circuit activates only the supply of the target clock by referring to the count value received from the counter and disables the other clock supply. Cumulative adder circuit to be activated. The cumulative addition circuit according to claim 1,
Of the N-bit count value, the bit that is 0 and is located on the lowest side is the lowest 0 bit,
Of the N-bit count value, bits from the least significant bit to the least significant 0 bit are the change bits,
The clock gating control circuit activates only the supply of the target clock by detecting the least significant 0 bit from the count value received from the counter. The cumulative addition circuit according to claim 1,
The N-bit count value includes first to Nth bits from the lower side to the upper side,
The N-bit register includes first to Nth registers for holding the first to Nth bits, respectively.
The clock gating control circuit includes first to Nth clock gates connected to each of the first to Nth registers and controlling clock supply to each of the first to Nth registers,
The first clock gate receives the carry signal as an enable signal and receives an input clock;
The i-th clock gate (i is each of 2 to N) receives the (i-1) -th bit as an enable signal, and uses a clock output from the (i-1) -th clock gate as an input clock. Acceptance,
Each of the first to Nth clock gates activates clock supply when the enable signal and the input clock are activated, and supplies clock when the enable signal or the input clock is deactivated. Deactivate cumulative adder circuit. The cumulative addition circuit according to claim 1,
The N-bit count value includes first to Nth bits from the lower side to the upper side,
The N-bit register includes first to Nth registers for holding the first to Nth bits, respectively.
The first to Nth registers are divided into M groups (M is an integer of 2 to N),
The M groups include first to Mth groups from the lower side to the upper side,
The clock gating control circuit includes first to Mth clock gates connected to each of the first to Mth groups and controlling clock supply to each of the first to Mth groups,
The first clock gate receives the carry signal as an enable signal and receives an input clock;
The j-th clock gate (j is each of 2 to M) receives the logical product of the respective bits held by the register belonging to the (j−1) -th group as an enable signal, and the (j− 1) Receive the clock output from the clock gate as the input clock,
Each of the first to Mth clock gates activates clock supply when the enable signal and the input clock are activated, and supplies clock when the enable signal or the input clock is deactivated. Deactivate cumulative adder circuit.

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