JP2011164212A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device having a proper display quality. <P>SOLUTION: The liquid crystal display device includes a first substrate, including an insulating substrate, a switching element disposed above the insulating substrate, a first electrode electrically connected to the switching element, and a second electrode disposed apart from the first electrode and side by side with the first electrode; a second substrate facing the first substrate; a liquid crystal layer held between the first and second substrates and including liquid crystal molecules; a first alignment film disposed on a surface that is brought into contact with the liquid crystal layer, of the first substrate and aligns the liquid crystal molecules in a direction approximately parallel with the normal direction of the first substrate; and a second alignment film disposed on a surface coming into contact with the liquid crystal layer of the second substrate and subjected to rubbing processing. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device.

  In recent years, flat display devices have been actively developed, and among them, liquid crystal display devices have been applied to various fields by taking advantage of features such as light weight, thinness, and low power consumption.

  For example, according to Patent Document 1, a lower substrate including a counter electrode formed in a unit pixel and a pixel electrode that operates a liquid crystal molecule by generating a fringe field together with the counter electrode, and between the lower substrate and the liquid crystal layer. A horizontal alignment film having a predetermined rubbing axis, a vertical alignment film interposed between the upper substrate and the liquid crystal layer, a polarizing element disposed on the outer surface of the upper substrate and having a predetermined polarization axis, and a lower substrate; A reflective fringe field drive mode liquid crystal display device is disclosed, which includes a reflecting means that is disposed and reflects light incident from above the upper substrate.

JP 2002-229032 A

  An object of the present invention is to provide a liquid crystal display device with good display quality.

According to one aspect of the invention,
An insulating substrate, a switching element disposed above the insulating substrate, a first electrode electrically connected to the switching element, and spaced apart from the first electrode and disposed side by side with the first electrode A first substrate provided with a second electrode; a second substrate facing the first substrate; a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate; A first alignment film disposed on a surface of the first substrate in contact with the liquid crystal layer and aligning the liquid crystal molecules in a direction substantially parallel to a normal direction of the first substrate; and the liquid crystal layer of the second substrate; There is provided a liquid crystal display device comprising: a second alignment film disposed on a contact surface and subjected to a rubbing process.

  According to the present invention, a liquid crystal display device with good display quality can be provided.

FIG. 1 schematically shows a configuration of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel shown in FIG. FIG. 3 is a schematic plan view of the pixel structure of the array substrate shown in FIG. 2 as viewed from the counter substrate side. FIG. 4 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel in which the pixel shown in FIG. 3 is cut along the line AB. FIG. 5 is a plan view schematically showing the alignment state of liquid crystal molecules located in the vicinity of the counter substrate. FIG. 6 is a cross-sectional view of the liquid crystal display panel along the rubbing direction of the second alignment film shown in FIG. FIG. 7 is a plan view schematically showing the alignment state of the liquid crystal molecules in a state where an electric field is formed by the potential difference between the pixel electrode and the counter electrode. FIG. 8 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel of a comparative example. FIG. 9 is a diagram illustrating a comparison result of transmittances when the same voltage is applied to the pixel electrodes in the present embodiment and the comparative example.

  Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device 1 includes an active matrix type liquid crystal display panel LPN, a drive IC chip 2 and a flexible wiring board 3 connected to the liquid crystal display panel LPN, a backlight 4 that illuminates the liquid crystal display panel LPN, and the like. .

  The liquid crystal display panel LPN is held between an array substrate (first substrate) AR, a counter substrate (second substrate) CT arranged to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer (not shown). Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. The active area ACT is composed of a plurality of pixels PX arranged in a matrix of m × n (where m and n are positive integers).

  In the illustrated example, the backlight 4 is disposed on the back side of the array substrate AR. As such a backlight 4, various forms are applicable, and any of those using a light emitting diode (LED) as a light source or a cold cathode tube (CCFL) is applicable. Description of the detailed structure is omitted.

  FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel LPN shown in FIG.

  In the active area ACT, the array substrate AR includes n gate wirings G (G1 to Gn) and n capacitance lines C (C1 to Cn) that extend along the X direction, and a Y direction that intersects the X direction. In each pixel PX, m source wirings S (S1 to Sm) extending along the line, and m × n switching elements SW electrically connected to the gate wiring G and the source wiring S in each pixel PX M × n pixel electrodes (first electrodes) PE each electrically connected to the switching element SW, a common potential counter electrode (second electrode) CE which is a part of the capacitor line C and is separated from the pixel electrode PE. Etc. The storage capacitor Cs is formed between the capacitor line C and the pixel electrode PE. The liquid crystal layer LQ is interposed between the pixel electrode PE and the counter electrode CE.

  Each gate line G is drawn outside the active area ACT and is connected to the first drive circuit GD. Each source line S is drawn outside the active area ACT and connected to the second drive circuit SD. Each capacitance line C is drawn outside the active area ACT and connected to the third drive circuit CD. The first drive circuit GD, the second drive circuit SD, and the third drive circuit CD are formed on, for example, the array substrate AR and connected to the drive IC chip 2.

  In the illustrated example, the drive IC chip 2 is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN. In addition, illustration of a flexible wiring board is abbreviate | omitted and the terminal T for connecting a flexible wiring board is formed in array board | substrate AR. These terminals T are connected to the driving IC chip 2 through various wirings.

  Further, the liquid crystal display panel LPN of the illustrated example includes a pixel electrode PE and a counter electrode CE on the array substrate AR, and mainly uses a horizontal electric field (that is, an electric field substantially parallel to the main surface of the substrate) formed therebetween. In-Plane Switching (IPS) mode for switching liquid crystal molecules contained in the liquid crystal layer LQ is applied.

  Next, the liquid crystal display panel LPN of this embodiment will be described.

  FIG. 3 is a schematic plan view of the structure of the pixel PX in the array substrate AR shown in FIG. 2 as viewed from the counter substrate CT side.

  The gate wiring G extends in the X direction. The source line S extends in the Y direction. The switching element SW is disposed in the vicinity of the intersection of the gate line G and the source line S, and is configured by, for example, a thin film transistor (TFT). The switching element SW includes a semiconductor layer SC. The semiconductor layer SC can be formed of, for example, polysilicon or amorphous silicon, and is formed of polysilicon here.

  The gate electrode WG of the switching element SW is located immediately above the semiconductor layer SC and is electrically connected to the gate wiring G (in the illustrated example, the gate electrode WG is formed integrally with the gate wiring G. ) The source electrode WS of the switching element SW is electrically connected to the source line S (in the illustrated example, the source electrode WS is formed integrally with the source line S). The drain electrode WD of the switching element SW is electrically connected to the pixel electrode PE.

  The capacitance line C extends in the X direction. That is, the capacitor line C is disposed in each pixel PX, intersects the source line S, and is common to each pixel PX adjacent in the X direction. The capacitance line C includes a counter electrode CE formed corresponding to each pixel PX. In the illustrated example, the capacitor line C is common to a plurality of pixels PX for one row arranged in the X direction between two gate lines G adjacent in the Y direction. In the illustrated example, the capacitance line C includes a counter electrode CE formed in a comb shape in each pixel PX. Here, the counter electrode CE includes two comb electrodes E1 and E2 extending in the Y direction per pixel.

  The pixel electrode PE of each pixel PX is disposed above the capacitance line C. A part of the pixel electrode PE is opposed to the capacitor line C through an interlayer insulating film (not shown) to form a storage capacitor Cs. Such pixel electrodes PE are each connected to the drain electrode WD of the switching element SW. In the present embodiment to which the IPS mode is applied, unlike the fringe field switching (FFS) mode, the pixel electrode PE has a substantially constant distance from the counter electrode CE in the XY plane parallel to the main surface of the array substrate AR. They are arranged side by side. In the illustrated example, the pixel electrode PE is formed in a substantially I-shape extending in the Y direction. That is, the pixel electrode PE extends substantially in parallel with the comb-tooth electrodes E1 and E2 constituting the counter electrode CE, and is located between these two comb-tooth electrodes E1 and E2.

  FIG. 4 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel LPN obtained by cutting the pixel PX shown in FIG. 3 along the line AB.

  That is, the array substrate AR is formed by using an insulating substrate 20 having a light transmission property such as a glass plate. The array substrate AR includes a switching element SW on the inner surface of the insulating substrate 20 (that is, the surface facing the liquid crystal layer LQ). The switching element SW shown here is a top-gate thin film transistor. The semiconductor layer SC is disposed on the insulating substrate 20. Such a semiconductor layer SC is covered with the gate insulating film 21. The gate insulating film 21 is also disposed on the insulating substrate 20.

  The gate electrode WG of the switching element SW is disposed on the gate insulating film 21 and is located immediately above the semiconductor layer SC. Such a gate electrode WG is covered with a first interlayer insulating film 22. The first interlayer insulating film 22 is also disposed on the gate insulating film 21. The gate insulating film 21 and the first interlayer insulating film 22 are formed of an inorganic material such as silicon nitride (SiN).

  The source electrode WS and the drain electrode WD of the switching element SW are disposed on the first interlayer insulating film 22. The source electrode WS and the drain electrode WD are in contact with the semiconductor layer SC through contact holes that penetrate the gate insulating film 21 and the first interlayer insulating film 22. The gate electrode WG, the source electrode WS, and the drain electrode WD are formed of a conductive material such as molybdenum, aluminum, tungsten, or titanium.

  The source electrode WS and the drain electrode WD are covered with the organic insulating film 23. The organic insulating film 23 is also disposed on the first interlayer insulating film 22. The organic insulating film 23 is formed of various organic materials such as an ultraviolet curable resin and a thermosetting resin.

  The counter electrode CE included in the capacitor line C is disposed on the organic insulating film 23. Such a counter electrode CE is covered with a second interlayer insulating film 24. The second interlayer insulating film 24 is also disposed on the organic insulating film 23.

  The pixel electrode PE is disposed on the second interlayer insulating film 24. That is, the pixel electrode PE and the counter electrode CE are arranged in different layers with the second interlayer insulating film 24 interposed therebetween. The pixel electrode PE does not overlap with the counter electrode CE and the normal direction Z of the array substrate AR, but is arranged side by side with the counter electrode CE.

  The pixel electrode PE is connected to the drain electrode WD through a contact hole that penetrates the organic insulating film 23 and the second interlayer insulating film 24. Both the capacitor line C or the counter electrode CE and the pixel electrode PE are formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode PE is covered with the first alignment film 25. The first alignment film 25 is disposed on the surface in contact with the liquid crystal layer LQ of the array substrate AR.

  On the other hand, the counter substrate CT is formed using an insulating substrate 30 having optical transparency such as a glass plate. The counter substrate CT includes a black matrix 31 and a color filter 32 that partition each pixel PX on the inner surface of the insulating substrate 30 (that is, the surface facing the liquid crystal layer LQ).

  The black matrix 31 is arranged on the insulating substrate 30 so as to face the gate wiring G and the source wiring S provided on the array substrate AR, and further to the wiring section such as the switching element SW. The black matrix 31 is formed of a light shielding metal material such as a resin material colored in black or chromium (Cr), for example.

  The color filter 32 is disposed on the insulating substrate 30 and is formed of a resin material colored in a plurality of different colors, for example, three primary colors such as red, blue, and green. The resin material colored red is arranged corresponding to the red pixel. Similarly, the resin material colored blue is arranged corresponding to the blue pixel, and the resin material colored green corresponds to the green pixel. Are arranged.

  In the liquid crystal mode using the lateral electric field as described above, it is desirable that the surface of the counter substrate CT that is in contact with the liquid crystal layer LQ is flat, and the counter substrate CT further includes irregularities on the surfaces of the black matrix 31 and the color filter 32. An overcoat layer 33 for flattening is provided. Such an overcoat layer 33 is formed of various organic materials such as an ultraviolet curable resin and a thermosetting resin. In the illustrated example, the overcoat layer 33 is disposed on the black matrix 31 and the color filter 32. The overcoat layer 33 is covered with the second alignment film 34. The second alignment film 34 is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film 25 and the second alignment film 34 face each other. At this time, a spacer (not shown) (for example, a columnar spacer integrally formed on one substrate with a resin material) is disposed between the array substrate AR and the counter substrate CT, thereby forming a predetermined gap. Is done. The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a predetermined gap is formed.

  The liquid crystal layer LQ is composed of a P-type liquid crystal composition sealed in a gap formed between the first alignment film 25 of the array substrate AR and the second alignment film 34 of the counter substrate CT.

  A polarizing plate PL1 is disposed on one outer surface of the liquid crystal display panel LPN, that is, the outer surface of the insulating substrate 20 constituting the array substrate AR. A polarizing plate PL2 is disposed on the other outer surface of the liquid crystal display panel LPN, that is, the outer surface of the insulating substrate 30 constituting the counter substrate CT.

  The first alignment film 25 interposed between the array substrate AR and the liquid crystal layer LQ is a vertical alignment film that aligns liquid crystal molecules (not shown) constituting the liquid crystal layer LQ in a direction substantially parallel to the normal direction Z of the array substrate AR. And no rubbing process is required. On the other hand, the second alignment film 34 interposed between the counter substrate CT and the liquid crystal layer LQ is rubbed so that liquid crystal molecules (not shown) are substantially the same as the main surface (surface parallel to the XY plane) of the counter substrate CT. It is a horizontal alignment film that is aligned in the rubbing direction in a parallel plane.

  FIG. 5 is a diagram schematically showing the alignment state of the liquid crystal molecules LM located in the vicinity of the counter substrate CT.

  The rubbing direction RB of the second alignment film 34 is not parallel to both the X direction and the Y direction. For example, the angle formed by the rubbing direction RB and the Y direction is about 10 °. The liquid crystal molecules LM in the vicinity of the counter substrate CT are oriented so that the major axis L is substantially parallel to the XY plane and faces the direction substantially parallel to the rubbing direction RB. Although not shown, the pixel electrode PE and the counter electrode CE on the array substrate side extend in the Y direction.

  FIG. 6 is a cross-sectional view of the liquid crystal display panel LPN along the rubbing direction RB of the second alignment film 34 shown in FIG. In FIG. 6, only the main parts necessary for explanation are shown.

  The first alignment film 25 interposed between the array substrate AR and the liquid crystal layer LQ is a vertical alignment film, and the second alignment film 34 interposed between the counter substrate CT and the liquid crystal layer LQ is a horizontal alignment film. For this reason, the liquid crystal molecules LM included in the liquid crystal layer LQ are hybrid-aligned. That is, the liquid crystal molecules LM1 positioned in the vicinity of the array substrate AR are aligned (homeotropic alignment) in a direction substantially parallel to the normal direction Z, and the liquid crystal molecules LM2 positioned in the vicinity of the counter substrate CT are aligned in the rubbing direction RB. Oriented (homogeneous orientation). In addition, the alignment state of the liquid crystal molecules LM continuously changes between the array substrate AR and the counter substrate CT.

  In the present embodiment, in order to realize the normally black mode, the first absorption axis A1 of the first polarizing plate PL1 disposed on the outer surface of the array substrate AR is the second polarizing plate disposed on the outer surface of the counter substrate CT. It is orthogonal to the second absorption axis A2 of PL2. In addition, the second absorption axis A <b> 2 is substantially parallel to the rubbing direction RB of the second alignment film 34.

  FIG. 7 is a diagram schematically showing the alignment state of the liquid crystal molecules LM in a state where the electric field EF is formed by the potential difference between the pixel electrode PE and the counter electrode CE. FIG. 7 shows the alignment state of the liquid crystal molecules LM when the liquid crystal display panel LPN is viewed from the counter substrate side.

  That is, when a potential different from the common potential is applied to the pixel electrode PE, an electric field EF is formed between the pixel electrode PE and the counter electrode CE. The electric field EF is formed along a direction substantially parallel to the XY plane and substantially parallel to the X direction.

  At this time, the liquid crystal molecules LM1 in the vicinity of the array substrate are aligned so that the long axis L is substantially parallel to the electric field EF. That is, the liquid crystal molecules LM1 are substantially parallel to the XY plane and aligned in a direction substantially parallel to the X direction.

  Further, the liquid crystal molecules LM2 in the vicinity of the counter substrate are hardly affected by the electric field EF formed in the vicinity of the array substrate, and thus are in an alignment state substantially equivalent to a state in which no electric field is formed. That is, the liquid crystal molecules LM2 are aligned so that the major axis L is substantially parallel to the XY plane and faces the direction substantially parallel to the rubbing direction (direction slightly inclined with respect to the Y direction) RB. Yes.

  In addition, the alignment state of the liquid crystal molecules LM continuously changes between the array substrate AR and the counter substrate CT. That is, the liquid crystal molecules LM are twisted between the array substrate AR and the counter substrate CT.

  In the liquid crystal display device having the above-described configuration, when there is no electric field, the liquid crystal molecules LM are aligned substantially vertically in the vicinity of the array substrate, and are approximately horizontally aligned in the rubbing direction RB in the vicinity of the counter substrate. Hybrid orientation between them. In such a state, the backlight light from the backlight passes through the first polarizing plate PL1, then passes through the liquid crystal display panel LPN, and is absorbed by the second polarizing plate PL2 (black display).

  On the other hand, when an electric field is formed between the pixel electrode PE and the counter electrode CE, it is oriented substantially horizontally in the direction of the electric field in the vicinity of the array substrate, and is oriented substantially horizontally in the rubbing direction RB in the vicinity of the counter substrate. Twist orientation is performed between the substrate and the counter substrate. When the orientation direction of the liquid crystal molecules LM changes in the vicinity of the array substrate, the modulation factor for the light transmitted through the liquid crystal layer LQ changes. Therefore, part of the backlight light emitted from the backlight and transmitted through the liquid crystal display panel LPN is transmitted through the second polarizing plate PL2 (white display). That is, the transmittance of the liquid crystal display panel LPN changes depending on the magnitude of the electric field EF. In the IPS mode, the backlight is selectively transmitted in this way to display an image.

  According to the configuration of the present embodiment, the rubbing process for the first alignment film 25 disposed on the surface of the array substrate AR that is in contact with the liquid crystal layer LQ is unnecessary. For this reason, it is possible to prevent defects caused by the rubbing treatment, for example, generation of scratches and streak-like rubbing unevenness caused by the rubbing member being in strong contact with the first alignment film 25 locally.

  In particular, the array substrate AR includes various wirings such as source wirings S and gate wirings G arranged so as to intersect with each other, switching elements SW, pixel electrodes PE, counter electrodes CE, and the like arranged in each pixel PX. Unevenness is easily formed on the side in contact with the liquid crystal layer LQ. The first alignment film 25 is arranged along the unevenness of the array substrate AR, and it is difficult to perform a uniform rubbing process with a rubbing member. In the normally black mode, a spot where a scratch or rubbing unevenness is formed in the first alignment film 25 becomes a bright line or a bright spot during black display, leading to a decrease in contrast.

  For this reason, according to the present embodiment, in which the rubbing process of the first alignment film 25 is not necessary, the problem caused by the rubbing process is eliminated, so that it is possible to prevent a decrease in contrast due to bright lines or bright spots. Display quality can be obtained. Further, according to the present embodiment, it is possible to improve the manufacturing yield.

  The second alignment film 34 is a horizontal alignment film and requires a rubbing process. In the present embodiment, the counter substrate CT includes an overcoat layer 33 serving as a base of the second alignment film 34. . That is, since the second alignment film 34 is disposed on the overcoat layer 33 having a smooth surface, scratches and rubbing unevenness due to the rubbing member are unlikely to occur. Therefore, the occurrence of defects due to the rubbing process in the second alignment film 34 is suppressed.

  Next, the transmittance was compared between the present embodiment to which the IPS mode was applied and the comparative example to which the FFS mode was applied.

  Note that both the present embodiment and the comparative example include a transmissive liquid crystal display panel LPN in which a vertical alignment film is applied as the first alignment film 25 and a horizontal alignment film is applied as the second alignment film 34, and the first polarizing plate PL1. This is a normally black mode in which the first absorption axis A1 and the second absorption axis A2 of the second polarizing plate PL2 are orthogonal to each other.

  The liquid crystal display panel LPN of this embodiment has the above-described IPS mode configuration, in which the counter electrode CE on the organic insulating film 23 and the pixel electrode PE on the second interlayer insulating film 24 are arranged side by side. It is. The liquid crystal display panel LPN of the comparative example has an FFS mode configuration as shown in FIG. 8, and has a counter electrode CE disposed on the organic insulating film 23 and a second interlayer insulating film 24 covering the counter electrode CE. The pixel electrode PE is provided with a slit SL positioned immediately above the counter electrode CE. The other configuration of the liquid crystal display panel LPN of the comparative example is the same as that of the present embodiment shown in FIG.

  FIG. 9 is a diagram illustrating a comparison result of transmittance when the same voltage is applied to the pixel electrode PE in the present embodiment and the comparative example. The horizontal axis in the figure is the applied voltage (V) of the pixel electrode PE, and the vertical axis in the figure is the transmittance.

  As shown in the figure, according to this embodiment to which the IPS mode is applied, it was confirmed that a maximum transmittance higher than that of the comparative example to which the FFS mode was applied was obtained, and that a larger modulation rate than that of the comparative example was obtained. .

  In the comparative example in which the liquid crystal molecules are switched by the fringe electric field formed between the pixel electrode PE and the counter electrode CE, the electric field necessary for switching the liquid crystal molecules is weak in the vicinity of the boundary of the fringe electric field. Therefore, it does not contribute to the display and causes a decrease in transmittance. That is, in the configuration of the comparative example, the modulation rate is significantly reduced.

  On the other hand, in the present embodiment in which liquid crystal molecules are switched by a lateral electric field formed between the pixel electrode PE and the counter electrode CE, there are fewer unmodulated regions than in the comparative example, and a decrease in transmittance can be suppressed. Therefore, according to the configuration of the present embodiment, a large modulation rate can be obtained.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 4 ... Back light LPN ... Liquid crystal display panel AR ... Array substrate CT ... Opposite substrate LQ ... Liquid crystal layer LM ... Liquid crystal molecule ACT ... Active area PX ... Pixel PE ... Pixel electrode C ... Capacitance line CE ... Counter electrode 25 ... 1st alignment film 34 ... 2nd alignment film PL1 ... 1st polarizing plate PL2 ... 2nd polarizing plate

Claims (4)

An insulating substrate, a switching element disposed above the insulating substrate, a first electrode electrically connected to the switching element, and spaced apart from the first electrode and disposed side by side with the first electrode A first substrate comprising a second electrode;
A second substrate facing the first substrate;
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A first alignment film disposed on a surface of the first substrate in contact with the liquid crystal layer and aligning the liquid crystal molecules in a direction substantially parallel to a normal direction of the first substrate;
A second alignment film disposed on a surface of the second substrate that contacts the liquid crystal layer and subjected to a rubbing process;
A liquid crystal display device comprising:   A first polarizing plate disposed on the outer surface of the first substrate; a second polarizing plate disposed on the outer surface of the second substrate; and a backlight disposed on the back side of the first substrate. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is provided.   The first absorption axis of the first polarizing plate is orthogonal to the second absorption axis of the second polarizing plate, and the second absorption axis is substantially parallel to the rubbing direction of the second alignment film. The liquid crystal display device according to claim 2.   The liquid crystal display device according to claim 1, wherein the second substrate includes an overcoat layer serving as a base of the second alignment film.

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