JP2011151241A - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device capable of relieving thermal stress generated in an isolation trench is provided.
A step of forming an oxide film 30 on the surface of an SOI layer 20 is provided. A step of forming a nitride film 40 on the surface of the oxide film 30 is provided. A step of removing the SOI layer 20, the oxide film 30, and the nitride film 40 in the isolation trench region R2 to form a first trench 52 is provided. The SOI layer 20 exposed on the side wall of the first trench 52 is thermally oxidized to change the first trench 52 to the narrow first trench 52a and the inside is filled with the thermal oxide film 60. Forming a region R2. A step of removing the nitride film 40 is provided. The step of closing the opening of the narrow first trench 52a with the amorphous silicon layer by forming the amorphous silicon layer 70 is provided. There is a step of transforming the amorphous silicon layer 70 into a thermal oxide film 71 by thermal oxidation.
[Selection] Figure 7

Description

  The present application relates to a method of manufacturing a semiconductor device in which an element region and an element isolation region are formed on a semiconductor substrate.

  As a method of performing element isolation by a trench, a method of forming a trench (groove) in a silicon substrate and embedding a silicon oxide film in the formed trench is known. Patent Document 1 discloses a method of filling the inside of a trench with a thermally oxidized silicon film by thermally oxidizing the sidewall of the trench after the trench is formed.

JP-A-9-205137

  Silicon oxide has a smaller coefficient of thermal expansion than silicon. For this reason, in the structure in which the inside of the trench is embedded with a silicon oxide film, it is distorted on the silicon side that is easily elastically deformed due to thermal stress generated due to the difference in thermal expansion coefficient during the heat treatment process in the semiconductor device formation process. May occur. When strain is generated in silicon, crystal defects such as dislocations are generated in the silicon to alleviate the strain, and there is a possibility that device characteristics are deteriorated.

  The technology of the present application has been developed to solve the above problems. That is, the present application provides a technique capable of relieving thermal stress generated in an isolation trench portion in a method for manufacturing a semiconductor device in which an element formation region and an element isolation region are formed on a semiconductor substrate.

  The method for manufacturing a semiconductor device disclosed in the present application is a method for manufacturing a semiconductor device in which an element isolation region is formed on a semiconductor substrate. This method for manufacturing a semiconductor device includes an oxide film forming step of forming an oxide film on the surface of a semiconductor substrate. In addition, a nitride film forming step of forming a nitride film on the surface of the oxide film is provided. In addition, the semiconductor device includes a first trench formation step of forming a first trench by removing the semiconductor substrate, the oxide film, and the nitride film in the element isolation region. In addition, the semiconductor substrate exposed on the side wall of the first trench is transformed into the first thermal oxide film by thermal oxidation, so that the width of the first trench is narrowed and the inside of the first trench is removed except for the first trench. A first thermal oxidation step for forming an isolation trench filled with a thermal oxide film; Further, a nitride film removing step for removing the nitride film is provided. In addition, an amorphous silicon layer forming step of closing the opening of the first trench with the amorphous silicon layer by forming an amorphous silicon layer on the surface of the semiconductor substrate after removing the nitride film is provided. In addition, a second thermal oxidation process is provided for transforming the amorphous silicon layer into a second thermal oxide film by thermal oxidation.

  In this manufacturing method, an oxide film and a nitride film are formed on the surface of a semiconductor substrate, and a part of the film and the semiconductor substrate is removed to form a first trench. Next, in the first thermal oxidation process, the semiconductor substrate exposed on the side wall of the first trench is oxidized by thermal oxidation, thereby forming an isolation trench filled with the first thermal oxide film.

  When the semiconductor substrate is oxidized, the first thermal oxide film is formed, and the volume expands. Therefore, as the thermal oxidation proceeds, the first thermal oxide film expands from both side walls of the first trench toward the center of the trench, and the width of the first trench becomes narrower. In the first thermal oxidation step, thermal oxidation is performed so that the first thermal oxide films that have expanded from both side walls of the first trench are not joined to each other and the first trench disappears. That is, thermal oxidation is performed so that the first trench having a reduced width remains in the isolation trench. In the first thermal oxidation step, the nitride film prevents the semiconductor substrate in the region other than the region where the isolation trench is formed from being thermally oxidized.

  In the amorphous silicon layer forming step, an amorphous silicon layer is formed on the surface of the semiconductor substrate after removing the nitride film, thereby closing the opening of the first trench with the amorphous silicon layer. Therefore, it is possible to form a structure in which the first trench exists as a gap in the thermal oxide film of the isolation trench. In the second thermal oxidation step, the amorphous silicon layer is transformed into a second thermal oxide film by thermal oxidation.

  In the semiconductor device manufactured by this manufacturing method, the thermal stress generated in the isolation trench portion by the heat treatment at the time of forming the semiconductor device can be relieved by the gap formed by the first trench. Therefore, the generation of crystal defects in silicon due to thermal stress can be suppressed, and deterioration of element characteristics can be prevented.

  Further, in the method for manufacturing a semiconductor device of the present application, a step of filling the isolation trench with the first thermal oxide film by the first thermal oxidation step, and a step of creating a narrow first trench in the thermal oxide film of the isolation trench Can be performed simultaneously. Therefore, since it is not necessary to provide a dedicated process for forming the trench in the thermal oxide film of the isolation trench, the manufacturing process of the semiconductor device can be simplified.

  In the semiconductor device manufactured by the method for manufacturing a semiconductor device of the present application, the opening of the first trench can be closed with the second thermal oxide film. The thermal oxide film is a dense film and has a high pressure resistance as compared with a silicon oxide film deposited by a CVD method or the like. Therefore, the breakdown voltage of the semiconductor device can be increased.

  In the method for manufacturing a semiconductor device disclosed in the present application, the thickness of the amorphous silicon layer is not less than √2 times the opening width of the opening of the first trench after being narrowed by the first thermal oxidation step. Is preferred. When viewed from the upper surface of the semiconductor substrate, the first trench may be formed to have a bent portion bent at a right angle. In this case, the maximum width of the first trench is the diagonal length of the bent portion (√2 times the width of the straight portion). In some cases, two linear first trenches are orthogonal and have an intersection. In this case, the maximum width of the first trench is the diagonal length of the intersection (√2 times the width of the straight portion). Therefore, by making the thickness of the amorphous silicon layer more than √2 times the opening width (width of the straight line portion) of the opening portion of the first trench after being narrowed, the opening portion of the first trench is surely made amorphous. It becomes possible to block with the silicon layer.

  In the first trench formation step of the method for manufacturing a semiconductor device disclosed in the present application, a plurality of first trenches are formed in a region where one isolation trench is formed, and the widths of the plurality of first trenches are equal. It is preferable that In forming a thick thermal oxide film on the order of submicron, the oxidation rate follows the square rate, so that the required oxidation time is proportional to the square of the silicon film thickness. In the semiconductor device manufacturing method of the present application, the width of the semiconductor substrate formed in a wall shape between the first trenches can be reduced by forming a plurality of first trenches for one isolation trench. . Therefore, since the thickness of silicon to be oxidized in the thermal oxide film filling step can be reduced, the time required for thermal oxidation can be shortened.

  In the first trench formation step of the method for manufacturing a semiconductor device disclosed in the present application, a plurality of first trenches may be formed in a region where one isolation trench is formed. At this time, it is preferable that the width of the first trench is larger than a value obtained by multiplying the wall thickness of the wall portion formed between the first trenches by 1.22. By forming a plurality of first trenches for one isolation trench, a wall portion of the semiconductor substrate is formed between the first trenches. When the wall is completely transformed into the first thermal oxide film, the altered wall thickness expands 2.22 times in the horizontal direction. That is, both side surfaces of the wall portion expand in the direction of narrowing the first trench by 0.61 times the wall thickness before oxidation. Then, in order to make the first trench remain when the wall portion is completely transformed into the first thermal oxide film, theoretically, the width of the first trench is set to 1 of the wall thickness of the wall portion. It can be seen that the value should be larger than .22 times.

  The method for manufacturing a semiconductor device disclosed in the present application may further include a resist film forming step of forming a resist film on the second thermal oxide film in a region where the isolation trench is formed by a photoetching technique or the like. it can. The photoetching technique means a series of techniques from photolithography to etching such as RIE. Since a conventionally known technique can be used for the photoetching technique, a detailed description thereof is omitted here. In addition, a second thermal oxide film removing step of removing the second thermal oxide film other than the region where the resist film is formed can be further provided. Moreover, the resist film removal process of removing a resist film can be further provided.

  In regions other than the region where the isolation trench is formed, there is an element formation region for forming various elements such as transistors. Then, the surface of the element formation region can be selectively exposed by the second thermal oxide film removal step. Therefore, it is possible to form elements in the element formation region in the subsequent processes.

  The semiconductor device disclosed in the present application is a semiconductor device in which an isolation trench is formed in an element isolation region of a semiconductor substrate. The isolation trench has a first thermal oxide film formed in a range from the surface of the semiconductor substrate to a predetermined depth, and a second thermal oxide film formed on the surface of the first thermal oxide film. In addition, a trench having a narrower width than the width of the first thermal oxide film is formed in the first thermal oxide film. The second thermal oxide film closes the opening of the trench formed in the first thermal oxide film. This semiconductor device is a semiconductor device embodied by the semiconductor device manufacturing method of the present application. In the semiconductor device, the trench formed in the first thermal oxide film can relieve the thermal stress generated in the isolation trench due to the heat treatment during the formation of the semiconductor device. In addition, since the opening of the trench formed in the first thermal oxide film is closed with the second thermal oxide film, it is possible to prevent a chemical solution or the like from entering the trench in a later process.

  According to the method for manufacturing a semiconductor device disclosed in the present application, when manufacturing a semiconductor device in which an element formation region and an element isolation region are formed on a semiconductor substrate, thermal stress generated in the isolation trench portion can be reduced. It becomes possible.

It is FIG. (1) explaining the manufacturing process of a semiconductor device. It is FIG. (2) explaining the manufacturing process of a semiconductor device. It is FIG. (3) explaining the manufacturing process of a semiconductor device. It is FIG. (4) explaining the manufacturing process of a semiconductor device. It is FIG. (5) explaining the manufacturing process of a semiconductor device. It is FIG. (6) explaining the manufacturing process of a semiconductor device. FIG. 7 is a view (No. 7) for explaining a manufacturing step of a semiconductor device; It is FIG. (8) explaining the manufacturing process of a semiconductor device. It is FIG. (9) explaining the manufacturing process of a semiconductor device. It is FIG. (10) explaining the manufacturing process of a semiconductor device. It is FIG. (11) explaining the manufacturing process of a semiconductor device. It is FIG. (1) explaining the maximum opening width. It is a figure (the 2) explaining the maximum opening width.

The main features of the embodiments described below are listed.
(Feature 1) Thermal oxidation of the SOI layer 20 exposed on the side wall of the first trench 52 is performed at 1100 ° C. or higher.
(Feature 2) The amorphous silicon layer 70 is formed by sputtering.
(Characteristic 3) The amorphous silicon layer 70 is formed by atmospheric pressure CVD.

  Embodiments of the present application will be described with reference to the drawings. A process of forming a trench portion in the isolation trench region R2 while leaving the SOI (Silicon On Insulator) layer 20 in the element formation region R1 will be described with reference to FIGS. The element formation region R1 is a region where a semiconductor element such as a transistor is formed. The isolation trench region R2 is a region where an isolation trench for electrically isolating adjacent element formation regions R1 is formed. 1 to 15 are partial cross-sectional views of the element formation region R1 and the isolation trench region R2.

  As shown in FIG. 1, the SOI substrate 9 includes a buried oxide film 10 and an SOI layer 20. The SOI layer 20 is single crystal silicon. In the present embodiment, the description will be made with the holding substrate existing below the buried oxide film 10 omitted. As shown in FIG. 1, first, an oxide film 30 is formed on the surface of the SOI layer 20. The oxide film 30 is formed by thermal oxide film deposition by CVD (Chemical Vapor Deposition) or thermal oxidation. The oxide film 30 may be a LOCOS oxide film that is widely used for element isolation. Next, a nitride film 40 is formed on the surface of the oxide film 30 by a CVD method. The nitride film 40 is a film for preventing the undesired SOI layer 20 from being thermally oxidized in a later thermal oxidation step. Accordingly, the thickness of the nitride film 40 may be sufficient to prevent oxidation, and is set to 50 (nm), for example.

  As shown in FIG. 2, a resist layer 50 is formed on the surface of the nitride film 40. Then, the resist layer 50 in the region of the isolation trench region R2 is removed by a photoetching technique, and an opening 51 is formed. The opening 51 is a mask hole for forming a first trench 52 described later. A plurality of openings 51 are preferably formed for one isolation trench region R2. Moreover, it is preferable that the opening width of each of the plurality of openings 51 be equal.

  Next, as shown in FIG. 3, the nitride film 40 and the oxide film 30 are etched by dry etching using a CF-based gas. Subsequently, the SOI layer 20 is dry-etched by dry etching using a gas (SF6 or the like) that has an etching effect on silicon. As a result, two first trenches 52 are formed in the SOI layer 20. Further, the wall portion 53 of the SOI layer 20 is formed between the first trenches 52.

  Here, the width of the first trench 52 is defined as the trench width W1, and the thickness of the wall portion 53 is defined as the wall thickness W2. A method of determining the ratio between the trench width W1 and the wall thickness W2 will be described. In the thermal oxidation step (FIG. 5) to be described later, when the wall 53 is completely transformed into a thermal oxide film, the wall thickness W2 after the alteration expands 2.22 times. That is, both side surfaces of the wall portion 53 expand in the horizontal direction (the left-right direction in the drawing) by a value 0.61 times the wall thickness W2. Similarly, the side wall of the first trench 52 facing the wall portion 53 also expands in the horizontal direction by a value 0.61 times the wall thickness W2. Then, in order to make the first trench 52 remain in the isolation trench region R2 after the wall portion 53 is completely transformed into a thermal oxide film, theoretically, the trench width W1 of the first trench 52 is set to It can be seen that the resist dimensions and the dry etching dimensions may be controlled so as to be larger than 1.22 times the wall thickness W2 of the wall portion 53.

  As shown in FIG. 4, the resist layer 50 remaining after the etching is removed. The removal method may use wet etching by SPM (Sulfuric acid / hydrogen Peroxide Mixture) which is a mixed solution of sulfuric acid, hydrogen peroxide solution and water, or may use ashing.

  As shown in FIG. 5, the SOI layer 20 exposed on the side wall of the first trench 52 is altered from a silicon single crystal to a thermal oxide film 60 by thermal oxidation. At this time, the SOI layer 20 in the element formation region R <b> 1 is prevented from being thermally oxidized by the nitride film 40. When the SOI layer 20 is transformed into the thermal oxide film 60, the volume expands. Therefore, as the thermal oxidation proceeds, the thermal oxide film 60 expands from both side walls of the first trench 52 toward the center of the first trench 52, and the width of the first trench 52 becomes narrower. When the thermal oxidation process is completed, the first trench 52 changes to the narrow first trench 52a. As a result, as shown in FIG. 5, a structure in which the inside of the isolation trench region R2 is filled with the thermal oxide film 60 and the narrow first trench 52a exists in the isolation trench region R2 can be formed. Here, the width of the opening of the narrow first trench 52a is defined as the opening width W3. 5 is preferably performed at a high temperature of 1100 ° C. or higher for the purpose of stress relaxation due to the fluidity of the thermal oxide film 60.

  Further, if the thermal oxidation process is continued even after the wall portion 53 is completely transformed into the thermal oxide film 60, the thermal oxidation of the SOI layer 20 existing at the boundary between the isolation trench region R2 and the element formation region R1 proceeds. The side wall of the narrow first trench 52a further expands. As a result, the thermal oxide films 60 forming the side walls of the narrow first trench 52a are joined together, and the narrow first trench 52a disappears. Therefore, it is necessary to adjust the thermal oxidation amount so that the thermal oxidation is completed when the wall portion 53 is completely transformed into the thermal oxide film 60. As an example of a method for adjusting the thermal oxidation amount, there is a method of calculating an oxidation time for completely oxidizing the wall thickness W2 of the wall portion 53 and performing thermal oxidation using the calculated oxidation time.

  As shown in FIG. 6, the nitride film 40 is removed. For removing the nitride film 40, wet etching with hot phosphoric acid or dry etching may be used.

  As shown in FIG. 7, an amorphous silicon layer 70 is formed on the surface after removing the nitride film 40 by sputtering. At this time, the opening width W3 of the narrow first trench 52a is narrowed. Further, the sputtering method has poor embeddability compared to the low pressure CVD method or the like. Therefore, since amorphous silicon is hardly embedded in the narrow first trench 52a, the amorphous silicon layer 70 grows on the surface of the thermal oxide film 60 so as to close the opening of the narrow first trench 52a. Thereby, a structure in which the narrow first trench 52a exists as a gap in the thermal oxide film 60 in the isolation trench region R2 can be formed. Further, by closing the opening of the narrow first trench 52a with the amorphous silicon layer 70, it is possible to prevent a chemical solution or the like from entering the narrow first trench 52a in a later step.

  Here, in order to reliably close the opening of the narrow first trench 52a with the amorphous silicon layer 70, the value of the opening width W3 is preferably 0.5 (μm) or less. The narrow first trench 52a preferably has a high aspect ratio, and the aspect ratio is preferably in the range of 5-10. The aspect ratio is the ratio of the depth and width of the trench. At the time of forming the amorphous silicon layer 70, amorphous silicon is also embedded in the narrow first trench 52a. However, by increasing the aspect ratio, the narrow first trench 52a is completely filled with amorphous silicon. Can be prevented. Therefore, since a gap can be present in the narrow first trench 52a, thermal stress can be relaxed.

  Further, the formation of the amorphous silicon layer 70 is not limited to the sputtering method, and may be performed by the CVD method. The atmospheric pressure CVD method is less likely to reach the bottom of the narrow first trench 52a and the embedding property is worse than the low pressure CVD method. Therefore, it is easier to close the opening of the narrow first trench 52a when the amorphous silicon layer 70 is formed using the atmospheric pressure CVD method.

  A method for determining the thickness of the amorphous silicon layer 70 will be described with reference to FIGS. As shown in FIG. 12, when the SOI substrate 9 is viewed from the upper surface, the narrow first trench 52a may be formed to have a bent portion A1 bent at a right angle due to the element layout. In this case, the maximum opening width W4 of the narrow first trench 52a is the diagonal length of the bent portion A1. Therefore, the maximum opening width W4 is √2 times (about 1.41 times) the opening width W3 of the narrow first trench 52a. Moreover, as shown in FIG. 13, two linear narrow first trenches 52a may be orthogonal to form an intersection A2. In this case, the maximum opening width W4 of the narrow first trench 52a is the diagonal length of the intersection A2. Therefore, the maximum opening width W4 is √2 times the opening width W3 of the narrow first trench 52a.

  As described above, the thickness of the amorphous silicon layer 70 is set to be √2 times or more the opening width W3 of the opening of the narrow first trench 52a, so that the opening of the narrow first trench 52a is reliably amorphous. It becomes possible to block with the silicon layer 70. For example, when the opening width W3 of the narrow first trench 52a is 0.5 (μm), the thickness of the amorphous silicon layer 70 needs to be 0.71 (μm) or more.

  As shown in FIG. 8, the outermost amorphous silicon layer 70 is thermally oxidized and transformed into a thermal oxide film 71. Thereby, it is possible to create a structure in which the insulator filled in the isolation trench region R2 is entirely a silicon thermal oxide film. The silicon thermal oxide film is a dense film and has a high pressure resistance compared to a silicon oxide film deposited by a CVD method or the like. Therefore, the breakdown voltage of the semiconductor device can be increased.

  The oxidation temperature during thermal oxidation of the amorphous silicon layer 70 is desirably a high temperature of 1100 ° C. or higher for the purpose of stress relaxation due to the fluidity of the thermal oxide film 71.

  As shown in FIG. 9, a resist layer 90 is formed on the thermal oxide film 71 in the region where the isolation trench region R2 is formed by the photoetching technique. Then, the resist layer 90 in the element formation region R1 is removed by a photoetching technique, and an opening is formed. This process is a preparation process for exposing the surface of the SOI layer 20 in the element formation region R1.

  As shown in FIG. 10, the thermal oxide film 71 and the oxide film 30 in the opening of the resist layer 90 are etched by wet etching with hydrofluoric acid. By adjusting the etching time, the surface of the SOI layer in the element formation region R1 can be completely exposed.

  As shown in FIG. 11, the resist layer 90 remaining after the etching is removed. As the removal method, the above-described wet etching by SPM may be used, or ashing may be used.

  The effects of the semiconductor device manufacturing method according to the present application will be described. In the manufacturing method of the semiconductor device of the present application, the thermal stress generated in the element formation region R1 and the isolation trench region R2 during the heat treatment during the formation of the semiconductor device can be relaxed by the gap formed by the narrow first trench 52a. Therefore, it is possible to suppress the occurrence of crystal defects in the SOI layer 20 in the element formation region R1 due to the thermal stress, so that the element characteristics can be prevented from being deteriorated.

  In the method for manufacturing a semiconductor device of the present application, the step of filling the isolation trench region R2 with the thermal oxide film 60 and the step of creating the narrow first trench 52a are simultaneously performed by the thermal oxidation step shown in FIG. it can. Therefore, it is not necessary to provide a dedicated process for forming a trench in the thermal oxide film 60 filled in the isolation trench region R2, so that the manufacturing process of the semiconductor device can be simplified.

  Moreover, in the manufacturing method of the semiconductor device of this application, the wall thickness of the wall part 53 formed between 1st trenches 52 is formed by forming several 1st trench 52 with respect to one isolation | separation trench area | region R2. Can be small. In the formation of a thick thermal oxide film on the order of submicrons, the oxidation rate follows the square rate, so the required oxidation time is proportional to the square of the film thickness. For example, the formation time of the thermal oxide film having a film thickness of 0.25 (μm) is about ¼ time compared to the formation time of the thermal oxide film having a film thickness of 0.5 (μm). Therefore, it is possible to shorten the time required for the thermal oxidation by reducing the wall thickness of the wall portion 53 to be oxidized in the thermal oxidation step.

  Compared with the method of forming an element isolation structure by forming an oxide film about 2 to 3 times the depth of the trench, and further removing and planarizing the oxide film in a CMP (Chemical Mechanical Polishing) process. In the semiconductor device manufacturing method of the present application, it is not necessary to use a CMP process. Therefore, an element isolation structure can be formed at low cost.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings can achieve a plurality of purposes at the same time, and has technical utility by achieving one of the purposes.

  In the step of forming the amorphous silicon layer 70 in FIG. 7, the amorphous silicon layer 70 does not necessarily exist only in the vicinity of the surface of the thermal oxide film 60, and even if amorphous silicon is present inside the narrow first trench 52a. good. The amorphous silicon inside the narrow first trench 52a is not necessarily thermally oxidized by the thermal oxidation process of FIG. However, since the amorphous silicon inside the narrow first trench 52a is covered with the buried oxide film 10 and the thermal oxide films 60 and 71, the breakdown voltage between the high voltage elements can be secured. .

  In this embodiment, the case where the SOI substrate 9 is used has been described, but the present invention is not limited to this. Even when a normal silicon substrate made of only a silicon single crystal is used, the method for manufacturing a semiconductor device of the present application can be implemented.

  Moreover, although the present Example demonstrated the case where the some 1st trench 52 was formed in one isolation | separation trench area | region R2, it is not restricted to this form. When there is no need to increase the thermal oxidation rate, such as when the width of the isolation trench region R2 is narrow, one first trench 52 may be formed in one isolation trench region R2.

  In the method for manufacturing a semiconductor device of the present application, an arbitrary number of narrow first trenches 52a can be formed for one isolation trench region R2. The number of the narrow first trenches 52a can be arbitrarily set according to the width of the isolation trench region R2, the number of gaps necessary for ensuring the withstand voltage between the high voltage elements, and the like.

9 SOI substrate 20 SOI layer 30 Oxide film 40 Nitride film 52 First trench 52a Narrow first trench 53 Wall portions 60 and 71 Thermal oxide film 70 Amorphous silicon layer R1 Element formation region R2 Isolation trench region W1 Trench width W2 Wall thickness W3 Opening width

Claims (6)

A method for manufacturing a semiconductor device in which an element isolation region is formed on a semiconductor substrate,
An oxide film forming step of forming an oxide film on the surface of the semiconductor substrate;
A nitride film forming step of forming a nitride film on the surface of the oxide film;
A first trench forming step of forming a first trench by removing the semiconductor substrate, oxide film, and nitride film in the element isolation region;
The semiconductor substrate exposed on the side wall of the first trench is transformed into a first thermal oxide film by thermal oxidation, so that the width of the first trench is reduced and the inside of the first trench is removed except for the first trench. A first thermal oxidation step to form an isolation trench filled with a film;
A nitride film removing step for removing the nitride film;
Forming an amorphous silicon layer on the surface of the semiconductor substrate after removing the nitride film, thereby closing the opening of the first trench with the amorphous silicon layer; and
A second thermal oxidation step for transforming the amorphous silicon layer into a second thermal oxide film by thermal oxidation;
A method for manufacturing a semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the thickness of the amorphous silicon layer is not less than √2 times the opening width of the opening of the first trench after being narrowed by the first thermal oxidation process. Production method. In the first trench formation step, a plurality of first trenches are formed in a region where one isolation trench is formed,
3. The method of manufacturing a semiconductor device according to claim 1, wherein each of the plurality of first trenches has the same width. In the first trench formation step, a plurality of first trenches are formed in a region where one isolation trench is formed, and the width of the first trench is the wall thickness of the wall portion formed between the first trenches. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is made larger than 1.22 times. A resist film forming step of forming a resist film on the second thermal oxide film in a region where the isolation trench is formed;
A second thermal oxide film removing step of removing the second thermal oxide film other than the region where the resist film is formed;
The method for manufacturing a semiconductor device according to claim 1, further comprising: a resist film removing step for removing the resist film. A semiconductor device in which an isolation trench is formed in an element isolation region of a semiconductor substrate,
The isolation trench is
A first thermal oxide film formed in a range from the surface of the semiconductor substrate to a predetermined depth;
Having a second thermal oxide film formed on the surface of the first thermal oxide film;
In the first thermal oxide film, a trench having a width narrower than the width of the first thermal oxide film is formed,
A semiconductor device, wherein the second thermal oxide film closes an opening of a trench formed in the first thermal oxide film.

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