JP2011151075A - Method of fabricating semiconductor optical integrated element - Google Patents

Abstract

A method of manufacturing a semiconductor optical integrated device capable of reducing optical connection loss between semiconductor optical devices is provided.
A mask 6 including a first portion 6a and a second portion 6b disposed so as to cross a boundary L1 between the first area 1b and the second area 1c is formed, and the mask 6 is used. Etching is performed to form a first waveguide mesa 7 and a semiconductor mesa 8, and the first waveguide mesa 7 and the semiconductor mesa 8 are embedded and connected to the first portion 11 a and the first portion 11 a on the semiconductor mesa. Then, a mask 11 including the second portion 11b is formed, and etching is performed using the mask 11 to form a second waveguide mesa 12 defined by the second portion 11b. The width of the second portion 6b is monotonously increased in the x-axis direction, and the width W2 of the second portion 11b is at least narrower than the width W1 of the second portion 6b.
[Selection] Figure 3

Description

  The present invention relates to a method for fabricating a semiconductor optical integrated device.

  Patent Document 1 describes a method in which a semiconductor laser (LD) having a buried structure and an arrayed waveguide (AWG) having a high mesa structure are formed to face each other. In this method, a mesa stripe structure connected to an AWG region is formed on a semiconductor substrate, and a portion of the mask used for forming the mesa stripe structure is removed from the AWG region. The method includes a step of forming a new mask, and a step of growing a buried layer on the semiconductor substrate and embedding a mesa stripe structure using the new mask as a selective growth mask.

Japanese Patent Laid-Open No. 2002-232069

  However, in the method described in Patent Document 1, in the step of embedding the mesa stripe structure, the abnormally grown semiconductor is grown on the mesa stripe structure from the AWG region where the mask is not formed. There is. In this case, the abnormally grown semiconductor is deposited on a region to be a connection portion between the buried structure and the high mesa structure. As a result, disconnection occurs at the connection portion between the embedded structure and the high mesa structure, and the optical connection loss between the LD and the AWG becomes large.

  As another method for manufacturing a semiconductor optical integrated device, the following can be applied. In this method, as shown in FIG. 5A, a semiconductor stack on a semiconductor substrate 33 is etched using a mask 30, and a first waveguide mesa 31 and a semiconductor mesa for the first semiconductor optical device are etched. 32 are formed on the main surface 33 a of the semiconductor substrate 33. Subsequently, as shown in FIG. 5B, using the mask 30 as a selective growth mask, a buried semiconductor layer 34 is grown on the main surface 33a of the semiconductor substrate 33, and the first waveguide mesa 31 and The semiconductor mesa 32 is embedded. Subsequently, as shown in FIG. 5C, after the mask 30 is removed, a new mask 35 is formed. Then, as shown in FIG. 6A, the semiconductor mesa 32 and the embedded semiconductor layer 34 are etched using the mask 35 to form a second waveguide mesa 36 for the second semiconductor optical device. To do.

  In this method, when the first waveguide mesa 31 and the semiconductor mesa 32 are embedded, abnormal growth may occur on the side surface 32a of the semiconductor mesa. In this case, as shown in FIG. 6B, a semiconductor by abnormal growth is deposited on a region to be a connection portion between the first waveguide mesa 31 and the second waveguide mesa 32, and the deposit E Will be formed. And in the area | region where the deposit E was formed, a mesa structure cannot be provided in a subsequent process. As a result, the edge of the second waveguide mesa 36 needs to be formed away from the edge of the first waveguide mesa 31. For this reason, also in this method, the optical connection loss between the first semiconductor optical device and the second semiconductor optical device is large.

  Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor optical integrated device that can reduce optical connection loss between semiconductor optical devices.

  A method of manufacturing a semiconductor optical integrated device according to the present invention is a method of manufacturing a semiconductor optical integrated device, in which a first semiconductor stack including a first waveguide layer for a first semiconductor optical device is a semiconductor. Forming a second semiconductor stack including a second waveguide layer for the second semiconductor optical device on the second area on the main surface of the semiconductor substrate; Crossing the boundary between the first area and the second area, the first portion having a stripe shape extending in the direction of a predetermined axis and disposed on the first semiconductor stack. Forming a first mask including a second portion disposed on the first semiconductor stack and the second semiconductor stack and a third portion disposed on the second semiconductor stack. And a first semiconductor stack and a second semiconductor stack using the first mask Etch and a first waveguide mesa for the first semiconductor optical device defined by the first portion, a semiconductor mesa defined by the second portion, and a third defined by the third portion A step of forming the semiconductor stack, a step of growing a buried semiconductor layer on the main surface using the first mask, a step of filling the first waveguide mesa and the semiconductor mesa, and a step of removing the first mask. After that, the buried semiconductor layer, the first waveguide mesa, the semiconductor mesa, the first portion disposed on the first area, the stripe shape extending in the direction of a predetermined axis, and the first portion on the semiconductor mesa. Forming a second mask connected to the first portion and including the semiconductor mesa, the third semiconductor stack, and the second portion disposed on the second area, and using the second mask Embedded semiconductor layer, semiconductor mesa and third semiconductor product And forming a second waveguide mesa for the second semiconductor optical device defined by the second portion of the second mask, the second portion of the first mask Is monotonically wide in the direction of the predetermined axis, and the width of the second portion of the second mask is narrower than the width of the second portion of the first mask. .

  In this method, the width of the second portion of the first mask monotonously increases in the direction of the predetermined axis. Further, the width of the second portion of the second mask is narrower than the width of the second portion of the first mask. Accordingly, in the step of embedding the semiconductor mesa with the buried semiconductor layer, even if the abnormally grown semiconductor is formed on both sides of the second portion of the first mask, the second portion of the second mask is formed. In the step of forming the second waveguide mesa by etching the semiconductor mesa, the abnormally grown semiconductor is removed together with both sides of the semiconductor mesa. For this reason, the optical connection loss between the first semiconductor optical device and the second semiconductor optical device can be reduced.

  In the method according to the present invention, the direction of the predetermined axis is the [011] direction, and the second portion of the first mask is defined by a straight line inclined at a predetermined angle with respect to the direction of the predetermined axis. It is preferable that the predetermined angle is 30 degrees or less. In this case, since the inclination of the straight line defining the taper shape of the second portion of the first mask is 30 degrees or less with respect to the [011] direction, the semiconductor mesa is embedded in the embedded semiconductor layer step. Abnormal growth from the side is difficult to occur.

  ADVANTAGE OF THE INVENTION According to this invention, the method of producing a semiconductor optical integrated device which can reduce the optical connection loss between semiconductor optical devices can be provided.

It is drawing which shows the main processes of the method of producing the semiconductor optical integrated element concerning this Embodiment. It is drawing which shows the main processes of the method of producing the semiconductor optical integrated element concerning this Embodiment. It is drawing which shows the main processes of the method of producing the semiconductor optical integrated element concerning this Embodiment. It is a figure for demonstrating the abnormal growth of a semiconductor, and a top view of the semiconductor optical integrated device produced by the method concerning this Embodiment. It is drawing which shows the main processes of the other method of producing a semiconductor optical integrated device. It is drawing which shows the main processes of the other method of producing a semiconductor optical integrated device.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Next, embodiments of the method for producing a semiconductor optical integrated device of the present invention will be described with reference to the attached drawings. Where possible, the same parts are denoted by the same reference numerals.

  1, 2 and 3 are drawings showing the main steps of a method for fabricating a semiconductor optical integrated device according to the present embodiment. 1-3, a rectangular coordinate system C is shown. A method of manufacturing a semiconductor optical integrated device including the first and second semiconductor optical devices will be described with reference to FIGS. Examples of the first semiconductor optical element include a semiconductor laser element, a semiconductor light receiving element, and a semiconductor optical amplification element. Examples of the second element include a ring resonator, a Mach-Zehnder interferometer, and an arrayed waveguide.

  First, a semiconductor substrate is prepared. As shown in FIG. 1A, the semiconductor substrate 1 has a main surface 1a. The main surface 1a of the semiconductor substrate 1 includes a first area 1b and a second area 1c. The first area 1b and the second area 1c are adjacent to each other and are arranged along the x-axis direction. The first area 1b is an area for the first semiconductor optical device, and the second area 1c is an area for the second semiconductor optical device. The semiconductor substrate 1 can be an n-type InP semiconductor substrate, for example. The main surface 1a of the semiconductor substrate 1 can be a (100) plane, for example. In the present embodiment, the x-axis indicates the [011] direction, and the y-axis indicates the [01-1] direction.

  Subsequently, in step S <b> 101, the semiconductor stack 2 is grown on the main surface 1 a of the semiconductor substrate 1 as shown in FIG. The semiconductor stack 2 includes a lower cladding layer 2a, an active layer 2b, an upper cladding layer 2c, and a contact layer 2d. The lower cladding layer 2a, the active layer 2b, the upper cladding layer 2c, and the contact layer 2d are sequentially stacked on the main surface 1a of the semiconductor substrate 1 in the z-axis direction.

  The material of the lower cladding layer 2a can be n-type InP, for example. The material of the upper cladding layer 2c can be p-type InP, for example. The material of the contact layer 2d can be, for example, p-type InGaAs. Moreover, the active layer 2b can be comprised by the multiple quantum well which consists of undoped GaInAsP, for example. For the growth of each of these layers, for example, a metal organic vapor phase epitaxial growth method can be used.

  Subsequently, in step S102, as shown in FIG. 1B, a mask 3 is formed on the semiconductor stack 2 and the first area 1b, and the semiconductor stack on the second area 1c is used by using the mask 3. 2 is removed by etching. With this step, the semiconductor stack 4 is formed on the first area 1 b of the main surface 1 a of the semiconductor substrate 1. The semiconductor stack 4 includes a lower cladding layer 4a, an active layer 4b, an upper cladding layer 4c, and a contact layer 4d. The lower cladding layer 4a, the active layer 4b, the upper cladding layer 4c, and the contact layer 4d are formed by etching the lower cladding layer 2a, the active layer 2b, the upper cladding layer 2c, and the contact layer 2d, respectively.

The mask 3 is preferably formed of a dielectric material. Specific examples of the material of the mask 3 include silicon oxide (for example, SiO ₂ ) and silicon nitride (for example, SiN). When the material of the mask 3 is SiO ₂ or SiN, for example, the semiconductor stack 2 can be etched by RIE (Reactive Ion Etching) using a mixed gas of CH ₄ and H ₂ .

  Subsequently, in step S103, as shown in FIG. 1C, the semiconductor stack 5 is selectively grown on the second area 1c using the mask 3 as a selective growth mask. The semiconductor stack 4 and the semiconductor stack 5 are adjacent to each other and arranged in the x-axis direction. The semiconductor stack 5 includes a lower cladding layer 5a, a waveguide layer 5b, an upper cladding layer 5c, and a contact layer 5d. The lower cladding layer 5a, the waveguide layer 5b, the upper cladding layer 5c, and the contact layer 5d are sequentially stacked in the z-axis direction on the second area 1c of the main surface 1a of the semiconductor substrate 1. The active layer 4b of the semiconductor stack 4 and the waveguide layer 5b of the semiconductor stack 5 are optically coupled to each other. The active layer 4b of the semiconductor stack 4 and the waveguide layer 5b of the semiconductor stack 5 are preferably formed at substantially the same height in the z-axis direction.

  The material of the lower cladding layer 5a can be n-type InP, for example. The material of the upper cladding layer 5c can be p-type InP, for example. The material of the contact layer 5d can be, for example, p-type InGaAs. The waveguide layer 5b can be made of, for example, undoped GaInAsP. The PL (Photo Luminescence) wavelength of the waveguide layer 5b is preferably shorter than the PL wavelength of the waveguide layer 4b in order to reduce the waveguide loss of the second element.

  Through the above steps S101 to S103, the semiconductor stack 4 including the active layer 4b for the first semiconductor optical device is formed on the first area 1b, and the waveguide layer 5b for the second semiconductor optical device is formed. A second semiconductor stack including the same is formed on the second area 1c.

  Subsequently, in step S104, after removing the mask 3, a mask 6 is formed on the semiconductor stack 4 and the semiconductor stack 5 as shown in FIG. The mask 6 includes a first portion 6a, a second portion 6b, and a third portion 6c. The first portion 6a, the second portion 6b, and the third portion 6c are sequentially arranged in the x-axis direction.

  The first portion 6 a is disposed on the surface 4 e of the semiconductor stack 4. The first portion 6a has a stripe shape extending in the x-axis direction. The end of the stripe is located in the vicinity of the boundary L <b> 2 between the semiconductor stack 4 and the semiconductor stack 5 on the semiconductor stack 4.

  The second portion 6b includes a surface 4e of the semiconductor stack 4 and a surface 5e of the semiconductor stack 5 so as to cross the boundary L1 between the first area 1b and the second area 1c and the boundary L2 between the semiconductor stack 4 and the semiconductor stack 5. Is placed on top. The width of the second portion 6b monotonously increases in the x-axis direction. As an example, the second portion 6b has a tapered shape, for example. This taper shape is defined by a straight line inclined at an angle θ with respect to the x-axis direction. For example, the inclination angle θ is preferably 30 degrees or less. The end portion E1 on the narrow side of the second portion 6b is connected to the end portion in the positive direction of the x-axis of the first portion 6a, and the end portion E2 on the wide side is 3 part 6c. The width of the end portion E2 of the second portion 6b is W1.

  The third portion 6 c is disposed on the semiconductor stack 5. As an example, the third portion 6c is disposed so as to cover the surface 5e of the semiconductor stack 5 other than the region R including the boundary L2 between the semiconductor stack 4 and the semiconductor stack 5 and extending in the y-axis direction, for example. .

The mask 6 is also preferably formed of a dielectric, like the mask 3. Specific examples of the material of the mask 6 include silicon oxide (for example, SiO ₂ ) and silicon nitride (for example, SiN). When the material of the mask 6 is SiO ₂ , the mask 6 can be formed as follows. First, after removing the mask 3, a SiO ₂ film is formed on the entire surface 4 e of the semiconductor stack 4 and the entire surface 5 e of the semiconductor stack 5. Thereafter, a resist mask is formed on the SiO ₂ film by photolithography. This resist mask has a shape corresponding to the first portion 6a, the second portion 6b, and the third portion 6c. Then, after etching the SiO ₂ film using this resist mask, the resist mask is removed.

Subsequently, in step S105, as illustrated in FIG. 2B, the semiconductor stack 4 and the semiconductor stack 5 are etched using the mask 6. When the material of the mask 6 is SiO ₂ or SiN, for example, the semiconductor stack 4 and the semiconductor stack 5 can be etched by RIE using a mixed gas of CH ₄ and H ₂ . By this etching, a first waveguide mesa 7, a semiconductor mesa 8, and a semiconductor stack 9 are formed on the main surface 1 a of the semiconductor substrate 1.

  The first waveguide mesa 7 is defined by the first portion 6 a of the mask 6. Therefore, the first waveguide mesa 7 is a stripe mesa extending in the x-axis direction and is disposed on the first area 1b. The end of the first waveguide mesa 7 in the positive x-axis direction is connected to the semiconductor mesa 8.

  The semiconductor mesa 8 is defined by the second portion 6 b of the mask 6. Therefore, the semiconductor mesa 8 is a taper-shaped mesa whose width increases in the x-axis direction. The semiconductor mesa 8 is formed on the first area 1b and the second area 1c so as to cross the boundary L1 between the first area 1b and the second area 1c. For this reason, the semiconductor mesa 8 includes the boundary L <b> 2 between the semiconductor stack 4 and the semiconductor stack 5. The narrow end of the semiconductor mesa 8 is connected to the positive end of the first waveguide mesa 7 in the x-axis direction, and the wide end of the semiconductor mesa 8 is connected to the semiconductor stack 9. Has been.

  The semiconductor stack 9 is defined by the third portion 6 c of the mask 6. Therefore, the semiconductor stack 9 is disposed on the second area 1c.

  Subsequently, in step S106, as shown in FIG. 2C, the buried semiconductor layer 10 is grown on the main surface 1a of the semiconductor substrate 1 using the mask 6 as a selective growth mask, and the first waveguide is formed. The mesa 7 and the semiconductor mesa 8 are embedded with the embedded semiconductor layer 10. The buried semiconductor layer 10 is preferably Fe-doped InP for current confinement in the first waveguide mesa 7.

  Subsequently, in step S107, after removing the mask 6, as shown in FIG. 3A, the mask 11 is formed on the first waveguide mesa 7, the semiconductor mesa 8, the semiconductor stack 9, and the embedded semiconductor layer 10. Form. The mask 11 includes a first portion 11a and a second portion 11b. The first portion 11a is disposed on the first waveguide mesa 7, the semiconductor mesa 8, the buried semiconductor layer 10, and the first area 1b.

  The second portion 11b is disposed on the semiconductor mesa 8, the semiconductor stack 9, and the second area 1c. The second portion 11b has a stripe shape extending in the x-axis direction. The second portion 11 b is connected to the first portion 11 a on the semiconductor mesa 9. Further, the width W2 of the second portion 11b is narrower than the width W1 of the end portion E2 of the second portion 6b of the mask 6.

Such a mask 11 is also preferably formed of a dielectric, like the mask 3 and the mask 6. Specific examples of the material of the mask 11 include silicon oxide (for example, SiO ₂ ) and silicon nitride (for example, SiN). In the case where the material of the mask 11 is SiO ₂ , it can be formed by using the photolithography method as in the mask 6.

Subsequently, in step S108, as shown in FIG. 3B, the semiconductor mesa 8, the semiconductor multilayer 9, and the embedded semiconductor layer 10 are etched using the mask 11. When the material of the mask 11 is SiO ₂ or SiN, this etching can be performed by, for example, RIE using a mixed gas of CH ₄ and H ₂ . In particular, since the surfaces of both side portions 8a of the semiconductor mesa 8 are not covered with the mask 11, both side portions 8a of the semiconductor mesa 8 are removed by this etching.

  By this step S108, the second waveguide mesa 12 for the second semiconductor optical device is formed on the second area 1c of the main surface 1a of the semiconductor substrate 1. The second waveguide mesa 12 is defined by the second portion 11 b of the mask 11. Therefore, the second waveguide mesa 12 is a stripe mesa extending in the x-axis direction on the second area 1c. The second waveguide mesa 12 is optically coupled to the first waveguide mesa 7 through the remaining portion 8 b of the semiconductor mesa 8.

  In step S109, as shown in FIG. 3C, the upper electrode 13 is formed on the first waveguide mesa 7, and the lower electrode 14 is formed on the back surface of the semiconductor substrate 1. The upper electrode 13 is formed in contact with the contact layer 4 d of the first waveguide mesa 7. Thereafter, the semiconductor optical integrated device including the first semiconductor optical device and the second semiconductor optical device is obtained by cleaving along a predetermined cleavage line.

  FIG. 4A is a diagram for explaining abnormal growth of a semiconductor. In the method according to the present embodiment, the second portion 6b of the mask 6 spreads at an angle θ with respect to the [011] direction (x-axis direction), as shown in FIG. For this reason, in the step S106 of embedding the semiconductor mesa 8 with the buried semiconductor layer 10, an abnormally grown semiconductor may grow on the both sides ba of the second portion 6b of the mask 6 from the [011] direction. . Further, since the growth rate of the plane along the [01-1] direction is not so different from the growth rate of the (100) plane, crystal growth is performed on the plane along the [01-1] direction and the (100) plane. When performed, abnormal growth is likely to occur on the plane along the [01-1] direction. For this reason, also in the method according to the present embodiment, in particular, from the vicinity of the boundary L3 between the surface 9a along the [01-1] direction (the y-axis direction) and the side surface 8c of the semiconductor mesa 8, The semiconductor rides on both side portions 6ba of the second portion 6b and grows abnormally. The second portion of the mask 6 has an intermediate portion 6bb between both side portions 6ba. The intermediate portion 6bb is, for example, a striped region extending along the x-axis direction.

  In the method according to the present embodiment, the width of the second portion 6b of the mask 6 is monotonously increased in the x-axis direction, and the width W2 of the second portion 11b of the mask 11 is This is narrower than the width W1 of the end E2 of the second portion 6b. For this reason, even if the semiconductor 11 in the abnormal growth is formed on both sides 6ba of the second portion 6b of the mask 6 as described above in the step S106 of embedding the semiconductor mesa 8 with the buried semiconductor layer 10, the mask 11 In step S108 of forming the second waveguide mesa 12 by etching the semiconductor mesa 8 using the second portion 11b, the abnormally grown semiconductor is removed together with the side portions 8a of the semiconductor mesa 8. As a result, it is possible to suppress disconnection at the connection portion between the first waveguide mesa 7 and the second waveguide mesa 12, and the edge of the second waveguide mesa 12 is connected to the edge of the first waveguide mesa 7. There is no need to move away from the edge. Therefore, the optical connection loss between the first semiconductor optical device and the second semiconductor optical device can be reduced.

  Here, in the method according to the present embodiment, it is preferable that the slope of the straight line defining the taper shape of the second portion 6b of the mask 6 is 30 degrees or less with respect to the [011] direction. In this case, since the inclination of the straight line defining the taper shape of the second portion 6b of the mask 6 is 30 degrees or less with respect to the [011] direction, the side surface 8c of the semiconductor mesa 8 and the first waveguide mesa 7 The angle formed with the side surface 7a is approximately 30 degrees or less. For this reason, the angle formed by the surface orthogonal to the side surface 7a of the first waveguide mesa 7 (that is, the surface extending along the [01-1] direction) and the side surface 8c of the semiconductor mesa 8 is relatively large. As a result, abnormal growth from the side surface 8c of the semiconductor mesa 8 is unlikely to occur in the step S106 of growing the embedded semiconductor layer 10.

  In the method according to the present embodiment, the third portion 6 c of the mask 6 is connected to the second portion 6 b of the mask 6 on the semiconductor stack 8. For this reason, in step S <b> 106 of embedding the first waveguide mesa 7 and the semiconductor mesa 8, it is possible to suppress the semiconductor from growing on the semiconductor stack 9 onto the second portion 6 b of the mask 6.

  Note that the width W2 of the second portion 11b of the mask 11 may be at least smaller than the width W1 of the end portion E2 of the second portion of the mask 6. Therefore, the width W2 of the second portion of the mask 11 is made smaller than the width of the second portion of the mask 6 on the boundary L1 between the first area 1b and the second area 1c of the semiconductor substrate 1, for example. Alternatively, it may be narrower than the width of the end E1 of the second portion of the mask 6.

  Further, in step S107, the mask 11 may be formed so that the second portion 11b is connected to the first portion 11a on the narrow end of the semiconductor mesa 8. In this case, since the first portion 11a and the second portion 11b of the mask 11 are connected on the edge of the first waveguide mesa 7, the semiconductor mesa 8 is etched by etching in step S108. The remaining portion 8b is not formed.

  Further, the method according to the present embodiment may further include the step of embedding the second waveguide mesa 12 with a low refractive index material such as polyimide after the second waveguide mesa 12 is formed in step S108. Good.

  Furthermore, the method according to the present embodiment may include a step of covering the second waveguide mesa 12 with a predetermined insulating film after forming the second waveguide mesa 12 in step S108.

  Here, in the method shown in FIGS. 5 and 6, the portion defining the semiconductor mesa 32 of the mask 30 has a rectangular shape. For this reason, in the step of embedding the first waveguide mesa 31 and the semiconductor mesa 32, abnormal growth proceeds from the side surface 32a of the semiconductor mesa 32, and on the region that becomes the second waveguide mesa 36 in a later step. Abnormally grown semiconductors may be deposited.

  On the other hand, in the method according to the present embodiment, the second portion 6b that defines the semiconductor mesa 8 of the mask 6 has a tapered shape whose width gradually increases in the x-axis direction. For this reason, even if abnormal growth proceeds from the side surface 9a of the semiconductor stack 9 in the step of embedding the first waveguide mesa 7 and the semiconductor mesa 8, both side portions 6ba of the second portion 6b of the second mask 6 are processed. In this case, it is difficult for an abnormally grown semiconductor to reach the intermediate portion 6bb located on the region that becomes the second waveguide mesa 12 in a later step. For this reason, it is possible to relatively reduce the abnormally grown semiconductor deposited on the intermediate portion 6bb.

  In order to prevent the abnormally grown semiconductor from reaching the intermediate portion 6bb, the inclination of the straight line defining the taper shape with respect to the x-axis direction is preferably set to 30 degrees or less, for example. Further, in order to prevent the abnormally grown semiconductor from reaching the intermediate portion 6bb, it is preferable to set the width W3 of the both side portions 6ba to be larger than a predetermined value. Since the degree of abnormal growth depends on the height of the buried semiconductor layer 10, this predetermined value also depends on the height of the buried semiconductor layer 10, but can be about 4 μm, for example.

  The method according to this embodiment described above can be applied to the fabrication of the semiconductor optical integrated device 20 as shown in FIG. 4B, for example. The semiconductor optical integrated device 20 includes a chirped diffraction grating 21, a gain region 22, and a ring resonator 23. The gain region 22 requires a current confinement structure in order to inject current and generate gain. For this reason, the waveguide 22a in the gain region 22 is preferably a waveguide having a buried structure of InP doped with Fe. On the other hand, in the ring resonator 103, since the waveguide 23a needs to be bent with a radius of curvature of about 10 μm, it is preferably a waveguide having a high mesa structure.

  Therefore, for example, in the connection portion D between the gain region 22 and the ring resonator 23, the waveguide 22a having a buried structure and the waveguide 23a having a high mesa structure are connected. In the above method, the semiconductor optical integrated device 20 is manufactured by using the first semiconductor optical device as the gain region 22 and the second semiconductor optical device as the ring resonator 23. Since it is difficult for problems to occur in the connection portion between the waveguide 22a and the waveguide 23a of the ring resonator 23, the optical connection loss between the gain region 22 and the ring resonator 23 is reduced.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention may be modified in detail without departing from such principles. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... Main surface, 1b ... 1st area, 1c ... 2nd area, 4 ... Semiconductor lamination | stacking (1st semiconductor lamination | stacking), 4b ... Active layer (1st waveguide layer), 5 ... Semiconductor stack (second semiconductor stack), 5b ... Waveguide layer (second waveguide layer), 6 ... Mask (first mask), 6a ... First part, 6b ... Second part, 6c ... 3rd part, 7 ... 1st waveguide mesa, 8 ... Semiconductor mesa, 9 ... Semiconductor lamination (3rd semiconductor lamination), 10 ... Embedded semiconductor layer, 11 ... Mask (2nd mask), 11a ... 1st part, 11b ... 2nd part, 12 ... 2nd waveguide mesa.

Claims (2)

A method for producing a semiconductor optical integrated device, comprising:
Forming a first semiconductor stack including a first waveguide layer for a first semiconductor optical device on a first area of a main surface of a semiconductor substrate;
Forming a second semiconductor stack including a second waveguide layer for a second semiconductor optical device on a second area of the main surface of the semiconductor substrate;
The first portion having a stripe shape extending in the direction of a predetermined axis and disposed on the first semiconductor stack, and the boundary between the first area and the second area, Forming a first mask including a first semiconductor stack, a second portion disposed on the second semiconductor stack, and a third portion disposed on the second semiconductor stack; When,
The first waveguide mesa for the first semiconductor optical device defined by the first portion is etched using the first mask to etch the first semiconductor stack and the second semiconductor stack. Forming a semiconductor mesa defined by the second portion and a third semiconductor stack defined by the third portion;
Growing a buried semiconductor layer on the main surface using the first mask, and embedding the first waveguide mesa and the semiconductor mesa;
After removing the first mask, the buried semiconductor layer, the first waveguide mesa, the semiconductor mesa, the first portion disposed on the first area, and the direction of the predetermined axis And a second portion disposed on the semiconductor mesa, the second portion disposed on the second area, and connected to the first portion on the semiconductor mesa. Forming a second mask including:
Etching the buried semiconductor layer, the semiconductor mesa, and the third semiconductor stack using the second mask, for a second semiconductor optical device defined by the second portion of the second mask Forming a second waveguide mesa of
The width of the second portion of the first mask is monotonously wide in the direction of the predetermined axis,
The width of the second portion of the second mask is narrower than the width of the second portion of the first mask. The direction of the predetermined axis is the [011] direction,
The second portion of the first mask has a tapered shape defined by a straight line inclined at a predetermined angle with respect to the direction of the predetermined axis;
The method of claim 1, wherein the predetermined angle is 30 degrees or less.

Images