JP2011151061A - Method of manufacturing semiconductor device - Google Patents

Abstract

In a three-dimensional layout transistor, a single bit line between adjacent pillars is provided to achieve miniaturization.
A bit line formed between first and second semiconductor pillars adjacent to each other via a first insulating film, and a side surface of the first semiconductor pillar and the first bit line are formed. In the method of manufacturing a semiconductor device comprising the conductor 10 that electrically connects the first bit line and the first semiconductor pillar, a first side surface of the first semiconductor pillar that connects the conductor 10 is provided. In order to remove the insulating film 7, the protective film is left on the side surface of the second semiconductor pillar, and the first insulating film 7 on the bit line 8 is selectively removed, or the protective film is left on the side surface of the second semiconductor pillar. At this time, the first insulating film 7 on the bit line 8 is removed.
[Selection] Figure 8

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bit line of a three-dimensional layout transistor.

  Although the occupied area of a transistor has been reduced along with higher integration of a semiconductor device, a method of making a vertical transistor having a three-dimensional layout has been proposed because the planar layout is becoming a limit.

  When a vertical transistor using a silicon pillar is used as a cell transistor of a semiconductor memory device, one of diffusion layers serving as a source or drain is connected to a bit line, and the other is connected to a memory element (a cell capacitor in a DRAM). It is common. Usually, since a memory element such as a cell capacitor is disposed above a cell transistor, the memory element is connected to the upper part of the silicon pillar, and a bit line is connected to the lower part of the silicon pillar.

  Here, since the lower part of the silicon pillar is a semiconductor substrate, in order to form a bit line here, it is necessary to embed the bit line inside the substrate.

  For example, Patent Document 1 shows a structure in which one embedded bit line is formed between adjacent silicon pillars and is connected only to one of the adjacent pillars. Here, the buried bit line is formed in a two-stage structure in a bit trench formed by further engraving between silicon pillars (silicon fins), so that the lower bit line is made of a low resistance material such as metal or metal silicide. . Then, in order to connect the upper bit line to the silicon pillar, the connection silicon pillar side insulating film in the bit trench is selectively removed, and the lower bit line made of silicon material such as impurity-doped polysilicon is used to reduce the low resistance of the lower layer. The bit line and the silicon pillar are connected.

On the other hand, as a method for removing an oxide film, Patent Document 2 includes a halogen salt by activating at least one of a gas containing a halogen element and a basic gas outside the reaction vessel and supplying the gas into the reaction vessel. A method for removing an oxide film by a reaction between a gas and an oxide film is disclosed. For example, in the removal of the silicon oxide film, when a mixed gas of NF ₃ and NH ₃ is used and the partial pressure of NH ₃ becomes larger than the partial pressure of NF ₃ , a thin film is formed on the silicon oxide film. The thin film can be easily sublimated and removed by heating to about 100 ° C., which is higher than the sublimation temperature.

JP 2009-10366 A JP-A-2-256235

  Patent Document 1 proposes a method of etching in a state where the other side wall of the bit trench is covered with a photoresist in order to selectively remove the silicon oxide film formed on one side wall of the bit trench. However, in order to cover the other side surface with the photoresist, the photoresist is exposed and developed. However, if the distance between adjacent silicon pillars is further reduced for miniaturization, the adjacent silicon pillars are exposed. The aspect ratio of the grooves formed between them becomes higher. For this reason, it is becoming difficult to form a photoresist having a constant thickness up to the bottom of the groove having a high aspect ratio. As a result, the photoresist at the bottom of the trench remains, so that the removal of the silicon oxide film on the side wall of the bit trench to be removed becomes incomplete, and the contact resistance increases, or conversely, In some cases, the photoresist is also removed, and there is a problem that a normal contact cannot be formed.

According to the first embodiment of the present invention,
Forming first and second semiconductor fins separated by a first groove;
Forming a sidewall film on the side surfaces of the first and second semiconductor fins;
Forming a second groove at the bottom of the first groove using the sidewall film as a mask;
Forming a silicon oxide film on the surface of the second groove;
Forming a bit line whose side and bottom are surrounded by the silicon oxide film;
After filling the first and second grooves on the bit line with an organic film, the organic film on the side surface of the second semiconductor fin not connected to the bit line is left and the side surface of the first semiconductor fin connecting the bit line is connected Removing the organic film to expose a part of the silicon oxide film and at least a part of the bit line surface;
Using the remaining organic film as an etching mask, the exposed silicon oxide film is etched using a mixed gas containing nitrogen, hydrogen, and fluorine under irradiation of inert gas ions, and a part of the first semiconductor fin Exposing the surface;
And a step of forming a conductor that electrically connects the exposed portion of the first semiconductor fin and the exposed portion of the bit line.

According to the second embodiment of the present invention,
Forming first and second semiconductor fins separated by a first groove;
Forming a first sidewall film on the side surfaces of the first and second semiconductor fins, and further forming a second sidewall on the first sidewall;
Forming a second groove at the bottom of the first groove using the sidewall film as a mask;
Forming a first insulating film on a surface of the second groove;
Forming a bit line having side and bottom surfaces surrounded by the first insulating film;
After filling the first and second grooves on the bit line with a protective film, the protective film on the side surface of the second semiconductor fin not connected to the bit line is left and the side surface of the first semiconductor fin connecting the bit line When removing at least part of the protective film, the second sidewall film on the side surface of the first semiconductor fin on the side where the bit line is connected is removed at the same time, and part of the first insulating film is removed. Exposing at least a portion of the bitline surface;
Etching the exposed first insulating film using the remaining protective film as an etching mask to expose a partial surface of the first semiconductor fin;
And a step of forming a conductor that electrically connects the exposed portion of the first semiconductor fin and the exposed portion of the bit line.

  A first bit line formed between adjacent first and second semiconductor pillars; a side surface of the first semiconductor pillar; and a first bit line formed on the first bit line; In connection with the manufacture of a three-dimensional layout transistor comprising a conductor electrically connected to a first semiconductor pillar, in order to connect a bit line to one of the adjacent pillars, the entire pillar side surface is covered with a first insulating film. It is necessary to remove only the first insulating film on the side surface that covers and connects the bit lines. However, since the etching proceeds isotropically in wet etching, only the insulating film on one side surface portion is anisotropically removed. It becomes difficult.

  However, the method according to the first embodiment of the present invention is particularly effective when the device area is further reduced because only the exposed first insulating film can be selectively removed instead of isotropic wet etching. At the same time, when the element areas are the same, the pillar dimensions can be increased by increasing the aspect ratio of the trench from which the side oxide film is removed. Increasing the pillar size in the three-dimensional layout transistor has the effect of increasing the channel width and improving the device characteristics.

  Further, in the method according to the second embodiment of the present invention, in order to remove a part of the side wall insulating film formed in the first groove on the bit line connecting side, the pillar on the side not connecting the bit line is removed. A thick protective film (insulating film) can be left on the side surface, and even if wet etching progresses isotropically, sufficient etching time can be secured until the protective film on the side surface of the pillar not connected to the bit line is removed, By controlling the time, it is possible to stably remove the first insulating film to be removed from the side surface of the pillar connected to the bit line.

1A and 1B are perspective views of a semiconductor device according to the present invention, in which FIG. 1A shows a capacitor portion at the top of a pillar, and FIG. 2B shows a configuration of the pillar portion. It is process sectional drawing explaining the manufacturing process of a 1st Example. FIG. 3 is a top view after the step of FIG. 2. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 1st Example. It is process sectional drawing explaining the manufacturing process of a 2nd Example. It is process sectional drawing explaining the manufacturing process of 2nd Example, (b) is the elements on larger scale of (a). It is process sectional drawing explaining the manufacturing process of a 2nd Example. It is process sectional drawing explaining the manufacturing process of a 2nd Example. It is process sectional drawing explaining the manufacturing process of a 2nd Example. It is process sectional drawing explaining the manufacturing process of a 2nd Example. It is process sectional drawing explaining the manufacturing process of a 2nd Example. It is process sectional drawing explaining the manufacturing process of a 2nd Example.

  FIG. 1 is a schematic perspective view of a cell portion of a DRAM (Dynamic Random Access Memory) having a three-dimensional layout structure. FIG. 1A shows a capacitor on a pillar 101 formed by digging a silicon substrate as a semiconductor substrate. FIG. 2B shows the pillars in the insulating film and the surrounding conditions when the insulating film 100 in FIG. 1A is seen through. That is, in FIG. 5B, the unit cell of the transistor is composed of one pillar, one bit line, and two word lines. For example, in the pillar A (PA), a bit line 1 (BL1) and word lines 1 (WL1) and 2 (WL2) constitute a unit cell. Similarly, pillar B (P-B) is bit line 1 (BL1) and word lines 3 (WL3) and 4 (WL4), and pillar C (PC) is bit line 2 (BL2) and word line 1 ( WL1) and 2 (WL2), and the pillar D (P-D) form a unit cell with the bit line 2 (BL2) and the word lines 3 (WL3) and 4 (WL4). The word lines 2 and 3 are separated by an insulating film. In the configuration shown in the figure, a double gate structure in which two word lines are arranged in one pillar is used, but the bit line is connected to only one side of each pillar. Therefore, it is important that the bit line is not connected to the pillar on the opposite side to the connection side by an insulating film (silicon oxide film), and the bit line is connected after forming the silicon oxide film in the groove between the silicon pillars. It is necessary to open the silicon oxide film on the pillar side. Although a double gate structure is used here, a surround gate structure in which all pillar side surfaces are covered with a gate may be used.

  Hereinafter, examples of the present invention will be described with reference to the drawings. However, the present invention is not limited to these examples, and may be appropriately changed / modified within the scope of the present invention. Is.

Example 1
A first embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 2, a silicon substrate 1 in which an active region is formed (not shown) by an isolation insulating film is used as an etching hard mask ₂ with a lower layer mask 2a which is SiO ₂ having a thickness of 9 nm from the lower layer, and SiN having a thickness of 180 nm. An intermediate layer mask 2b, an upper layer mask 2c made of SiO ₂ with a thickness of 50 nm are formed, and a mask 3 made of amorphous carbon with a thickness of 200 nm is further laminated, and then patterning of the hard mask 2 is performed by photolithography and dry etching. . FIG. 3 is a top view after the step of FIG.

Next, as shown in FIG. 4, the remaining mask 3 is removed by ashing, and then the depth Y1 = 120 nm and the width X1 = on the silicon substrate 1 by dry etching using the hard mask 2 as an etching mask. When the 38 nm first-stage groove 4a is formed, the silicon fin 1a is completed.
At this time, the remaining film thickness of the upper mask 2c is 33 nm, and the film thickness is reduced by 12 nm.
As a result, the groove depth Y2 including the hard mask 2 is 342 nm (= 33 + 180 + 9 + 120).

As shown in FIG. 5, an insulating film 5 made of SiO ₂ having a thickness of 5 nm is formed on the side surface of the groove 4a by radical oxidation. Here, 2.5 nm thick silicon is oxidized from the surface of the silicon substrate 1 to a thickness of 5 nm, so that the increase in film thickness is 2.5 nm, and the SiN surface of the intermediate layer mask 2b is also _{2 to 3} nm of SiO _2. A film 5 'is formed. Further, a silicon nitride film (SiN) is formed on the insulating film 5 and etched back, thereby forming the SiN sidewall 6 with a thickness of 8 nm. Thereafter, a second groove 4b having a depth Y3 = 100 nm and a width X2 = 17 nm (= 38−2 × (2.5 + 8)) is further formed in the silicon substrate 1 by dry etching.
As a result, the total depth Y4 of the first-stage groove 4a and the second-stage groove 4b is 220 nm, and the remaining film thickness of the upper mask 2c is reduced by 10 nm to 23 nm. Therefore, the groove depth including the etching mask 2 is increased. The length Y5 is 432 nm (= 342-10 + 100).

As shown in FIG. 6, a first insulating film 7 made of SiO ₂ having a thickness of 4 nm is formed on the side surface of the second-stage trench 4b by radical oxidation. Here, since the silicon having a thickness of 2 nm is oxidized from the surface of the silicon substrate 1 to a thickness of 4 nm, the increase in the film thickness is 2 nm, and the SiO ₂ film 7 ′ having a thickness of 2 to 3 nm is also formed on the SiN surface of the sidewall 6. To do. Further, DOPOS is formed and etched back to form a bit line 8 having a thickness T1 = 70 nm on the bottom surface of the groove of the silicon substrate.
Here, the width X3 in the second-stage groove 4b is 13 nm (= 17−2 × 2),
The remaining film thickness of the upper mask 2c is 23 nm without any film reduction.
The groove depth Y6 including the etching mask is 360 nm (= 432-2-70).

  As shown in FIG. 7, an organic film 9 is formed on the upper layer mask 2c, and the organic film on the silicon fin 1a side connecting the bit lines 8 is removed with a width of 8 nm by photolithography and dry etching. The aspect ratio at this time is 45 (= 360/8).

The organic film 9 at this time is preferably a novolak-based BARC material (Bottom Anti-Reflection Coating) from the selection ratio, and the dry etching conditions are as follows in a parallel plate type reactive ion etching (RIE) apparatus:
Power: 1000W
Pressure: 6.7 Pa (50 mTorr)
Stage temperature: 40 ° C
End of processing: 20% overetch,
Etching gas: ammonia NH ₃ (500 sccm).

  Here, the organic film 9 remains with a thickness of 7 nm (= 17−2−8) on the side surface of the second-stage groove 4b on the side where the bit line is not connected.

As shown in FIG. 8, after introducing reactive gases [ammonia (50 sccm) and hydrogen fluoride (50 sccm)] into the etching chamber at a pressure of 6.7 Pa (50 mTorr), dry etching is performed to form the bit line 8. The first insulating film 7 on the side of the silicon fin 1a to be connected is removed. The dry etching conditions at this time are as follows:
Power: 1500 / 1000W,
Pressure: 4 Pa (30 mTorr)
Etching gas: Argon Ar (500 sccm).

Here, the reaction gas may be a mixed gas containing nitrogen, hydrogen, and fluorine. For example, a mixed gas of hydrogen and nitrogen trifluoride (NF ₃ ) can be used, and the etching gas is an inert gas He, Ne, Kr, and Xe can also be used.

The removal of the first insulating film 7 which is SiO ₂ during dry etching proceeds according to the following reaction formula.
SiO ₂ + 4HF → SiF ₄ + 2H ₂ O
SiF ₄ + 2NH ₃ + 2HF → (NH ₄ ) ₂ SiF ₆

Since ammonium silicofluoride _{[(NH 4) 2 SiF 6} ] is fixed to the SiO ₂ surface, the SiO ₂ surface is covered with ammonium fluorosilicate, removal of SiO ₂ is stopped without proceeding the reaction. However, since ammonium silicofluoride is decomposed and sublimed by heating at about 100 to 200 ° C., the first insulating film 7 made of SiO ₂ can be continuously removed by heat treatment. On organic film 9 also because the reaction does not proceed, it is not the first insulating film 7 organic film 9 is SiO ₂ underlayer in reduced film is exposed, the flat SiO _2, such as further mask portions Since the Ar plasma reaches the surface of the SiO ₂ to inhibit the reaction, the flat SiO ₂ is not removed. Accordingly, even in a situation where the aspect ratio is high and excessive overwetting etching is difficult, only the first insulating film on the side surface connecting the bit lines can be removed by the above-described method.

  As shown in FIG. 9, the organic film 9 is removed by ashing, and a conductor 10 made of epitaxial silicon is grown to a thickness of 30 nm from the exposed silicon surface of the silicon fin 1a.

As shown in FIG. 10, the SiO ₂ film 7 ′ on the sidewall 6 is removed by the same dry etching method as in FIG. Again, the SiO ₂ film 5 ′ on the mask SiN film 2b remains without being removed.

As shown in FIG. 11, the sidewall 6 is removed by wet etching. In this case the intermediate layer mask. 2b, are covered by the SiO ₂ of the SiO ₂ film 5 'and the upper mask 2c generated during radical oxidation, it remains as it is. After that, as shown in FIG. 12, the trenches 4a and 4b including the hard mask 2 are filled with the second insulating film 11 made of SiO ₂ , and the second insulating layer is excessive by CMP processing using the intermediate layer mask 2b as an etch stopper. The film 11 is removed.

  Thus, the bit line is completed, and then the process moves to the formation of the word line.

  In the above embodiment, it is particularly effective when the element area is further reduced, and when the element area is the same, the aspect ratio of the groove for removing the side oxide film can be increased to increase the silicon fin dimension. It becomes possible. The expansion of the silicon fin size in the three-dimensional layout transistor has the effect of increasing the channel width and improving the device characteristics.

(Example 2)
A second embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 13, a lower layer mask that is a silicon oxide film (SiO ₂ ) having a thickness of 9 nm from the lower layer as a hard mask 2 for etching on a silicon substrate 1 in which an active region is formed (not shown) by an isolation insulating film. 2a, an intermediate layer mask 2b which is a 180 nm thick silicon nitride film (SiN), and an upper layer mask 2c which is a 50 nm thick SiO ₂ film are formed and formed on the silicon substrate 1 by photolithography and dry etching in the same manner as in the first embodiment. When the first stage groove 4a having the depth Y7 = 120 nm and the width X6 = 63 nm is formed, the silicon fin 1a is completed. At this time, the remaining film thickness of the upper layer mask 2c is 33 nm, and the film thickness is reduced by 12 nm. As a result, the depth Y8 of the groove 4a including the hard mask 2 is 342 nm.

Next, as shown in FIG. 14, an insulating film 5 of SiO ₂ having a thickness of 5 nm is formed on the silicon substrate 1 exposed in the trench 4a by radical oxidation. Here, 2.5 nm thick silicon is oxidized from the surface of the silicon substrate 1 to a thickness of 5 nm, so that the increase in film thickness is 2.5 nm, and the SiN surface of the intermediate layer mask 2b is also _{2 to 3} nm of SiO _2. A film 5 'is formed. Further, an oxygen-containing silicon nitride film (SiON) is formed on the insulating film 5 and etched back to form a SiON sidewall film 6 having a thickness of 8 nm. The SiON of the sidewall film 6 is a low pressure CVD method, (a) a 1.5 nm-thick sidewall film 6a is formed under process conditions that increase the nitrogen content, and (b) a process that increases the oxygen content. A sidewall film 6b having a thickness of 6.5 nm is formed by changing the conditions. By such a change in the conditions, as shown in the partially enlarged view of FIG. 14B, the sidewall film 6a on the side close to the silicon pillar 1a has a high nitrogen content, and a sidewall having a high oxygen content thereon. A film 6b is laminated.

For example, the above process conditions (a) and (b) are as follows.
Process conditions of (a) (element ratio: N / O = 2/1)
Pressure: 165Pa
Etching gas: dichlorosilane (100 sccm) / ammonia (100 sccm) / nitrous oxide (50 sccm)
Carrier gas: N ₂ (250 sccm)
Film formation time: 6 minutes (b) process conditions (element ratio: N / O = 2/3)
Pressure: 165Pa
Etching gas: dichlorosilane (100 sccm) / ammonia (10 sccm) / nitrous oxide (50 sccm)
Carrier gas: N ₂ (250 sccm)
Deposition time: 44 minutes

  As a result, the width X5 in the first-stage silicon trench is 42 nm (= 63−2 × (2.5 + 8)). Although SiON on the hard mask 2 and the bottom of the groove 4a is removed during the etch back of the sidewall film 6, there is no film reduction of the upper layer mask 2c and the silicon substrate 1, and the groove depth including the hard mask 2 is reduced. Y9 is 342 nm.

  Next, as shown in FIG. 15, a second-stage trench 4b having a depth Y10 = 100 nm and a width X6 = 42 nm is further formed in the silicon substrate 1 by dry etching using the sidewall film 6 as a mask. As a result, the total depth Y11 of the silicon substrate is 220 nm. At this time, the remaining film thickness of the upper mask 2c was reduced by 10 nm to 23 nm, and the groove depth Y12 including the etching mask 2 was 432 nm (= 342-10 + 100).

As shown in FIG. 16, a first insulating film 7 of SiO ₂ having a thickness of 4 nm is formed on the side surface of the second-stage trench 4b by radical oxidation. Here, since the silicon having a thickness of 2 nm is oxidized from the surface of the silicon substrate 1 to a thickness of 4 nm, the increase in the film thickness is 2 nm, and a SiO ₂ film 7 ′ having a thickness of 2 to 3 nm is also formed on the SiON surface of the sidewall 6b. To do. Further, a bit line 8 having a thickness T3 = 70 nm is formed in the groove 4b by forming a DOPOS (Doped Poly Silicon) film and then etching back.
Here, the width X7 in the second-stage groove 4b is 38 nm (= 42-2 × 2),
The remaining film thickness of the upper mask 2c is 23 nm without any film reduction.
The groove depth Y13 including the etching mask is 360 nm (= 432-2-70).

As shown in FIG. 17, as the protective film 12, the groove 4 including the hard mask 2 is filled with a coating insulating material (SOD: Spin On Dielectrics), and then the intermediate layer mask 2 b of the hard mask 2 is used as a stopper film. The unnecessary protective film 12 is removed by performing CMP (Chemical Mechanical Polishing).
Here, the remaining film thickness of the upper mask 2c is reduced to 23 nm by 23 nm and disappears by CMP.
Further, the groove depth Y14 including the etching mask is 337 nm (= 360-23).

  As shown in FIG. 18, after forming a mask 13 made of amorphous carbon having a thickness of 200 nm on the entire surface of the wafer, patterning of the amorphous carbon mask 13 is performed by photolithography and dry etching. Further, the SOD 12 and the sidewalls 6 on the silicon fin 1a side connecting the bit lines 8 are removed with a width of 24 nm by dry etching. The aspect ratio at this time is 14 (≈337 / 24).

The dry etching conditions at this time are as follows: the target film is SiO ₂ (including the SOD of the protective film 12), and in a dual frequency parallel plate reactive ion etching (RIE) apparatus (RIE: Reactive Ion Etching)
Power: 1500 / 5000W,
Pressure: 2 Pa (15 mTorr),
Etching gas: hexafluoro-1,3-butadiene (50 sccm) / argon (500 sccm) / oxygen (50 sccm),
Etching time: 60 seconds. As described above, since the SiON film constituting the sidewall film 6 is formed by stacking layers having different oxygen and nitrogen contents, the sidewall 6b, which is SiON having a large oxygen content, is almost the same as SiO ₂ . Although it can be removed under the above dry etching conditions, the sidewall 6a which is SiON having a high nitrogen content cannot be removed and remains. Accordingly, the thickness of the sidewall 6 on the fin side surface of the groove 4a on the side to which the bit line 8 is connected is reduced to 1.5 nm on the thickness of the sidewall 6a. Therefore, the first insulating film 7 on the removal side in the fin of the groove 4b. Are all exposed to a dry etching gas. However, the first insulating film cannot be completely removed due to the variation in the shape of the groove 4b, and remains with a thickness of about 1 nm. The film thickness of the SOD 12 to be left protected by the amorphous carbon mask 13 remains with a thickness of 20 nm (= 42 + 2-24).

  Next, wet etching is performed in order to completely remove the first insulating film 7 on the removal side, but the film is removed in a wet etching time of about 10 seconds by securing the film thickness of the protective film 12 on the remaining side. Only the first insulating film 7 on the side can be removed.

  As shown in FIG. 19, the remaining amorphous carbon mask 13 is removed by ashing. Thereafter, a conductor 10 which is selective epitaxial silicon is grown on the exposed side surface of the silicon pillar with a thickness T4 = 30 nm, and the silicon pillar 1a and the bit line 8 are connected.

As shown in FIG. 20, a part of the conductor 10 that is selective epitaxial silicon is reformed by thermal oxidation to a third insulating film 14 that is SiO ₂ having a thickness T5 = 20 nm, and the formation of the bit line is completed. .

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1a Silicon fin 2 Hard mask 2a Lower layer mask 2b Middle layer mask 2c Upper layer mask 3, 13 Mask 4 Groove 4a Groove 4b Groove 5 Insulating film 6 Side wall film 6a Side wall film 6b Side wall film 7 First insulating film 8 Bit line 9 Organic film 10 Conductor 11 Second insulating film 12 Protective film (SOD)
14 Third insulating film

Claims (7)

Forming first and second semiconductor fins separated by a first groove;
Forming a sidewall film on the side surfaces of the first and second semiconductor fins;
Forming a second groove at the bottom of the first groove using the sidewall film as a mask;
Forming a silicon oxide film on the surface of the second groove;
Forming a bit line whose side and bottom are surrounded by the silicon oxide film;
After filling the first and second grooves on the bit line with an organic film, the organic film on the side surface of the second semiconductor fin not connected to the bit line is left and the side surface of the first semiconductor fin connecting the bit line is connected Removing the organic film to expose a part of the silicon oxide film and at least a part of the bit line surface;
Using the remaining organic film as an etching mask, the exposed silicon oxide film is etched using a mixed gas containing nitrogen, hydrogen, and fluorine under irradiation of inert gas ions, and a part of the first semiconductor fin Exposing the surface;
Forming a conductor that electrically connects the exposed portion of the first semiconductor fin and the exposed portion of the bit line.   2. The method for manufacturing a semiconductor device according to claim 1, wherein the mixed gas containing nitrogen, hydrogen, and fluorine is a mixed gas of ammonia and hydrogen fluoride or a mixed gas of hydrogen and nitrogen trifluoride.   The method for manufacturing a semiconductor device according to claim 1, wherein the inert gas ions are ions of at least one inert gas of argon, helium, neon, krypton, and xenon. Forming first and second semiconductor fins separated by a first groove;
Forming a first sidewall film on the side surfaces of the first and second semiconductor fins, and further forming a second sidewall on the first sidewall;
Forming a second groove at the bottom of the first groove using the sidewall film as a mask;
Forming a first insulating film on a surface of the second groove;
Forming a bit line having side and bottom surfaces surrounded by the first insulating film;
After filling the first and second grooves on the bit line with a protective film, the protective film on the side surface of the second semiconductor fin not connected to the bit line is left and the side surface of the first semiconductor fin connecting the bit line When removing at least part of the protective film, the second sidewall film on the side surface of the first semiconductor fin on the side where the bit line is connected is removed at the same time, and part of the first insulating film is removed. Exposing at least a portion of the bitline surface;
Etching the exposed first insulating film using the remaining protective film as an etching mask to expose a partial surface of the first semiconductor fin;
Forming a conductor that electrically connects the exposed portion of the first semiconductor fin and the exposed portion of the bit line.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the protective film is a silicon oxide film, and the second sidewall film is a silicon oxynitride film having a high oxygen content.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the etching of the first insulating film is isotropic etching.   The method for manufacturing a semiconductor device according to claim 4, wherein the conductor is formed without removing the remaining protective film after the etching of the first insulating film.