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JP2011151048A - Method of manufacturing electronic component, and electronic component - Google Patents

Method of manufacturing electronic component, and electronic component Download PDF

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Publication number
JP2011151048A
JP2011151048A JP2008125539A JP2008125539A JP2011151048A JP 2011151048 A JP2011151048 A JP 2011151048A JP 2008125539 A JP2008125539 A JP 2008125539A JP 2008125539 A JP2008125539 A JP 2008125539A JP 2011151048 A JP2011151048 A JP 2011151048A
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Prior art keywords
electronic component
ceramic substrate
wiring pattern
insulating resin
resin sheet
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JP2008125539A
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Japanese (ja)
Inventor
Yoshitake Hayashi
林  祥剛
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Panasonic Corp
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Panasonic Corp
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Priority to JP2008125539A priority Critical patent/JP2011151048A/en
Priority to PCT/JP2009/001900 priority patent/WO2009139121A1/en
Publication of JP2011151048A publication Critical patent/JP2011151048A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H10W72/0198
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10636Leadless chip, e.g. chip capacitor or resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H10W74/15
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component which has superior shock resistance and highly reliable electric connection of an inner via and secondary mounting in laminate structure including a ceramic substrate. <P>SOLUTION: A method of manufacturing the electronic component in which, from both sides of a laminate formed by laminating a ceramic substrate, an insulating resin sheet made of a conductive resin composition and having via conductors, and a multilayer circuit substrate or a metal foil, pressurizing force is impressed while heating the laminate through ceramic bases to cure the insulating resin sheet, thereby obtaining a precursor, and dividing the precursor to manufacture the electronic component, is used. The electronic component having insulating resins formed on both surfaces of the ceramic substrate is also used. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、セラミック基板と樹脂材料との異種材料を積層した部品内蔵構造を有する電子部品とその製造方法に関する。   The present invention relates to an electronic component having a component built-in structure in which different kinds of materials of a ceramic substrate and a resin material are laminated, and a method for manufacturing the same.

半導体チップを中心とする電子部品が実装された電子部品モジュールは、情報通信機器、事務用電子機器、家庭用電子機器、医療用電子機器などの、小型化、薄型化、高性能化に大きく寄与している。特に、情報通信機器の分野での小型化、薄型化の要求に対し、半導体チップ等の電子部品の実装密度をより高めるために、電子部品の電極ピッチおよび電子部品を実装する配線基板の配線ルールの微細化が益々進んでいる。   Electronic component modules on which electronic components, mainly semiconductor chips, are mounted greatly contribute to miniaturization, thinning, and high performance of information communication devices, office electronic devices, household electronic devices, medical electronic devices, etc. is doing. In particular, in response to the demand for miniaturization and thinning in the field of information communication equipment, in order to further increase the mounting density of electronic components such as semiconductor chips, the wiring pitch of the wiring board for mounting the electronic component electrode pitch and electronic components. The miniaturization is progressing more and more.

最近では、配線基板の表面に電子部品を実装する従来の2次元的な実装だけでなく、配線基板に電子部品を内蔵し、実装面積を大幅に縮小し、小型高密度化を図る3次元的な実装方法を用いた部品内蔵モジュールの開発も盛んに行われている。   Recently, in addition to the conventional two-dimensional mounting in which electronic parts are mounted on the surface of the wiring board, the electronic parts are built in the wiring board, and the mounting area is greatly reduced, and the three-dimensional structure is aimed at reducing the size and increasing the density. Development of built-in component modules using various mounting methods is also actively underway.

また、半導体チップ等の電子部品をパソコンや携帯電話等の電子機器のマザー基板に実装する場合、微細な配線ルールの電子部品と電子部品に対して配線ルールが比較的粗なマザー基板との配線ルールの調整を図るために、インターポーザー基板やモジュール基板と呼ばれる配線基板に電子部品を実装した後、半田ボールを用いたBGA(Ball grid array)実装や電極部半田印刷によるLGA(Land gird array)実装によってマザー基板に二次実装するといった段階的な実装形態が採られることが多い。このマザー基板には通常、樹脂基板が使用されることが多いが、インターポーザー基板やモジュール基板には電子部品およびマザー基板の配線ルール、必要とされる基板の面積や厚さ、および電子部品の放熱性等さまざまな観点から樹脂基板もしくはセラミック基板が選択されて用いられている。ここでインターポーザー基板やモジュール基板としてセラミック基板を用いた場合、セラミック基板とマザー基板との熱膨張係数が大きく異なるため、二次実装部分に大きな応力がかかり、例えばBGA実装の半田ボールにクラックが発生する等の電気接続不良が発生することがあった。この様な異種材料を用いることに起因する不良発生に対し、セラミック材料で構成されるインターポーザー基板またはモジュール基板の、マザー基板実装面に樹脂層を形成することで応力を緩和させ不良発生を防ぐ方法(特許文献1)が提案されている。
特開2003−124435号公報
In addition, when mounting electronic components such as semiconductor chips on a mother board of an electronic device such as a personal computer or a mobile phone, wiring between the electronic parts with fine wiring rules and the mother board with relatively coarse wiring rules for the electronic parts In order to adjust the rules, electronic components are mounted on a wiring board called an interposer board or module board, and then BGA (Ball Grid Array) mounting using solder balls or LGA (Land Guard Array) by electrode part solder printing. In many cases, stepwise mounting forms such as secondary mounting on a mother board are adopted. Resin substrates are usually used for this mother board, but wiring rules for electronic components and mother boards, required board area and thickness, and electronic component wiring are often used for interposer boards and module boards. A resin substrate or a ceramic substrate is selected and used from various viewpoints such as heat dissipation. Here, when a ceramic substrate is used as an interposer substrate or a module substrate, the thermal expansion coefficients of the ceramic substrate and the mother substrate are greatly different, so that a large stress is applied to the secondary mounting portion, for example, a crack is generated in a solder ball of BGA mounting. An electrical connection failure such as occurrence may occur. In response to the occurrence of defects due to the use of such dissimilar materials, by forming a resin layer on the mother substrate mounting surface of an interposer substrate or module substrate made of a ceramic material, stress can be relieved and defects can be prevented. A method (Patent Document 1) has been proposed.
JP 2003-124435 A

しかし、特許文献1に開示されている方法には、マザー基板への二次実装する前のセラミック基板と樹脂基板との異種積層接続構造の状態において、二次実装する面に反りがないことが求められる。セラミック基板は剛性が高く樹脂基板との異種積層接続構造において反りの発生は少ないが、反りが発生しにくい分、応力を内在的に含んでいることが多い。この内部応力が大きくなると、例えば一気にセラミック基板の欠け、割れ等の破損に繋がるといった様々な問題の原因となることが多かった。そのため、セラミック基板と樹脂基板の異種積層接続構造において、特許文献1に開示されているようにセラミック基板に樹脂層を形成する構造によって、樹脂面同士の接続により応力緩和をする方法がある。しかし、セラミック基板に直接樹脂層を形成する積層構造では、BGA実装やLGA実装のように極小的なグリッドパターン接続ではなく全面接着となるため、熱膨張係数の差によって大きな反りが発生することでマザー基板への二次実装性を著しく損なうことになる。セラミック基板の厚さと樹脂層の厚さの関係によっても、異種積層構造に起因する内部応力や反りは変化しやすいため、どのような異種積層構造においても、マザー基板への二次実装の信頼性を高いものにすることは非常に困難であった。   However, in the method disclosed in Patent Document 1, there is no warp on the secondary mounting surface in the state of the heterogeneous stacked connection structure of the ceramic substrate and the resin substrate before the secondary mounting on the mother substrate. Desired. A ceramic substrate has high rigidity and generates little warpage in a heterogeneous laminated connection structure with a resin substrate, but often contains stress inherently because warpage hardly occurs. When this internal stress increases, it often causes various problems such as breakage such as chipping and cracking of the ceramic substrate all at once. Therefore, in a heterogeneous laminated connection structure of a ceramic substrate and a resin substrate, there is a method of relaxing stress by connecting resin surfaces by a structure in which a resin layer is formed on a ceramic substrate as disclosed in Patent Document 1. However, in the laminated structure in which the resin layer is directly formed on the ceramic substrate, since the entire surface is bonded instead of the minimum grid pattern connection as in BGA mounting and LGA mounting, a large warp occurs due to the difference in thermal expansion coefficient. Secondary mountability on the mother board will be significantly impaired. Depending on the relationship between the thickness of the ceramic substrate and the thickness of the resin layer, the internal stress and warpage caused by the heterogeneous multilayer structure are likely to change, so the reliability of the secondary mounting on the mother board in any heterogeneous multilayer structure It was very difficult to make the price high.

以下に、図13(a)〜図13(e)と図14と図15を用いて従来の電子部品の製造方法と電子部品について説明する。   Hereinafter, a conventional method for manufacturing an electronic component and an electronic component will be described with reference to FIGS. 13 (a) to 13 (e), 14 and 15. FIG.

図13(a)において、セラミック基板301の配線パターン302aに回路部品311bと311cを実装したセラミック基板333と、導電性樹脂組成物にて構成されるビアホール導体334を形成した絶縁性樹脂シート335と、転写形成材のキャリア層323上に転写形成材の配線パターン324が形成された転写シート325を準備する。ビアホール導体334で、セラミック基板の配線パターン302aと転写形成材の配線パターン324を電気接続するように位置合わせを行い積層する。図13(b)〜図13(e)に示す様に、上述の積層体を熱プレス装置にて加圧加熱することで、絶縁性樹脂シートを熱硬化して積層体を一体化する。356は金属プレート、352はクッション材、353は熱プレス機の加熱プレートである。更に、ぞの後、セラミック基板の配線パターン302b上に回路部品311aと半導体チップまたは半導体パッケージなどの半導体素子312を実装した後、転写シートのキャリア層を剥離して電子部品の前駆体343(図14)を作製する。電子部品の前駆体343を切断ライン355に沿って切断して個片に分割することで電子部品を作製する。しかし、加圧加熱する際にセラミック基板と絶縁性樹脂シートや転写シートあるいは樹脂多層基板との異種積層構造による熱膨張係数差によって図15に示す様にビアホール導334に歪みが発生し、配線パターンとの位置合わせずれにより、信頼性の高い接続を得ることができなかった。また、異種積層構造による熱膨張係数差によって反りの発生も大きく、100×100mmサイズで5〜8mm程度の反りが発生していた。   In FIG. 13A, a ceramic substrate 333 in which circuit components 311b and 311c are mounted on a wiring pattern 302a of the ceramic substrate 301, an insulating resin sheet 335 in which a via-hole conductor 334 made of a conductive resin composition is formed, Then, a transfer sheet 325 in which a wiring pattern 324 of the transfer forming material is formed on the carrier layer 323 of the transfer forming material is prepared. The via hole conductor 334 is aligned and laminated so that the wiring pattern 302a of the ceramic substrate and the wiring pattern 324 of the transfer forming material are electrically connected. As shown in FIG. 13B to FIG. 13E, the laminated body is integrated by thermosetting the insulating resin sheet by pressurizing and heating the above-described laminated body with a hot press apparatus. 356 is a metal plate, 352 is a cushioning material, and 353 is a heating plate of a hot press machine. Further, after mounting the circuit component 311a and the semiconductor element 312 such as a semiconductor chip or a semiconductor package on the wiring pattern 302b of the ceramic substrate, the carrier layer of the transfer sheet is peeled off and the electronic component precursor 343 (FIG. 14) is produced. The electronic component precursor 343 is cut along the cutting line 355 to be divided into individual pieces, thereby producing the electronic component. However, when heated under pressure, the via hole conductor 334 is distorted as shown in FIG. 15 due to the difference in thermal expansion coefficient due to the different laminated structure of the ceramic substrate and the insulating resin sheet, transfer sheet, or resin multilayer substrate. Due to the misalignment, a reliable connection could not be obtained. Further, the warpage is greatly generated due to the difference in thermal expansion coefficient between the different laminated structures, and the warpage of about 5 to 8 mm occurs in the size of 100 × 100 mm.

本発明はかかる点に鑑みてなされたものであり、その主な目的は、セラミック基板を含む電子部品の異種積層構造に起因するビアホール導体334の歪みや反りの発生を抑制し、電子部品のマザー基板への二次実装の電気的接続信頼性を向上させる技術を提供することにある。   The present invention has been made in view of the above points, and its main object is to suppress the generation of distortion and warpage of the via-hole conductor 334 due to the heterogeneous multilayer structure of the electronic component including the ceramic substrate, and to prevent the mother of the electronic component. An object of the present invention is to provide a technique for improving the electrical connection reliability of secondary mounting on a substrate.

本発明の電子部品の製造方法は、少なくとも一方の主面の配線パターン上に、回路部品を実装したセラミック基板を準備する工程と、ビアホールに導電性樹脂組成物を充填してなる、ビアホール導体を有した未硬化の絶縁性樹脂シートAおよびBを準備する工程と、キャリア層と、配線パターンの少なくとも2層からなる転写形成材を準備する工程と、第2の転写形成材または、配線パターンを有した樹脂多層基板または、金属箔を準備する工程と、前記転写形成材、前記未硬化の絶縁性樹脂シートA、前記セラミック基板、前記未硬化の絶縁性樹脂シートBおよび第2の転写形成材または、配線パターンを有した樹脂多層基板または、金属箔を順次積層し前記ビアホール導体によって、前記セラミック基板の一方の主面の配線パターンと前記転写形成材の配線パターンおよび、前記セラミック基板の他方の主面の配線パターンと第2の転写形成材または、配線パターンを有した樹脂多層基板または、金属箔が電気的に接続されるように位置合わせして積層する工程と、前記工程により積層された積層体の上下面にセラミックベースを配置し、加圧加熱して前記未硬化の絶縁性樹脂シートAおよびBを硬化させ、前記転写形成材、前記未硬化の絶縁性樹脂シートA、前記セラミック基板、前記未硬化の絶縁性樹脂シートBおよび第2の転写形成材または、配線パターンを有した樹脂多層基板または、金属箔とを一体化する工程と、前記転写形成材のキャリア層を除去し、前記絶縁樹脂シートに埋め込まれた配線パターンを形成し電子部品の前駆体を作製する工程と、前記電子部品の前駆体を分割し電子部品を作製する工程とを含むものである。   The method of manufacturing an electronic component according to the present invention includes a step of preparing a ceramic substrate on which circuit components are mounted on a wiring pattern on at least one main surface, and a via hole conductor formed by filling a via hole with a conductive resin composition. A step of preparing the uncured insulating resin sheets A and B having, a step of preparing a transfer forming material composed of at least two layers of a carrier layer and a wiring pattern, and a second transfer forming material or a wiring pattern. A step of preparing a resin multilayer substrate or a metal foil, and the transfer forming material, the uncured insulating resin sheet A, the ceramic substrate, the uncured insulating resin sheet B, and a second transfer forming material. Alternatively, a resin multilayer substrate having a wiring pattern or a metal foil is sequentially laminated, and the wiring pattern on one main surface of the ceramic substrate and the front are formed by the via-hole conductor. The wiring pattern of the transfer forming material and the wiring pattern of the other main surface of the ceramic substrate and the second transfer forming material, the resin multilayer substrate having the wiring pattern, or the metal foil are positioned so as to be electrically connected A step of laminating and laminating, a ceramic base is disposed on the upper and lower surfaces of the laminate laminated in the step, and the uncured insulating resin sheets A and B are cured by pressure and heating, and the transfer forming material The uncured insulating resin sheet A, the ceramic substrate, the uncured insulating resin sheet B and the second transfer forming material, a resin multilayer substrate having a wiring pattern, or a metal foil are integrated. Removing the carrier layer of the transfer forming material, forming a wiring pattern embedded in the insulating resin sheet to produce a precursor of the electronic component, and Dividing the precursor is intended to include a step of fabricating the electronic component.

この構成によると、前記積層体を加圧加熱して前記絶縁樹脂シートを硬化する際に、積層体の上下面にセラミックベースを配置しておくだけで、特別な工程を加えることなく、前記絶縁樹脂シート内に形成したビアホール導体に歪みを起こさず反りが発生しにくい高信頼性の電子部品を簡単に作成することができる。また、ビアホール導体に歪みを起こさず反りが発生しにくいことから、大判で一括形成できるので、作製時間の大幅な増加なく、電子部品を作製することができる。   According to this configuration, when the insulating resin sheet is cured by pressurizing and heating the laminated body, the insulating base is simply disposed on the upper and lower surfaces of the laminated body without adding a special process. A highly reliable electronic component in which a via hole conductor formed in a resin sheet is not distorted and hardly warps can be easily produced. In addition, since the via-hole conductor is not distorted and is not easily warped, it can be formed in a large size, so that an electronic component can be manufactured without a significant increase in manufacturing time.

また、本発明の電子部品の製造方法は、少なくとも一方の主面の配線パターン上に、回路部品を実装したセラミック基板を準備する工程と、ビアホールに導電性樹脂組成物を充填してなる、ビアホール導体を有した未硬化の絶縁性樹脂シートAおよびBを準備する工程と、配線パターンを有した樹脂多層基板またはかつ、金属箔を準備する工程と、前記樹脂多層基板、前記未硬化の絶縁性樹脂シートA、前記セラミック基板、前記未硬化の絶縁性樹脂シートBおよび第2の樹脂多層基板または、金属箔を順次積層し、前記ビアホール導体によって、前記セラミック基板の一方の主面の配線パターンと前記樹脂多層基板の配線パターンおよび、前記セラミック基板の他方の主面の配線パターンと第2の樹脂多層基板または、金属箔が電気的に接続されるように位置合わせして積層する工程と、前記工程により積層された積層体の上下面にセラミックベースを配置し、加圧加熱して前記未硬化の絶縁性樹脂シートAおよびBを硬化させ、樹脂多層基板、前記未硬化の絶縁性樹脂シートA、前記セラミック基板、前記未硬化の絶縁性樹脂シートBおよび第2の樹脂多層基板または、金属箔とを一体化し電子部品の前駆体を作製する工程と、前記電子部品の前駆体を分割し電子部品を作製する工程とを含むものである。   The method for manufacturing an electronic component according to the present invention includes a step of preparing a ceramic substrate on which circuit components are mounted on a wiring pattern on at least one main surface, and a via hole formed by filling a via hole with a conductive resin composition. A step of preparing uncured insulating resin sheets A and B having a conductor, a step of preparing a resin multilayer substrate or a metal foil having a wiring pattern, the resin multilayer substrate, and the uncured insulating property The resin sheet A, the ceramic substrate, the uncured insulating resin sheet B and the second resin multilayer substrate, or a metal foil are sequentially laminated, and a wiring pattern on one main surface of the ceramic substrate is formed by the via-hole conductor. The wiring pattern of the resin multilayer substrate and the wiring pattern of the other main surface of the ceramic substrate are electrically connected to the second resin multilayer substrate or the metal foil. The ceramic bases are disposed on the upper and lower surfaces of the laminated body laminated by the above steps, and the uncured insulating resin sheets A and B are cured by pressurizing and heating. A resin multilayer substrate, the uncured insulating resin sheet A, the ceramic substrate, the uncured insulating resin sheet B and the second resin multilayer substrate, or a metal foil are integrated to produce a precursor of an electronic component And a step of dividing the precursor of the electronic component to produce an electronic component.

この構成においても、上記本発明の電子部品の製造方法と同様の効果が得られる。また、配線転写パターンに替わり多層フレキ基板を用いていることにより、反りの発生無く配線収容性を高めることができるので設計の自由度を妨げることはない。   Even in this configuration, the same effects as those of the electronic component manufacturing method of the present invention can be obtained. In addition, by using a multilayer flexible substrate instead of the wiring transfer pattern, the wiring capacity can be improved without warping, so that the degree of design freedom is not hindered.

また、本発明の電子部品の製造方法は、前記電子部品の前駆体の前記金属箔を加工して配線パターンを形成する工程と、前記金属箔を加工した配線パターン上に回路部品を実装する工程と、前記電子部品の前駆体を分割し電子部品を作製する工程とを含むものである。   The method for manufacturing an electronic component according to the present invention includes a step of processing the metal foil as a precursor of the electronic component to form a wiring pattern, and a step of mounting a circuit component on the wiring pattern processed from the metal foil. And a step of producing an electronic component by dividing the precursor of the electronic component.

この構成によると前記セラミック基板の両面に接着された前記絶縁性樹脂シートに回路部品を内蔵したうえ、さらに前記絶縁性樹脂シートの上に形成された配線パターンに回路部品を実装することで、回路部品が高密度に三次元実装された電子部品となる。   According to this configuration, the circuit component is built in the insulating resin sheet bonded to both surfaces of the ceramic substrate, and the circuit component is further mounted on the wiring pattern formed on the insulating resin sheet. The electronic component is a three-dimensionally mounted component.

また、本発明の電子部品の製造方法は、前記電子部品の前駆体の前記第2の樹脂多層基板の配線パターン上に回路部品を実装する工程を含むものである。この構成によると上記発明の電子部品の製造方法と同じ効果を得ることができる。   The electronic component manufacturing method of the present invention includes a step of mounting a circuit component on the wiring pattern of the second resin multilayer substrate as a precursor of the electronic component. According to this configuration, the same effects as those of the electronic component manufacturing method of the invention can be obtained.

具体的には、前記樹脂多層基板がポリイミド、アラミド、PET、PPS、PEN、テフロン(登録商標)から選ばれる少なくとも一つのフィルムベース材を用いたフレキ基板であることが好ましい。   Specifically, the resin multilayer substrate is preferably a flexible substrate using at least one film base material selected from polyimide, aramid, PET, PPS, PEN, and Teflon (registered trademark).

この構成によれば前記セラミック基板の両面に積層される前記絶縁性樹脂シートによる反り緩和構造以外のアンバランス要因である樹脂多層基板が電子部品の反りに与える影響を最小限に抑えることが可能となる。   According to this configuration, it is possible to minimize the influence of the resin multilayer substrate, which is an unbalance factor other than the warp mitigation structure by the insulating resin sheet laminated on both surfaces of the ceramic substrate, on the warp of the electronic component. Become.

具体的には、前記絶縁性樹脂シートが、無機フィラー50%体積〜75%体積%と熱硬化性樹脂とを含む混合物からなるものである。この構成によると、無機フィラーを混合することで、異種積層構造における内部応力の原因の一つである絶縁性樹脂シートの熱膨張係数を小さくする効果がある。また配合比について、75体積%以上であると、粉体量に対し、液体量が少なすぎ、シート化が難しくなり、50体積%以下ではあると、無機フィラーを混合したことによる熱膨張の低減や放熱性の向上等の効果が少なくなる。加圧加熱して半導体チップ等の回路部品を絶縁性樹脂シートに内蔵する時に、回路部品に損傷を与えない粘度であれば、無機フィラーの配合率は大きい方が好ましい。   Specifically, the insulating resin sheet is made of a mixture containing 50% to 75% by volume inorganic filler and a thermosetting resin. According to this configuration, mixing the inorganic filler has an effect of reducing the thermal expansion coefficient of the insulating resin sheet, which is one of the causes of internal stress in the heterogeneous laminated structure. In addition, when the mixing ratio is 75% by volume or more, the amount of liquid is too small with respect to the amount of powder, making it difficult to form a sheet, and when it is 50% by volume or less, the thermal expansion is reduced by mixing the inorganic filler. And the effect of improving heat dissipation is reduced. When the circuit component such as a semiconductor chip is embedded in the insulating resin sheet by pressurization and heating, if the viscosity does not damage the circuit component, the compounding ratio of the inorganic filler is preferably large.

具体的には、前記無機フィラーが、Al23、SiO2、MgO、BNおよびAlNから選ばれる少なくとも一つの無機フィラーを含むものである。これらの無機フィラーを用いることで、絶縁性樹脂シートの放熱性が高くなり、熱膨張係数が小さい効果がある。 Specifically, the inorganic filler contains at least one inorganic filler selected from Al 2 O 3 , SiO 2 , MgO, BN, and AlN. By using these inorganic fillers, there is an effect that the heat dissipation of the insulating resin sheet is increased and the thermal expansion coefficient is small.

具体的には、前記熱硬化性樹脂が、エポキシ樹脂、フェノール樹脂およびシアネート樹脂から選ばれる少なくとも一つの熱硬化性樹脂を含むものである。これらの樹脂は多種多様な種類が市販されており、これらの樹脂を用いることで耐熱性や電気的絶縁性に優れたものとなる。   Specifically, the thermosetting resin contains at least one thermosetting resin selected from an epoxy resin, a phenol resin, and a cyanate resin. A wide variety of these resins are commercially available, and by using these resins, the resin becomes excellent in heat resistance and electrical insulation.

具体的には、前記導電性樹脂組成物が、金、銀、銅、およびニッケルから選ばれる少なくとも一つの金属を含む金属粒子を導電性成分として含み、かつ、エポキシ樹脂を樹脂成分として含むものである。上記金属は電気抵抗が低く、また、エポキシ樹脂は耐熱性や電気絶縁性に優れている。特に、銅粉をコア材として、表面に銀でコートした金属粒子は、機械的強度が強く安価である銅粉と、酸化しにくく低抵抗である銀粉の両方の特性を併せ持ち、好適である。   Specifically, the conductive resin composition includes metal particles including at least one metal selected from gold, silver, copper, and nickel as a conductive component, and includes an epoxy resin as a resin component. The metal has a low electrical resistance, and the epoxy resin is excellent in heat resistance and electrical insulation. In particular, metal particles coated with silver on the surface using copper powder as a core material are suitable because they have both the characteristics of copper powder that has high mechanical strength and is inexpensive and silver powder that is resistant to oxidation and low resistance.

本発明の電子部品は、第1の配線パターンを有したセラミック基板層と、前記セラミック基板層の第1の主面に接着され、導電性樹脂組成物からなるビアホール導体を有した絶縁性樹脂シート層と、前記絶縁性樹脂シート層に接着され、前記ビアホール導体により前記第1の配線パターンと電気的に接続される第2の配線パターンまたは、第2の配線パターンを有した樹脂多層基板層と、前記セラミック基板の第2の主面に接着される絶縁性樹脂シート層とを備えたものである。この構成によると、異種材料の積層に起因する反りを、セラミック基板層の両面に絶縁性樹脂シート層を形成しているため応力バランスがとれ反りのない二次実装信頼性の高い電子部品にすることができる。また、セラミック基板層の第1の主面に絶縁性樹脂シート層を介して接着される第2の配線パターンまたは第2の配線パターンを有した樹脂多層基板層を積層することによって生じる応力バランスの不整合を、セラミック基板層の両面に接着される絶縁性樹脂シート層の厚みを変えることで容易に応力バランスの整合をとることが可能であり、必ずしも完全な対称構造としなくても反りのない電子部品となる。   An electronic component according to the present invention includes a ceramic substrate layer having a first wiring pattern, and an insulating resin sheet having a via-hole conductor made of a conductive resin composition bonded to the first main surface of the ceramic substrate layer. A second wiring pattern bonded to the insulating resin sheet layer and electrically connected to the first wiring pattern by the via-hole conductor, or a resin multilayer substrate layer having a second wiring pattern And an insulating resin sheet layer bonded to the second main surface of the ceramic substrate. According to this configuration, since the insulating resin sheet layer is formed on both sides of the ceramic substrate layer, the warpage due to the lamination of different materials is made into an electronic component with high stress that balances stress and has no warpage. be able to. Further, the stress balance caused by laminating the second wiring pattern or the resin multilayer substrate layer having the second wiring pattern that is bonded to the first main surface of the ceramic substrate layer via the insulating resin sheet layer. It is possible to easily match the stress balance by changing the thickness of the insulating resin sheet layer bonded to both surfaces of the ceramic substrate layer, and there is no warping even if it is not necessarily a completely symmetrical structure. It becomes an electronic component.

また本発明の電子部品は、前記セラミック基板層の第1の主面および第2の主面の少なくとも一方に、前記絶縁性樹脂シート層に内蔵した状態で、前記第1の配線パターンに実装した回路部品をさらに備えたものでもよい。この構成においてセラミック基板層の両面に回路部品を実装した形態では対称構造に近くなり応力緩和ができるため好ましい。この構造においても内蔵回路部品構成を含んだ応力バランスの不整合を、セラミック基板層の両面に接着される絶縁性樹脂シート層の厚みを変えることで容易に応力バランスの整合をとることが可能であり、必ずしも完全な対称構造としなくても反りのない電子部品となる。   The electronic component of the present invention is mounted on the first wiring pattern in a state of being incorporated in the insulating resin sheet layer on at least one of the first main surface and the second main surface of the ceramic substrate layer. It may further include a circuit component. In this configuration, a circuit component mounted on both sides of the ceramic substrate layer is preferable because it is close to a symmetric structure and can relieve stress. Even in this structure, the stress balance mismatch including the built-in circuit component configuration can be easily achieved by changing the thickness of the insulating resin sheet layer bonded to both sides of the ceramic substrate layer. In other words, the electronic component is not necessarily warped without necessarily having a completely symmetrical structure.

具体的には、前記回路部品が半導体チップを含むものである。この構成によると、反りが発生しにくいことに基づき。特に、微細なピッチの外部電極が形成されたベアチップ半導体もしくは半導体パッケージが実装されている場合において、反りに起因するベアチップ半導体もしくは半導体パッケージ実装の電気接続の悪化が起こりにくい。   Specifically, the circuit component includes a semiconductor chip. Based on this configuration, warping is less likely to occur. In particular, when a bare chip semiconductor or a semiconductor package in which external electrodes with fine pitches are formed is mounted, the electrical connection of the bare chip semiconductor or semiconductor package mounting due to warpage hardly occurs.

また本発明の電子部品は、前記セラミック基板層の第2の主面に接着され、導電性樹脂組成物からなるビアホール導体を有した絶縁性樹脂シート層と、前記絶縁性樹脂シート層に接着される第3の配線パターンまたは、第3の配線パターンを有した樹脂多層基板層または、導電性膜層を備え、前記ビアホール導体によって前記セラミック基板層の第1の配線パターンと、前記第3の配線パターンまたは導電性膜層とが電気的に接続されたものでもよい。この構成において前記ビアホール導体を内蔵された回路部品の周辺に配置してグランドに接続することによって磁気シールド効果を得ることができる。また、第3の配線パターンまたは、第3の配線パターンを有した樹脂多層基板上にさらに回路部品を実装することにより高密度に部品実装された電子部品となる。   The electronic component of the present invention is bonded to the second main surface of the ceramic substrate layer and bonded to the insulating resin sheet layer having a via-hole conductor made of a conductive resin composition and the insulating resin sheet layer. A third wiring pattern or a resin multilayer substrate layer having a third wiring pattern or a conductive film layer, and the first wiring pattern of the ceramic substrate layer and the third wiring by the via-hole conductor. The pattern or the conductive film layer may be electrically connected. In this configuration, the magnetic shield effect can be obtained by arranging the via-hole conductor around the built-in circuit component and connecting it to the ground. Further, by mounting circuit components on the third wiring pattern or the resin multilayer substrate having the third wiring pattern, electronic components are mounted with high density.

本発明によれば、回路部品が実装されたセラミック基板の両面に、導電性樹脂ペーストが充填されたビアホール導体を有した未硬化の熱硬化性樹脂シートと、配線パターンが形成された転写シートまたは樹脂多層基板または金属箔のいずれかを積層した積層体を加圧加熱して一体化する際に、積層体の上下面にセラミックベースを配置して加圧加熱することで、電子部品の異種積層に起因するビアホール導体の歪み、および、反りの発生を抑制することができる。これは、加熱時に発生するセラミック基板と樹脂・金属材料の熱膨張係数の差によって生ずる歪みを、セラミック基板をコアとして両面にセラミックベースを配して圧力をかけることで間にある樹脂・金属材料の熱膨張を抑制することができ、絶縁性樹脂シートに形成されたビアホール導体の歪み生じさせず配線パターンとの位置ずれを発生させない。セラミック基板の両面に接着される絶縁性樹脂シートの厚みを電子部品構成に応じて変えることで、応力対称構造を容易に構成できるため反りの発生を制御できる。この製造方法によればセラミック基板の両面に回路部品を実装した状態で加熱加圧できるため工程を単純化できる。また、電子部品内のビアホール導体の歪みおよびの反りを低減することで、マザー基板の二次実装性、そして二次実装後の電気接続信頼性および耐落下衝撃信頼性を高めることができるようになる。   According to the present invention, an uncured thermosetting resin sheet having a via-hole conductor filled with a conductive resin paste on both sides of a ceramic substrate on which circuit components are mounted, and a transfer sheet on which a wiring pattern is formed or When laminating a laminate with either a resin multilayer substrate or metal foil by pressurization and heating, disposing different types of electronic components by placing a ceramic base on the top and bottom surfaces of the laminate and heating with pressure It is possible to suppress the distortion of the via-hole conductor and the occurrence of warpage due to the above. This is because the distortion caused by the difference in coefficient of thermal expansion between the ceramic substrate and the resin / metal material that occurs during heating is placed between the ceramic substrate as a core and the ceramic base is placed on both sides to apply pressure. Therefore, the via hole conductor formed in the insulating resin sheet is not distorted and the positional deviation from the wiring pattern is not generated. By changing the thickness of the insulating resin sheet bonded to both surfaces of the ceramic substrate according to the configuration of the electronic component, it is possible to easily configure a stress symmetric structure, thereby controlling the occurrence of warpage. According to this manufacturing method, it is possible to simplify the process because heating and pressurization can be performed with circuit components mounted on both sides of the ceramic substrate. In addition, by reducing the distortion and warpage of via-hole conductors in electronic components, it is possible to improve the secondary mounting property of the motherboard, the electrical connection reliability after secondary mounting, and the drop impact resistance reliability. Become.

以下、本発明の実施の形態について、図1ないし図12を用いて説明する。   Embodiments of the present invention will be described below with reference to FIGS.

(第1の実施の形態)
本発明の第1の実施の形態の電子部品の製造方法を図1(a)〜図1(m)の模式的な工程断面図を参照して説明する。
(First embodiment)
A method for manufacturing an electronic component according to a first embodiment of the present invention will be described with reference to schematic process cross-sectional views of FIGS. 1 (a) to 1 (m).

図1において、101は厚み0.5mmの6層セラミック基板で無収縮のLTCC(low temperature co−fired ceramics)、102a・102bはセラミック基板101の配線パターンでAg材料を主成分としたペーストにて印刷・焼成形成され厚みは20μmである。111a・111b・111cは、回路部品で抵抗、コンデンサ、インダクタなどのチップ部品であり、112は半導体素子であり、半導体チップ、半導体パッケージ等、124は転写形成材に形成された厚み0.012mmのCu箔からなる配線パターン、123は転写形成材のキャリア層で厚み0.07mmのCu箔または樹脂フィルム、131は厚み0.5mmの絶縁性樹脂シートで内蔵される部品厚みに応じて厚みは調整される。132は厚み0.02mmの保護フィルムでPPS(ポリフェニレンサルファイド)であるが、PET(ポリエチレンテレフタレート)、PEN(ポリエチレンナフタレート)などを用いても良い。133は直径0.16mmのビアホール、134は導電性樹脂組成物からなるビアホール導体、141は金属箔、151は厚み2mmのセラミックベース、152は厚み2mmのクッション材、154はヒーター、153は熱プレス装置の加熱プレート、143は電子部品の前駆体、155は分割加工ライン、147は本発明の電子部品である。   In FIG. 1, 101 is a 6-layer ceramic substrate having a thickness of 0.5 mm, non-shrinkable LTCC (low temperature co-fired ceramics), 102a and 102b are wiring patterns of the ceramic substrate 101, and a paste mainly composed of an Ag material. The thickness is 20 μm formed by printing / firing. Reference numerals 111a, 111b, and 111c denote circuit parts, which are chip parts such as resistors, capacitors, and inductors, 112 denotes a semiconductor element, and a semiconductor chip, a semiconductor package, and the like 124 has a thickness of 0.012 mm formed on the transfer forming material. A wiring pattern made of Cu foil, 123 is a transfer formation material carrier layer of 0.07 mm thick Cu foil or resin film, 131 is a 0.5 mm thick insulating resin sheet, and the thickness is adjusted according to the thickness of the component Is done. Reference numeral 132 denotes a protective film having a thickness of 0.02 mm, which is PPS (polyphenylene sulfide), but PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or the like may be used. 133 is a via hole having a diameter of 0.16 mm, 134 is a via hole conductor made of a conductive resin composition, 141 is a metal foil, 151 is a ceramic base having a thickness of 2 mm, 152 is a cushioning material having a thickness of 2 mm, 154 is a heater, 153 is a hot press A heating plate of the apparatus, 143 is an electronic component precursor, 155 is a division processing line, and 147 is an electronic component of the present invention.

絶縁性樹脂シート131は、無機フィラー50体積%〜75体積%と熱硬化性樹脂とを含む混合物からなる。ここで無機フィラーは、Al23、SiO2、MgO、BNおよびAlNから選ばれる少なくとも一つの無機フィラーを含み、熱硬化性樹脂は、エポキシ樹脂、フェノール樹脂およびシアネート樹脂から選ばれる少なくとも一つの熱硬化性樹脂を含むものからなる。さらに、ビアホール導体134を構成する導電性樹脂組成物は、金、銀、銅、およびニッケルから選ばれる少なくとも一つの金属を含む金属粒子を導電性成分として含み、かつ、エポキシ樹脂を樹脂成分として含むものからなる。このような構成は、第2ないし第6の実施の形態においても同様である。 The insulating resin sheet 131 is made of a mixture containing 50% to 75% by volume of an inorganic filler and a thermosetting resin. Here, the inorganic filler includes at least one inorganic filler selected from Al 2 O 3 , SiO 2 , MgO, BN and AlN, and the thermosetting resin is at least one selected from an epoxy resin, a phenol resin and a cyanate resin. It consists of what contains a thermosetting resin. Furthermore, the conductive resin composition constituting the via-hole conductor 134 includes metal particles including at least one metal selected from gold, silver, copper, and nickel as a conductive component, and includes an epoxy resin as a resin component. Consists of things. Such a configuration is the same in the second to sixth embodiments.

図1(a)と図1(b)でセラミック基板101の配線パターン102a・102b上に回路部品111a・111b・11cおよび半導体素子112を実装する。図1(c)と図1(d)で転写形成材121の金属箔122を加工して転写形成材の配線パターン124が形成された転写形成材125を用意する。図1(e)〜図1(h)で絶縁性樹脂シート131の両面に保護フィルム132を貼り合わせ、ビアホール133を開口、導電性樹脂組成物を充填してビアホール導体134を形成、保護フィルム132を除去してビアホール導体134が形成された絶縁性樹脂シート135を用意する。図1(i)で回路部品が実装されたセラミック基板104、ビアホール導体を備えた絶縁性樹脂シート135a、配線パターン形成された転写形成材125および金属箔141を、ビアホール導体134によって、セラミック基板101の一方の主面に形成されたセラミック基板の配線パターン102bと転写形成材の配線パターン124および、セラミック基板101の他方の主面に形成されたセラミック基板の配線パターン102aと金属箔141が電気的に接続されるように位置合わせして積層する。図1(j)で回路部品が実装されたセラミック基板104、ビアホール導体を備えた絶縁性樹脂シート135a・135b、配線パターン形成された転写形成材125および金属箔141が積層された積層体の上下面に、セラミックベース151とクッション材152とを配置し、加熱プレート153にて加圧加熱することで絶縁性樹脂シート131を熱硬化して積層体を一体化する。図1(k)は加圧加熱して一体化された積層体である。図1(l)で転写形成材のキャリア層123を除去する。図1(a)〜図1(l)の工程によって製作される電子部品は、現実的な製造方法としては大判で多数個取りされるのが一般的であり、転写形成材のキャリア層123を除去した段階で図1(m)に示す電子部品の前駆体143が得られる。切断ライン155で分割、個片化し、一つ一つの電子部品147として、本発明の電子部品を作製する。   1A and 1B, circuit components 111a, 111b, and 11c and a semiconductor element 112 are mounted on the wiring patterns 102a and 102b of the ceramic substrate 101. In FIG. 1C and FIG. 1D, a metal foil 122 of the transfer forming material 121 is processed to prepare a transfer forming material 125 in which a wiring pattern 124 of the transfer forming material is formed. 1E to 1H, the protective film 132 is bonded to both surfaces of the insulating resin sheet 131, the via hole 133 is opened, the conductive resin composition is filled to form the via hole conductor 134, and the protective film 132 is formed. Is removed to prepare an insulating resin sheet 135 on which a via-hole conductor 134 is formed. In FIG. 1 (i), the ceramic substrate 104 on which circuit components are mounted, the insulating resin sheet 135a provided with via-hole conductors, the transfer forming material 125 on which the wiring pattern is formed, and the metal foil 141 are connected to the ceramic substrate 101 by the via-hole conductors 134. The ceramic substrate wiring pattern 102b and the transfer forming material wiring pattern 124 formed on one main surface of the ceramic substrate 101, and the ceramic substrate wiring pattern 102a and metal foil 141 formed on the other main surface of the ceramic substrate 101 are electrically connected. Are aligned so that they are connected to each other. In FIG. 1 (j), the ceramic substrate 104 on which the circuit components are mounted, the insulating resin sheets 135a and 135b having via-hole conductors, the transfer forming material 125 on which the wiring pattern is formed, and the metal foil 141 are stacked. The ceramic base 151 and the cushioning material 152 are arranged on the lower surface, and the insulating resin sheet 131 is thermoset by pressurizing and heating with the heating plate 153 to integrate the laminate. FIG. 1 (k) shows a laminate integrated by pressurization and heating. In FIG. 1L, the carrier layer 123 of the transfer forming material is removed. As a practical manufacturing method, a large number of electronic parts manufactured by the processes of FIGS. 1A to 1L are generally taken in large numbers, and a carrier layer 123 of a transfer forming material is formed. At the stage of removal, the electronic component precursor 143 shown in FIG. 1 (m) is obtained. The electronic component of the present invention is manufactured as each electronic component 147 by dividing and dividing into pieces at the cutting line 155.

尚、第1の実施の形態では、セラミック基板の両面に回路部品を実装して絶縁性樹脂シートに内蔵しているがそれに限定されず、片面の実装でも良く、さらには厚膜または薄膜で形成されるセラミック基板上への作り込み部品でも良い。また、セラミック基板の他方の主面に接着される絶縁性樹脂シートには、必ずしもビアホール導体を形成することなく部品を内蔵するだけでも良い。   In the first embodiment, the circuit components are mounted on both surfaces of the ceramic substrate and incorporated in the insulating resin sheet. However, the present invention is not limited to this, and mounting on one surface may be possible. A built-in component on a ceramic substrate may be used. In addition, the insulating resin sheet bonded to the other main surface of the ceramic substrate may contain only components without necessarily forming via-hole conductors.

加熱時に発生するセラミック基板と樹脂材料の熱膨張係数の差によって生ずる歪みを、セラミック基板101をコアとして両面にセラミックベース151を配して圧力をかけることで、間にある樹脂・金属材料の熱膨張を抑制することができ、絶縁性樹脂シート131に形成されたビアホール導体134に歪みを生じさせないため、ビアホール導体と配線パターンとの位置ずれを発生させない。セラミック基板101の両面に接着される絶縁性樹脂シート131の厚みを電子部品構成に応じて変えることで、応力対称構造が容易に構成できるため反りの発生を制御できる。また、セラミック基板の両面に回路部品を実装した状態で加熱加圧できることで、加圧加熱後に部品を実装する工程を省略でき工程を単純化できる。また、電子部品内のビアホール導体の歪みおよびの反りを低減することで、マザー基板の二次実装性、そして二次実装後の電気接続信頼性および耐落下衝撃信頼性を高めることができるようになる。   Distortion caused by the difference in thermal expansion coefficient between the ceramic substrate and the resin material generated during heating is applied by applying pressure by placing the ceramic base 151 on both sides with the ceramic substrate 101 as a core, so that the heat of the resin / metal material in between is applied. The expansion can be suppressed, and the via hole conductor 134 formed on the insulating resin sheet 131 is not distorted, so that the positional deviation between the via hole conductor and the wiring pattern does not occur. By changing the thickness of the insulating resin sheet 131 bonded to both surfaces of the ceramic substrate 101 according to the configuration of the electronic component, a stress symmetric structure can be easily configured, so that the occurrence of warpage can be controlled. In addition, since it is possible to heat and press the circuit component mounted on both sides of the ceramic substrate, the step of mounting the component after pressurizing and heating can be omitted, and the process can be simplified. In addition, by reducing the distortion and warpage of via-hole conductors in electronic components, it is possible to improve the secondary mounting property of the motherboard, the electrical connection reliability after secondary mounting, and the drop impact resistance reliability. Become.

(第2の実施の形態)
本発明の第2の実施の形態の電子部品の製造方法を図3(a)〜図3(c)の模式的な工程断面図を参照して説明する。
(Second Embodiment)
A method for manufacturing an electronic component according to a second embodiment of the present invention will be described with reference to schematic process cross-sectional views in FIGS. 3 (a) to 3 (c).

図3において、133は回路部品が実装されたセラミック基板、135a・135bはビアホール導体が形成された絶縁性樹脂シートでそれぞれの構成要素および製造工程は第1の実施の形態と同様である。126は樹脂多層基板、141は金属箔である。   In FIG. 3, reference numeral 133 denotes a ceramic substrate on which circuit components are mounted, 135a and 135b are insulating resin sheets on which via-hole conductors are formed, and the respective components and manufacturing steps are the same as those in the first embodiment. 126 is a resin multilayer substrate, and 141 is a metal foil.

図3(a)で回路部品が実装されたセラミック基板133、ビアホール導体を備えた絶縁性樹脂シート135a・135b、樹脂多層基板126、金属箔141とを、ビアホール導体134によってセラミック基板101の一方の主面に形成されたセラミック基板の配線パターン102aと、樹脂多層基板126の配線パターン128bおよび、セラミック基板101の他方の主面に形成されたセラミック基板の配線パターン102bと金属箔141が電気的に接続されるように位置合わせして積層する。図3(b)で回路部品が実装されたセラミック基板133、ビアホール導体を備えた絶縁性樹脂シート135a・135b、樹脂多層基板126および金属箔141が積層された積層体の上下面に、セラミックベース151とクッション材152とを配置し、熱プレス装置の加熱プレート153にて加圧加熱することで絶縁性樹脂シート131を熱硬化して積層体を一体化する。ここで、154は、加熱するためのヒーターである。図3(c)は加圧加熱して一体化された積層体である。図示では個片で示しているが実施の形態1と同様に多数個取りの大判である電子部品の前駆体を分割、個片化して本発明の電子部品を作製する。   In FIG. 3A, the ceramic substrate 133 on which circuit components are mounted, the insulating resin sheets 135a and 135b provided with via-hole conductors, the resin multilayer substrate 126, and the metal foil 141 are connected to one of the ceramic substrates 101 by the via-hole conductors 134. The wiring pattern 102a of the ceramic substrate formed on the main surface, the wiring pattern 128b of the resin multilayer substrate 126, and the wiring pattern 102b of the ceramic substrate formed on the other main surface of the ceramic substrate 101 and the metal foil 141 are electrically connected. Laminate them so that they are connected. In FIG. 3 (b), ceramic bases 133 on which circuit components are mounted, insulating resin sheets 135a and 135b having via-hole conductors, a resin multilayer substrate 126, and a metal base 141 are laminated on the upper and lower surfaces of the laminate. 151 and the cushioning material 152 are arranged, and the insulating resin sheet 131 is thermally cured by pressurizing and heating with the heating plate 153 of the hot press device, and the laminate is integrated. Here, 154 is a heater for heating. FIG. 3C shows a laminated body integrated by pressurization and heating. Although shown in the drawing as an individual piece, the electronic component precursor of the present invention is manufactured by dividing and dividing the precursor of a large-sized electronic component having a large number of pieces as in the first embodiment.

尚、第2の実施の形態では、セラミック基板の両面に回路部品を実装して絶縁性樹脂シートに内蔵しているがそれに限定されず、片面の実装でも良く、さらには厚膜または薄膜で形成されるセラミック基板上への作り込み部品でも良い。また、セラミック基板の他方の主面に接着される絶縁性樹脂シートには、必ずしもビアホール導体を形成することなく部品を内蔵するだけでも良い。   In the second embodiment, the circuit components are mounted on both surfaces of the ceramic substrate and incorporated in the insulating resin sheet. However, the present invention is not limited to this, and single-sided mounting may be used, and a thick film or a thin film may be formed. A built-in component on a ceramic substrate may be used. In addition, the insulating resin sheet bonded to the other main surface of the ceramic substrate may contain only components without necessarily forming via-hole conductors.

第2の実施の形態では、第1の実施の形態における効果に加え、単層配線層である転写パターンに代わり樹脂多層基板を用いているので、配線収容性が高く設計の自由度を妨げることのない電子部品となる。また、樹脂多層基板としてポリイミド、アラミド、PET、PPS、PENまたはテフロン(登録商標)などの厚み0.005mmから0.05mmのフィルムベース材を用いたフレキ基板(厚み0.015mmから0.1mm)を用いることでより反りを小さく出来る。   In the second embodiment, in addition to the effects of the first embodiment, since a resin multilayer substrate is used instead of the transfer pattern which is a single-layer wiring layer, the wiring capacity is high and the design freedom is hindered. It becomes an electronic component without. Also, a flexible substrate (thickness 0.015 mm to 0.1 mm) using a film base material having a thickness of 0.005 mm to 0.05 mm such as polyimide, aramid, PET, PPS, PEN or Teflon (registered trademark) as a resin multilayer substrate By using, warpage can be made smaller.

(第3の実施の形態)
本発明の第3の実施の形態の電子部品の製造方法を図4(a)と図4(b)の模式的な工程断面図を参照して説明する。
(Third embodiment)
A method for manufacturing an electronic component according to a third embodiment of the present invention will be described with reference to schematic process cross-sectional views in FIGS. 4 (a) and 4 (b).

図4において、142は金属箔を加工した配線パターン、114a・114bは回路部品、112と113は、半導体素子で、半導体チップまたは半導体パッケージである。   In FIG. 4, 142 is a wiring pattern obtained by processing a metal foil, 114a and 114b are circuit components, and 112 and 113 are semiconductor elements, which are semiconductor chips or semiconductor packages.

図4(a)と図4(b)にて、第2の実施の形態で作製された電子部品の前駆体の金属箔141をパターンニングして配線パターン142を形成する。次に、配線パターン142上に半導体チップまたは半導体パッケージなどの半導体素子113および回路部品114a・114bを実装する。さらに多数個取りの大判である電子部品の前駆体を分割、個片化して本発明の電子部品を作製する。尚、電子部品の前駆体として第1の実施の形態で説明した電子部品の前駆体を用いても良い。また、金属箔をパターン加工して配線パターンを形成したが、加圧加熱する際に、転写形成材による配線パターン転写または樹脂多層基板を接着してその配線パターン上に回路部品を実装しても良い。   In FIG. 4A and FIG. 4B, the wiring pattern 142 is formed by patterning the metal foil 141 of the precursor of the electronic component manufactured in the second embodiment. Next, a semiconductor element 113 such as a semiconductor chip or a semiconductor package and circuit components 114 a and 114 b are mounted on the wiring pattern 142. Furthermore, the electronic component precursor of the present invention is manufactured by dividing a large-sized large-sized electronic component precursor into individual pieces. The electronic component precursor described in the first embodiment may be used as the electronic component precursor. In addition, the wiring pattern was formed by patterning the metal foil, but when applying pressure and heating, the wiring pattern transfer using a transfer forming material or a resin multilayer substrate can be adhered and circuit components can be mounted on the wiring pattern. good.

第3の実施の形態では、第2の実施の形態における効果に加え、さらに回路部品が多段に積層されて実装されているため実装密度の高い電子部品となり小型化に優位である。   In the third embodiment, in addition to the effects of the second embodiment, circuit components are stacked and mounted in multiple stages, so that the electronic component has a high mounting density and is advantageous for miniaturization.

(第4の実施の形態)
本発明の第4の実施の形態の電子部品を、図5ないし図12の模式的な断面図を参照して説明する。
(Fourth embodiment)
An electronic component according to a fourth embodiment of the present invention will be described with reference to schematic cross-sectional views of FIGS.

図5ないし図12において、101は、セラミック基板、102aと102bはセラミック基板101の配線パターン、111a・111b・111cは回路部品で抵抗、コンデンサ、インダクタなどのチップ部品、112は、半導体素子で、半導体チップまたは半導体パッケージ等、124は転写形成材の配線パターン、127は樹脂多層基板、128a・128bは樹脂多層基板の配線パターン、131a・131bは絶縁性樹脂シート、134は導電性樹脂組成物からなるビアホール導体、141は金属箔である。このような構成は、第5の実施の形態においても同様である。尚、金属箔141に代わり、スパッター、蒸着等で形成される金属薄膜や、メッキで形成される金属厚膜または導電性粒子を含んだ印刷ペーストでも形成しても良い。   5 to 12, 101 is a ceramic substrate, 102a and 102b are wiring patterns of the ceramic substrate 101, 111a, 111b, and 111c are circuit components and chips such as resistors, capacitors, and inductors, and 112 is a semiconductor element. A semiconductor chip or a semiconductor package, etc. 124 is a wiring pattern of a transfer forming material, 127 is a resin multilayer board, 128a and 128b are wiring patterns of a resin multilayer board, 131a and 131b are insulating resin sheets, and 134 is a conductive resin composition. The via-hole conductor 141 is a metal foil. Such a configuration is the same in the fifth embodiment. Instead of the metal foil 141, a metal thin film formed by sputtering, vapor deposition, or the like, a metal thick film formed by plating, or a printing paste containing conductive particles may be used.

図5における本発明の電子部品は、セラミック基板101の第1の主面に接着され、導電性樹脂組成物からなるビアホール導体134を有した絶縁性樹脂シート131aと、絶縁性樹脂シート131aに接着され、ビアホール導体134により第1の配線パターンと電気的に接続される第2の転写形成材の配線パターン124と、セラミック基板101の第2の主面に回路部品111aおよび半導体チップまたは半導体パッケージなどの半導体素子112が実装されると共に、絶縁性樹脂シート131bが接着され、回路部品111aおよび半導体チップまたは半導体パッケージなどの半導体素子112が絶縁性樹脂シートに内蔵されている。   The electronic component of the present invention in FIG. 5 is bonded to the first main surface of the ceramic substrate 101 and bonded to the insulating resin sheet 131a having a via-hole conductor 134 made of a conductive resin composition, and the insulating resin sheet 131a. The wiring pattern 124 of the second transfer forming material electrically connected to the first wiring pattern by the via hole conductor 134, the circuit component 111a and the semiconductor chip or the semiconductor package on the second main surface of the ceramic substrate 101, etc. The semiconductor element 112 is mounted, the insulating resin sheet 131b is bonded, and the circuit component 111a and the semiconductor element 112 such as a semiconductor chip or a semiconductor package are built in the insulating resin sheet.

この構成によると、異種材料の積層に起因する反りを、セラミック基板の両面に絶縁性樹脂シートを形成しているため応力バランスがとれ反りのない二次実装信頼性の高い電子部品にすることができる。また、回路部品を実装することでより複雑な応力が発生しやすい構造を、セラミック基板の両面に接着される絶縁性樹脂シートの厚みを変えることで容易に応力バランスの整合をとることが可能であり、必ずしも完全な対称構造としなくても反りのない電子部品となる。   According to this configuration, since the insulating resin sheets are formed on both surfaces of the ceramic substrate, the warpage due to the lamination of different materials can be made into an electronic component with high stress balance and no secondary warpage. it can. In addition, it is possible to easily adjust the stress balance by changing the thickness of the insulating resin sheet that is bonded to both sides of the ceramic substrate, so that more complex stresses can easily be generated by mounting circuit components. In other words, the electronic component is not necessarily warped without necessarily having a completely symmetrical structure.

図6における本発明の電子部品は、セラミック基板の第1の主面にも回路部品を実装して、絶縁樹脂シートに内蔵したものである。このことで、セラミック基板の第1の主面に接着される絶縁樹脂シートが、単なるマザー基板への二次実装時の応力緩和機能だけでなく部品内蔵層としての役割も果たし、高密度実装の電子部品となる。   The electronic component of the present invention in FIG. 6 is a component in which a circuit component is mounted on the first main surface of a ceramic substrate and is built in an insulating resin sheet. As a result, the insulating resin sheet bonded to the first main surface of the ceramic substrate not only serves as a stress relaxation function during secondary mounting on the mother substrate but also serves as a component built-in layer. It becomes an electronic component.

図7および図8における本発明の電子部品は、上記で説明した構成に加えて、セラミック基板の第2の主面に接着され回路部品が内蔵される絶縁樹脂シート131bに、さらに金属箔141を接着するとともにビアホール導体134を回路部品111aおよび半導体チップまたは半導体パッケージなどの半導体素子112を囲むように形成してグランドに接続することで磁気シールド機能を持たせたものである。   7 and 8, in addition to the configuration described above, the electronic component of the present invention is further provided with a metal foil 141 on an insulating resin sheet 131b that is bonded to the second main surface of the ceramic substrate and has a built-in circuit component. A magnetic shield function is provided by bonding and forming a via-hole conductor 134 so as to surround the circuit component 111a and the semiconductor element 112 such as a semiconductor chip or a semiconductor package, and connecting it to the ground.

図9ないし図12における本発明の電子部品は、図5ないし図8で説明した電子部品の構成における転写形成材の配線パターン124に代わり樹脂多層基板126を用いたものである。127は樹脂多層基板のコア材で、好ましくはポリイミド、アラミド、PET、PPS、PENおよびテフロン(登録商標)から選ばれる少なくとも一つのフィルムベース材を用いたフレキ基板である。   The electronic component of the present invention in FIGS. 9 to 12 uses a resin multilayer substrate 126 in place of the wiring pattern 124 of the transfer forming material in the configuration of the electronic component described in FIGS. Reference numeral 127 denotes a core material of a resin multilayer substrate, preferably a flexible substrate using at least one film base material selected from polyimide, aramid, PET, PPS, PEN, and Teflon (registered trademark).

単層配線層である転写パターンに代わり樹脂多層基板を用いているので、配線収容性が高く設計の自由度を妨げることのない電子部品となる。また、樹脂多層基板としてポリイミド、アラミド、PET、PPS、PENおよびテフロン(登録商標)などのフィルムベース材を用いたフレキ基板を用いることでより反りを小さく出来る。また、樹脂多層基板は2層基板として図示されているが特にこれに限定されるものではない。   Since a resin multilayer substrate is used in place of the transfer pattern which is a single-layer wiring layer, the electronic component has high wiring capacity and does not hinder the freedom of design. Further, by using a flexible substrate using a film base material such as polyimide, aramid, PET, PPS, PEN, and Teflon (registered trademark) as the resin multilayer substrate, warpage can be further reduced. Moreover, although the resin multilayer substrate is illustrated as a two-layer substrate, it is not limited to this.

(第5の実施の形態)
本発明の第5の実施の形態の電子部品を、図4(b)の模式的な断面図を参照して説明する。
(Fifth embodiment)
An electronic component according to a fifth embodiment of the present invention will be described with reference to a schematic cross-sectional view of FIG.

図4(b)において、148は第4実施の形態で作製された図3(c)に示す本発明の電子部品の一例である。本実施の形態では、金属箔141を配線パターン142に置き換えたものである。配線パターン142上に半導体チップまたは半導体パッケージなどの半導体素子113や回路部品114a・114bを実装されている。尚、ビアホール導体134は磁気シールド目的に限定されず信号線としても使用する。配線パターンは金属箔をパターン加工しているが、これに限定されるものではなく配線パターン転写や樹脂多層基板を貼り付けたものでも良い。また、マザー基板への二次実装面側には樹脂多層基板を用いているが配線パターン転写による形成でも良い。さらには、セラミック基板への回路部品実装は片面への実装形態でも良い。   In FIG. 4B, 148 is an example of the electronic component of the present invention shown in FIG. 3C manufactured in the fourth embodiment. In the present embodiment, the metal foil 141 is replaced with the wiring pattern 142. A semiconductor element 113 such as a semiconductor chip or a semiconductor package and circuit components 114 a and 114 b are mounted on the wiring pattern 142. The via-hole conductor 134 is not limited to the purpose of magnetic shielding but is also used as a signal line. The wiring pattern is obtained by patterning a metal foil. However, the wiring pattern is not limited to this, and a wiring pattern transfer or a resin multilayer substrate may be attached. Further, although a resin multilayer substrate is used on the secondary mounting surface side to the mother substrate, it may be formed by wiring pattern transfer. Furthermore, the circuit component mounting on the ceramic substrate may be a mounting form on one side.

本発明の電子部品では、回路部品が多段に積層されて実装されているため実装密度の高い電子部品となり小型化に優位である。   In the electronic component of the present invention, circuit components are stacked and mounted in multiple stages, so that the electronic component has a high mounting density and is advantageous for miniaturization.

以下、実施例により本発明をさらに詳細に説明する。   Hereinafter, the present invention will be described in more detail with reference to examples.

(第6の実施の形態)
上述の第1の実施の形態の電子部品の製造方法を、次の(1)〜(7)の手順および図1(a)〜図1(m)および図2の模式的な工程断面図を用いて説明する。
(Sixth embodiment)
The manufacturing method of the electronic component of the first embodiment described above includes the following steps (1) to (7) and schematic process cross-sectional views of FIGS. 1 (a) to 1 (m) and FIG. It explains using.

なお、第2から第5の実施の形態も同様の製造にて製造した。各層の構成などが各実施の形態で異なるが、プロセス的には同じ製造方法を使用できる。   The second to fifth embodiments were manufactured in the same manner. Although the structure of each layer differs in each embodiment, the same manufacturing method can be used in terms of process.

(1)回路部品が実装されたセラミック基板の準備
図1(a)に示す、絶縁性樹脂シート131に形成されたビアホール導体134の接続性を評価するための配線パターンと、回路部品を実装するための配線パターン102a、102bが形成された、サイズ100×100mm、厚み0.4mmの4層で構成される多層のセラミック基板103を準備する。
(1) Preparation of ceramic substrate on which circuit components are mounted A wiring pattern for evaluating the connectivity of via-hole conductors 134 formed on insulating resin sheet 131 and circuit components shown in FIG. 1A are mounted. A multilayer ceramic substrate 103 composed of four layers having a size of 100 × 100 mm and a thickness of 0.4 mm, on which wiring patterns 102a and 102b are formed, is prepared.

次いで図1(b)に示す、セラミック基板の配線パターン上に、ACF、NCF、SBB、等の手段により半導体チップまたは半導体パッケージなどの半導体素子112をフリップチップ実装する。次にクリーム半田ペーストをスクリーン印刷、ディスペンス等の手段により供給し、回路部品111a・111b・111cを実装し、リフローを行って回路部品が実装されたセラミック基板104を準備する。尚、これら実装部品は絶縁性樹脂シートに内蔵されるが、二次実装時のリフロー工程で半田再溶融によりショートが発生しないように、Sn−Ag−Cu半田より融点が高いSnSb半田の様な高温タイプのクリーム半田や、融点シフト型半田あるいは導電性接着剤を用いることが好ましい。また、回路部品の実装はセラミック基板の片面側だけでも良い。   Next, a semiconductor element 112 such as a semiconductor chip or a semiconductor package is flip-chip mounted on the ceramic substrate wiring pattern shown in FIG. 1B by means of ACF, NCF, SBB, or the like. Next, a cream solder paste is supplied by means of screen printing, dispensing, etc., the circuit components 111a, 111b, and 111c are mounted, and reflow is performed to prepare the ceramic substrate 104 on which the circuit components are mounted. These mounting parts are built in the insulating resin sheet. However, in order to prevent a short circuit due to remelting of the solder in the reflow process at the time of secondary mounting, it is possible to use SnSb solder having a higher melting point than Sn-Ag-Cu solder. It is preferable to use a high-temperature type cream solder, a melting point shift type solder, or a conductive adhesive. Further, the circuit component may be mounted only on one side of the ceramic substrate.

(2)配線パターンを形成した転写形成材の準備
図1(c)は厚み0.07mmキャリア銅箔である転写形成材のキャリア層123上に離型層としてニッケルめっきを介して、厚み0.012mmの銅箔122が積層された転写形成材121(古河サーキットフォイル株式会社F−DP)である。フォトリソグラフィー技術によって、銅箔122を加工して所定のパターンを形成した転写形成材の配線パターン124を形成した転写形成材125を準備する。尚、キャリア銅箔上に配線パターンと逆パターンのレジストパターンを形成して、メッキにて配線パターンを形成後、レジストを除去する方法で転写形成材を作製しても良い。
(2) Preparation of Transfer Forming Material Formed with Wiring Pattern FIG. 1 (c) shows a thickness of 0.07 mm as a release layer on a carrier layer 123 of transfer forming material having a thickness of 0.07 mm via nickel plating. A transfer forming material 121 (Furukawa Circuit Foil Co., Ltd. F-DP) on which a 012 mm copper foil 122 is laminated. A transfer forming material 125 in which a wiring pattern 124 of a transfer forming material in which a predetermined pattern is formed by processing the copper foil 122 is prepared by a photolithography technique. The transfer forming material may be produced by forming a resist pattern opposite to the wiring pattern on the carrier copper foil, forming the wiring pattern by plating, and then removing the resist.

(3)導電性ペーストが充填された樹脂シートの準備
図1(e)〜図1(h)に示す様に、まず、無機フィラーと熱硬化性樹脂の混合物からなる絶縁性樹脂シートを作製した。エポキシ樹脂(油化シェルエポキシ製エピキュアYH−306)10重量%、アルミナフィラー(昭和電工製AS−40)90重量%を含む混合物を10分攪拌し、この混合物からドクターブレード法によって厚さ0.1mmの絶縁性樹脂シート131を作製した。次に、この絶縁性樹脂シート5枚と上下面に厚み0.02mmのPPSフィルム132を重ねてラミネートし、100×100×0.54mmの絶縁性樹脂シートを作製した後、パンチャーまたはレーザーを用いてインナービアとなる直径0.16mmの貫通穴133を形成し、この貫通穴に導電性樹脂ペーストをスクリーン印刷により充填した後、PPS保護フィルムを剥離した。ここで使用した導電性樹脂ペーストは、球形状の銅粒子85重量%と、樹脂成分としてビスフェノールA型エポキシ樹脂(油化シェルエポキシ社製「エピコート828」)3重量%と、グリシジルエステル系エポキシ樹脂(東都化成社「YD−171」)9重量%と、硬化剤としてアミンアダクト硬化剤(味の素社製「MY−24」)3重量%とを三本ロールを用いて混錬して調整した。尚、内蔵する回路部品のサイズなど状況に応じて、絶縁性樹脂シートに回路部品を内蔵するためのキャビティを加工してもかまわない。
(3) Preparation of Resin Sheet Filled with Conductive Paste As shown in FIGS. 1 (e) to 1 (h), first, an insulating resin sheet made of a mixture of an inorganic filler and a thermosetting resin was produced. . A mixture containing 10% by weight of an epoxy resin (Epicure YH-306 made of oil-shelled epoxy) and 90% by weight of an alumina filler (AS-40 made by Showa Denko) was stirred for 10 minutes. A 1 mm insulating resin sheet 131 was produced. Next, five insulating resin sheets and a PPS film 132 having a thickness of 0.02 mm are laminated on the upper and lower surfaces to form an insulating resin sheet of 100 × 100 × 0.54 mm, and then a puncher or laser is used. A through hole 133 having a diameter of 0.16 mm serving as an inner via was formed, and the through hole was filled with a conductive resin paste by screen printing, and then the PPS protective film was peeled off. The conductive resin paste used here is 85% by weight of spherical copper particles, 3% by weight of bisphenol A type epoxy resin (“Epicoat 828” manufactured by Yuka Shell Epoxy Co., Ltd.) as a resin component, and a glycidyl ester epoxy resin. (Toto Kasei Co., Ltd. “YD-171”) 9% by weight and an amine adduct curing agent (“MY-24” manufactured by Ajinomoto Co., Inc.) 3% by weight as a curing agent were kneaded and adjusted using three rolls. Note that a cavity for incorporating a circuit component in the insulating resin sheet may be processed according to the situation such as the size of the built-in circuit component.

(4)積層体の準備
図1(i)に示す様に、先ほど準備した転写形成材125、ビアホール導体134が形成された絶縁性樹脂シート135a、回路部品が実装されたセラミック基板104、ビアホール導体が形成された絶縁性樹脂シート135bおよび厚さ0.035mmの銅箔でなる金属箔141を、絶縁性樹脂シートに形成されたビアホール導体134によって、セラミック基板の一方の主面に形成される配線パターン102aと転写形成材の配線パターン124および、セラミック基板の他方の主面に形成される配線パターン102bと銅箔からなる金属箔141とが電気接続する様に位置合わせされた積層体を準備する。
(4) Preparation of Laminated Body As shown in FIG. 1 (i), the transfer forming material 125 prepared earlier, the insulating resin sheet 135a on which the via-hole conductor 134 is formed, the ceramic substrate 104 on which circuit components are mounted, and the via-hole conductor The wiring formed on one main surface of the ceramic substrate by the via-hole conductor 134 formed on the insulating resin sheet, with the insulating resin sheet 135b formed with a metal foil 141 made of copper foil having a thickness of 0.035 mm. A laminate is prepared in which the pattern 102a, the wiring pattern 124 of the transfer forming material, the wiring pattern 102b formed on the other main surface of the ceramic substrate, and the metal foil 141 made of copper foil are aligned so as to be electrically connected. .

(5)熱プレスにより絶縁性樹脂シートを硬化して積層体を一体化する
図1(j)〜図1(i)に示す様に、先ほど準備した積層体の上下面に厚み2mmのセラミックベース151と、厚み2mmのクッション材152を置き加熱プレート153にて加圧加熱することで一体化させた後、転写形成材のキャリア層123を剥離して本発明の電子部品の前駆体を作製した。ここで、154は、加熱するためのヒーターである。加圧加熱は熱プレス機を用いて、加熱温度は200℃、圧力は3MPa、加圧加熱時間は2時間とした。絶縁性樹脂シートおよびビアホール導体に含まれるエポキシ樹脂も完全に硬化し、絶縁性樹脂シートに形成されたビアホール導体を通してセラミック基板の配線パターン102a・102bと、転写形成材の配線パターン124および金属箔108が電気接続された。上述のクッション材152は、熱プレスの加熱プレートの平行度や平面度の狂い等を吸収して均圧化を図るのが目的である。
(5) Curing the insulating resin sheet by hot pressing to integrate the laminated body As shown in FIGS. 1 (j) to 1 (i), a ceramic base having a thickness of 2 mm is formed on the upper and lower surfaces of the previously prepared laminated body. 151 and a cushioning material 152 having a thickness of 2 mm are placed and integrated by heating with a heating plate 153, and then the carrier layer 123 of the transfer forming material is peeled off to produce a precursor of the electronic component of the present invention. . Here, 154 is a heater for heating. Pressurization heating was performed using a hot press machine, the heating temperature was 200 ° C., the pressure was 3 MPa, and the pressure heating time was 2 hours. The epoxy resin contained in the insulating resin sheet and via hole conductor is also completely cured, and the wiring patterns 102a and 102b of the ceramic substrate, the wiring pattern 124 of the transfer forming material, and the metal foil 108 are passed through the via hole conductor formed in the insulating resin sheet. Was electrically connected. The above-described cushioning material 152 aims to equalize pressure by absorbing the parallelism and flatness of the heating plate of the hot press.

積層体を、金属プレートやクッション材で直接挟んで加圧加熱した場合、セラミック基板101と、金属プレート、クッション材、転写形成材のキャリア層、銅箔および絶縁性樹脂シート131との熱膨張係数の違いによって、絶縁性樹脂シートのセラミック接触面と、逆の接触面との熱膨張量が厚み部分で異なり、このことにより図15(a)と図15(b)に示す様に、導電性樹脂シートに形成されるビアホール導体が歪むこととなる。図15(a)は、ビアホール導体の断面、図15(b)はその上面図である。積層体の上下面にセラミックベース151を配置して、セラミック基板をコアとして上下の樹脂材料や金属材料をセラミックベースで挟み込み加圧することで、加熱されても樹脂や金属材料の伸びをセラミック材料で押さえ込むことができ、図2(a)、図2(b)に示す様にビアホール導体が歪まない。図2(a)は、断面図、図2(b)は上面図である。また、セラミック基板の両面に絶縁性樹脂層を形成することで対称構造に近い構成とし、かつ加圧加熱する際に絶縁性樹脂層の伸びを押さえ込んでいるため、100×100mサイズにおいて反りが0〜0.7mmと非常に小さい。   When the laminate is directly sandwiched between a metal plate or a cushioning material and heated under pressure, the thermal expansion coefficient between the ceramic substrate 101, the metal plate, the cushioning material, the carrier layer of the transfer forming material, the copper foil, and the insulating resin sheet 131. The difference in thermal expansion between the ceramic contact surface of the insulating resin sheet and the opposite contact surface differs in the thickness portion, and as a result, as shown in FIGS. 15 (a) and 15 (b), the conductivity is increased. The via hole conductor formed in the resin sheet is distorted. FIG. 15A is a cross-sectional view of the via-hole conductor, and FIG. 15B is a top view thereof. The ceramic base 151 is disposed on the upper and lower surfaces of the laminate, and the ceramic substrate is used as a core. The upper and lower resin materials and metal materials are sandwiched between the ceramic bases and pressed. The via-hole conductor is not distorted as shown in FIGS. 2 (a) and 2 (b). 2A is a cross-sectional view, and FIG. 2B is a top view. Further, since the insulating resin layers are formed on both sides of the ceramic substrate, the structure is close to a symmetric structure, and the elongation of the insulating resin layer is suppressed when being heated under pressure. It is very small with ~ 0.7mm.

(6)電子部品の作製
先ほど作製された電子部品の前駆体を分割加工ライン155に沿ってダイシング加工によって分割し、20×20mm、厚み1.6mmの本発明の電子部品を(16個/基板)作製した。
(6) Production of electronic component The electronic component precursor produced earlier is divided by dicing along the dividing line 155 to obtain the electronic component of the present invention having a size of 20 × 20 mm and a thickness of 1.6 mm (16 pieces / board). ) Made.

(7)二次実装
次に、作製した電子部品を厚み1mmのFR−4の配線基板に、半田ペーストを使用してLGA実装によって二次実装した電子部品搭載装置を作製した。
(7) Secondary mounting Next, an electronic component mounting apparatus in which the manufactured electronic component was secondarily mounted on a FR-4 wiring board having a thickness of 1 mm by LGA mounting using a solder paste was manufactured.

ここで比較例として図16に示す、セラミック基板の他方の主面には絶縁性樹脂層が無い電子部品を作製しLGA実装によって二次実装した電子部品搭載装置を作製した。   Here, as an example for comparison, an electronic component mounting apparatus in which an electronic component having no insulating resin layer on the other main surface of the ceramic substrate shown in FIG. 16 was manufactured and secondarily mounted by LGA mounting was manufactured.

評価は、本発明の電子部品を二次実装した電子部品搭載装置および比較の電子部品搭載装置、各50個を用い、液槽熱衝撃試験(−55℃の恒温槽に5分浸漬後に125℃の恒温槽に5分浸漬)を1000回行い、ビアホール導体と二次実装部の電気接続抵抗で行った。その結果、比較例の電子部品搭載装置では18個がビアホール導体、42個が二次実装の電気接続不良が発生したのに対して、本発明の電子部品を二次実装した電子部品搭載装置ではビアホール導体および二次実装の電気接続不良が発生しなかった。   The evaluation was performed by using an electronic component mounting apparatus in which the electronic component of the present invention was secondarily mounted and a comparative electronic component mounting apparatus, 50 pieces each, and a liquid bath thermal shock test (125 ° C. after being immersed in a thermostatic bath at −55 ° C. for 5 minutes. Was immersed in a constant temperature bath for 5 minutes) 1000 times, and the electrical connection resistance between the via-hole conductor and the secondary mounting portion was performed. As a result, in the electronic component mounting apparatus of the comparative example, 18 poorly connected electrical connections occurred in the via hole conductor and 42 in the secondary mounting, whereas in the electronic component mounting apparatus in which the electronic component of the present invention was secondary mounted, There was no electrical connection failure between the via-hole conductor and the secondary mounting.

尚、本実施例1では、二次実装面の配線パターンを転写パターンとしたが、多層フレキ基板でも良い。また、回路部品の実装面は片面でも良い。   In the first embodiment, the wiring pattern on the secondary mounting surface is the transfer pattern, but a multilayer flexible substrate may be used. Further, the circuit component mounting surface may be one side.

このように本発明の電子部品は、セラミック基板の両面に絶縁性樹脂シートと配線パターンが形成された基材の積層体を、加圧加熱して一体化する際に、積層体の上下面にセラミックベースを配置することで、異種積層構成に起因するビアホール導体の歪みと基板反りを緩和し、二次実装の電気接続信頼性を高める効果がある。   As described above, the electronic component according to the present invention is formed on the upper and lower surfaces of the laminate when the laminate of the base material in which the insulating resin sheet and the wiring pattern are formed on both surfaces of the ceramic substrate is pressed and heated. By disposing the ceramic base, there is an effect that the distortion of the via-hole conductor and the warpage of the substrate due to the heterogeneous laminated structure are alleviated and the electrical connection reliability of the secondary mounting is improved.

本発明は、セラミック基板を含む異種積層構造において、耐衝撃性に優れ、インナービア接続および、二次実装の電気接続信頼性の高い電子部品および、その電子部品を製造する際に有用である。   INDUSTRIAL APPLICABILITY The present invention is useful in manufacturing an electronic component having excellent impact resistance, high inner via connection, secondary mounting electrical connection reliability, and the electronic component in a heterogeneous laminated structure including a ceramic substrate.

(a)〜(m)本発明の第1の実施の形態における電子部品の製造方法示す工程断面図(A)-(m) Process sectional drawing which shows the manufacturing method of the electronic component in the 1st Embodiment of this invention (a)本発明の第1〜5の実施の形態におけるビアホール導体状態を示す断面図、(b)本発明の第1〜5の実施の形態におけるビアホール導体状態を示す平面図(A) Sectional view showing via-hole conductor state in first to fifth embodiments of the present invention, (b) Plan view showing via-hole conductor state in first to fifth embodiments of the present invention (a)〜(c)本発明の第2の実施の形態における電子部品の製造方法示す工程断面図(A)-(c) Process sectional drawing which shows the manufacturing method of the electronic component in the 2nd Embodiment of this invention. (a)と(b)本発明の第3の実施の形態における電子部品の製造方法示す工程断面図(A) And (b) Process sectional drawing which shows the manufacturing method of the electronic component in the 3rd Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention 本発明の第4の実施の形態における電子部品の断面図Sectional drawing of the electronic component in the 4th Embodiment of this invention (a)〜(e)従来の電子部品の製造方法示す工程断面図(A)-(e) Process sectional drawing which shows the manufacturing method of the conventional electronic component 従来の電子部品の前駆体を示す断面図Sectional view showing a precursor of a conventional electronic component (a)従来の電子部品のビアホール導体の状態を示す断面図、(b)従来の電子部品のビアホール導体の状態を示す平面図(A) Sectional drawing which shows the state of the via-hole conductor of the conventional electronic component, (b) Top view which shows the state of the via-hole conductor of the conventional electronic component 従来の電子部品の断面図Sectional view of conventional electronic components

符号の説明Explanation of symbols

101、301 セラミック基板
102a、102b、302a、302b 配線パターン
111a〜111c、114a〜114b、311a〜311c 回路部品
112、113、312 半導体素子
121 転写形成材
123、323 転写形成材のキャリア層
124、324 転写形成材の配線パターン
131、131a、131b 絶縁性樹脂シート
134、334 ビアホール導体
141 金属箔
151 セラミックベース
152、352 クッション材
143、343 電子部品の前駆体
126 樹脂多層基板
153、353 加熱プレート
356 金属プレート
101, 301 Ceramic substrate 102a, 102b, 302a, 302b Wiring pattern 111a-111c, 114a-114b, 311a-311c Circuit component 112, 113, 312 Semiconductor element 121 Transfer forming material 123, 323 Transfer forming material carrier layer 124, 324 Wiring pattern 131, 131a, 131b Insulating resin sheet 134, 334 Via hole conductor 141 Metal foil 151 Ceramic base 152, 352 Cushion material 143, 343 Precursor of electronic component 126 Resin multilayer substrate 153, 353 Heating plate 356 Metal plate

Claims (10)

セラミック基板と、ビアホールに導電性樹脂組成物を充填してなるビアホール導体を有した未硬化の絶縁性樹脂シートと、樹脂多層基板、または、金属箔とを積層し、
上下面にセラミック板を配置し、加圧加熱して前記未硬化の絶縁性樹脂シートを硬化させ、前駆体を作製し、前記前駆体を分割し電子部品を作製することを含むことを特徴とする電子部品の製造方法。
Laminating a ceramic substrate, an uncured insulating resin sheet having a via hole conductor formed by filling a via hole with a conductive resin composition, a resin multilayer substrate, or a metal foil,
Including placing ceramic plates on the upper and lower surfaces, pressurizing and heating to cure the uncured insulating resin sheet, producing a precursor, and dividing the precursor to produce an electronic component; Manufacturing method for electronic parts.
前記セラミックス基板には、電子部品が実装されている請求項1記載の電子部品の製造方法。 The method of manufacturing an electronic component according to claim 1, wherein an electronic component is mounted on the ceramic substrate. 前記樹脂多層基板がポリイミド、アラミド、PET、PPS、PEN、テフロン(登録商標)から選ばれる少なくとも一つのフィルムベース材を用いたフレキ基板であることを特徴とする請求項1または2に記載の電子部品の製造方法。 3. The electron according to claim 1, wherein the resin multilayer substrate is a flexible substrate using at least one film base material selected from polyimide, aramid, PET, PPS, PEN, and Teflon (registered trademark). A manufacturing method for parts. 前記絶縁性樹脂シートが、無機フィラー50%体積〜75%体積と熱硬化性樹脂とを含む混合物からなることを特徴とする請求項1ないし3のいずれかに記載の電子部品の製造方法。 4. The method of manufacturing an electronic component according to claim 1, wherein the insulating resin sheet is made of a mixture containing 50% to 75% volume of an inorganic filler and a thermosetting resin. 前記無機フィラーが、Al23、SiO2、MgO、BNおよびAlNから選ばれる少なくとも一つの無機フィラーを含むことを特徴とする請求項4記載の電子部品の製造方法。 Wherein the inorganic filler is, Al 2 O 3, SiO 2 , MgO, method of manufacturing an electronic component according to claim 4, characterized in that it comprises at least one inorganic filler selected from BN and AlN. 第1の配線パターンを有するセラミック基板と、
前記セラミック基板の第1の主面に接着され、導電性樹脂組成物からなるビアホール導体を有した絶縁性樹脂シート層と、
前記絶縁性樹脂シートに接着され、前記ビアホール導体により前記第1の配線パターンと電気的に接続される第2の配線パターンまたは、第2の配線パターンを有する樹脂多層層と、
前記セラミック基板の第2の主面に接着される絶縁性樹脂シート層とを備えたことを特徴とする電子部品。
A ceramic substrate having a first wiring pattern;
An insulating resin sheet layer having a via-hole conductor made of a conductive resin composition, bonded to the first main surface of the ceramic substrate;
A second wiring pattern bonded to the insulating resin sheet and electrically connected to the first wiring pattern by the via-hole conductor, or a resin multilayer layer having a second wiring pattern;
An electronic component comprising: an insulating resin sheet layer bonded to the second main surface of the ceramic substrate.
前記セラミック基板の第1の主面および第2の主面の少なくとも一方に、前記絶縁性樹脂シートに内蔵した状態で、前記第1の配線パターンに実装した回路部品をさらに備えたことを特徴とする請求項6記載の電子部品。 A circuit component mounted on the first wiring pattern in a state of being incorporated in the insulating resin sheet is further provided on at least one of the first main surface and the second main surface of the ceramic substrate. The electronic component according to claim 6. 前記回路部品が半導体素子を含むことを特徴とする請求項7記載の電子部品。 The electronic component according to claim 7, wherein the circuit component includes a semiconductor element. 前記セラミック基板の第2の主面に接着され、導電性樹脂組成物からなるビアホール導体を有した絶縁性樹脂シート層と、
前記絶縁性樹脂シートに接着される第3の配線パターンまたは、第3の配線パターンを有した樹脂多層基板層または、導電性膜層を備え、前記ビアホール導体によって前記セラミック基板層の第1の配線パターンと、前記第3の配線パターンまたは導電性膜層とが電気的に接続された請求項7または8記載の電子部品。
An insulating resin sheet layer having a via-hole conductor made of a conductive resin composition, bonded to the second main surface of the ceramic substrate;
A third wiring pattern bonded to the insulating resin sheet, a resin multilayer substrate layer having a third wiring pattern, or a conductive film layer, and the first wiring of the ceramic substrate layer by the via-hole conductor The electronic component according to claim 7 or 8, wherein the pattern and the third wiring pattern or the conductive film layer are electrically connected.
前記第3の配線パターンに、回路部品を実装したことを特徴とする請求項9記載の電子部品。 The electronic component according to claim 9, wherein a circuit component is mounted on the third wiring pattern.
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