JP2011145971A - Method of designing semiconductor integrated circuit - Google Patents

Abstract

A design method of a semiconductor integrated device in which TAT for determining the arrangement of power supply pads of a semiconductor integrated circuit is further shortened.
A CAD design tool 5 as a method for designing a semiconductor integrated circuit includes a reference value of power supplied to each power supply pad based on the amount of current that can be supplied to the power supply pad that supplies a power supply potential to a semiconductor chip. The power consumption reference value is set as a power reference value, and the semiconductor chip area is divided until the area becomes a power consumption divided area equal to or lower than the power consumption reference value, and the power supply potential is supplied to the internal circuit of the semiconductor chip. A power supply pad is arranged on the power supply wiring that is closest to the center of the defined area as the divided area.
[Selection] Figure 2

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a method for designing a semiconductor integrated circuit using bonding wires.

  In the semiconductor field, there are semiconductor integrated circuits using bonding wires. Such a semiconductor integrated circuit is used in the consumer field which is particularly inexpensive. A semiconductor integrated circuit using a bonding wire has a semiconductor chip and a substrate, a power supply pad and an electrode pad on the semiconductor chip, and a bonding lead on the substrate. Then, the bonding lead and the power supply pad and the power supply pad and the electrode pad are connected by a bonding wire. By connecting with a bonding wire, a power supply voltage is applied to the semiconductor chip via a bonding lead and a power supply pad.

  Nowadays, due to the multi-functionality of the semiconductor chip internal circuits, the semiconductor chip has a mixture of blocks with high functionality and high power consumption and blocks with low functionality and low power consumption. As described above, in a semiconductor chip having a difference in power consumption between blocks, there is a possibility that the power consumption is biased depending on the area of the chip, resulting in insufficient supply of power to some circuits. Therefore, it is necessary to consider the stable power supply when arranging the power supply pads. For stable power supply, it is necessary to arrange power pads in consideration of a voltage drop (IR-Drop) generated on the power wiring.

  As described above, the determination of the pad arrangement must take into account stable power supply to each block and IR-Drop. As a result, the TAT (turn around time) for determining the arrangement of the power supply pads is increased, and as a result, the overall development period of the semiconductor integrated circuit is prolonged. Therefore, the TAT for determining the arrangement of the power supply pads is increased. The need for shortening has increased.

  Patent Document 1 discloses a technique for providing an electrode arrangement method in a semiconductor device that suppresses IR-Drop of a semiconductor integrated circuit.

  FIG. 14 is a flowchart showing the electrode arrangement method of the semiconductor integrated circuit described in Patent Document 1. First, as an initial setting, information necessary for calculating the bonding pad position is input. This information includes the size of the semiconductor chip, the position and number of power supply pads arranged around the semiconductor chip, and the like. Furthermore, various conditions such as an end condition (number of points and the number of simulated loops), a limit IR-Drop value, an assembly constraint, and a replacement probability, which will be described later, are appropriately included as necessary. Furthermore, the critical IR-Drop value and the importance level for the assembly constraint can be input as appropriate (step S111).

  Next, the central portion of the semiconductor chip is divided into meshes (step S112), and a position where the vertical and horizontal lines intersect is set as a candidate point for bonding pad arrangement, and a predetermined number of electrode pads are uniquely arranged randomly. (Step S113). In this case, the mesh interval may be a fixed value based on a parameter, or may be a value designated individually by an operator. At this time, it is also possible to limit the bonding pad arrangement position by narrowing a certain range in consideration of assembly constraints (particularly the bonding wire length). That is, by considering the bonding wire length with respect to the power supply pad, the area where the electrode pad can be arranged on the semiconductor chip can be limited in advance to the area surrounded by the thick line frame (see FIG. 4 of Patent Document 1). .

  In addition, by inputting assembly constraints such as the maximum and minimum rule values of the bonding wire and the plane arrangement angle of the wire, the semiconductor can be limited to a range in which the bonding wire can be stretched from each power supply pad (generally fan-shaped). A region where the electrode pad can be arranged on the chip can be limited in advance to a region surrounded by a fan-shaped frame (see FIG. 5 of Patent Document 1). Note that the plane layout angle of the wire is input because the IR-Drop improvement effect is small even if the internal bonding pad is disposed near the periphery of the chip, so that the angle is set to about 90 degrees. Can be a candidate point. In this way, narrowing down candidate points in advance has the advantage of shortening the processing time.

  Next, information on the voltage drop at the bonding pad position at the present time is calculated using the IR-Drop analysis tool (step S114). This IR-Drop analysis tool is commercially available. Note that the potential distribution on the semiconductor chip is calculated by the IR-Drop analysis tool in a state where a predetermined number of electrode pads are arranged on the semiconductor chip in advance. Therefore, it is possible to refer to the form of the electrode pad initially arranged when the electrode pad arrangement is changed thereafter, and the electrode pad arrangement can be easily changed.

  Next, information on the maximum value and average value of the voltage drop on the semiconductor chip obtained by the IR-Drop analysis tool is scored using a calculation formula based on a score calculation graph. When the IR-Drop limit value input in advance is exceeded, the electrode pad position is set to a large value obtained by multiplying 100 points by 100 times so that the electrode pad position is not adopted. The points of the maximum value and the average value are obtained by multiplying the importance degree inputted in advance and the score of each item (step S115).

  Next, the path from the power supply pad at the periphery of the semiconductor chip to the measurement point via the bonding wire and the power supply wiring in the chip, and the path from the electrode pad at the center of the semiconductor chip to the measurement point via only the power supply wiring in the chip The resistance value at and is calculated at the measurement point (step S116). The resistance value is calculated by preparing the resistance value per unit length as a library for each bonding wire and chip wiring, and multiplying the resistance value per unit length by the bonding wire length or chip wiring length (linear distance). To do.

  Next, based on the calculation result at the measurement point, the average value and the maximum value of the resistance value are scored using a calculation formula based on the score calculation graph. The maximum value and the average value are multiplied by the importance level inputted in advance, and the score of each item is set (step S117).

  Next, in the state of the bonding pad position at the present time, the peripheral power supply pad and the electrode pad at the center of the chip are connected by a bonding wire, and the rule determination regarding the assembly constraint is performed. As an example of the determination content, a determination is made regarding the bonding wire length, the distance between bonding wires, and the like (step S118). The bonding wire length is calculated by calculating the linear distance from the center of the power supply pad on the peripheral pad side to the center of the chip internal pad. As the distance between bonding wires, the shortest distance of the bonding wire from the chip peripheral pad to the chip internal pad is calculated.

  Next, the result of the bonding wire length is applied to the rule value and scored using a calculation formula based on the score calculation graph (step S119). In the assembly constraint item, since assembly outside the range of the rule value is impossible, the value is set to a large value obtained by multiplying 100 points by 100 times.

  Similarly, the result of the distance between bonding wires is applied to the rule value, and scored using a calculation formula based on the score calculation graph (step S119). The inter-wire distance cannot be assembled only when the distance is short. Therefore, when the measurement result is less than the rule value, the distance between the wires is set to a large value such as 100 times 100 times.

  Regarding the bonding wire length and bonding wire interval, the maximum value and the average value are obtained by multiplying the importance number inputted in advance and the score of each item. The total points are calculated by adding the points calculated for each item of IR-Drop, resistance value, and assembly constraint (step S119). This total score can be expressed as a score table.

  When the total score reaches the score input in step S111, the process is terminated, and the electrode pad is arranged on the semiconductor chip based on the result obtained by the simulation described above (step S123). On the other hand, when the total score has not reached the score input in step S111, the process returns to step S31 to rearrange the electrode pads again, and similarly, the operations from step S32 to S20 are performed. In this case, if the number of points calculated after the second time is improved as compared with the previous one, the position of the bonding pad is determined, and if not, the replaced bonding pad position is returned to the original ( Step S121).

  It can be said that the smaller the total score is, the better the result is. Therefore, if the score is smaller than the previous result, the current pad position and the total score are stored. Otherwise, the previous pad position is returned. If the replacement probability (probability for determining whether to return the pad position) is specified in advance, the current pad position and the total score are stored with the specified probability even if the score is not improved. By setting the replacement probability to 0%, it is possible to always return the pad position to the original if it is not improved. When the score reaches the pre-input end score, the pad position is output as the final result.

  Further, depending on the designation of the end point, there is a possibility that the number of points will not be reached forever, and the above-mentioned repeated simulation may become an infinite loop. Therefore, the maximum number of loops can be designated as the end condition. If the number of loops reaches the specified number of loops, the process is terminated, and the bonding pad position with the best (smallest) score is output as the final result (step S122).

  The data obtained in steps S31 to S120, the score graph, and the like are stored and displayed on a display device or the like as necessary. Further, the data finally obtained through step S122 (electrode pad arrangement form) is output to the output device (step S123).

  In the embodiment of Patent Document 1, IR-Drop of a semiconductor chip, a power supply pad, an electrode pad, a bonding wire connecting the power supply pad and the electrode pad, and a power supply in the semiconductor chip electrically connected to the electrode pad Although the resistance value resulting from the wiring and the assembly constraint of the semiconductor device are evaluated and analyzed in this order and scored, the order of the evaluation analysis can be changed as appropriate. For example, after the resistance value evaluation analysis, the IR-Drop evaluation analysis may be performed, and the assembly constraint evaluation analysis may be performed. Furthermore, after assembly constraint evaluation analysis, IR-Drop evaluation analysis and resistance value evaluation analysis can be performed.

JP 2008-270439 A

  In the technique described in Patent Document 1, bonding pads are randomly arranged at the center of the chip. However, in a semiconductor integrated circuit in which the distribution of power consumption is biased, when a predetermined number of electrode pads are randomly arranged, power consumption is concentrated on some electrode pads. As a result, an IR-Drop exceeding the design allowable limit value may occur. In this case, since iteration is repeated many times, TAT for determining the arrangement of power supply pads is prolonged. There's a problem.

  The method for designing a semiconductor integrated circuit according to the present invention sets a power reference value as a reference value of power to be supplied to each power supply pad based on the amount of current that can be supplied to the power supply pad that supplies the power supply potential to the semiconductor chip. The power supply line that divides the semiconductor chip area until the area becomes a divided area of power consumption equal to or lower than the power reference value, and supplies the power supply potential to the internal circuit of the semiconductor chip. A power pad is placed on the wiring. Thereby, the number and arrangement of the power supply pads can be determined more easily.

  According to the present invention, it is possible to provide a design method of a semiconductor integrated device in which TAT for determining the arrangement of power supply pads of a semiconductor integrated circuit is further shortened.

1 is a diagram illustrating a configuration of a system according to a first exemplary embodiment. 3 is a flowchart showing a method for designing a semiconductor chip according to the first embodiment; 3 is a flowchart showing details of a semiconductor chip design method according to the first exemplary embodiment; 1 is a diagram illustrating a semiconductor integrated circuit according to a first embodiment; FIG. 3 is a diagram showing a chip area according to the first embodiment. FIG. 3 is a diagram showing a chip area according to the first embodiment. FIG. 3 is a diagram showing a chip area according to the first embodiment. 3 is a flowchart showing an operation for determining the arrangement of power supply pads according to the first exemplary embodiment; FIG. 3 is a diagram showing a chip area according to the first embodiment. 6 is a flowchart illustrating a semiconductor chip design method according to a second embodiment; It is a figure which shows the chip area concerning Embodiment 2. FIG. It is a figure which shows the chip area concerning Embodiment 2. FIG. It is a figure which shows the chip area concerning Embodiment 2. FIG. It is a flowchart which shows the electrode placement method of the conventional semiconductor integrated circuit.

Embodiment 1 of the present invention
Embodiments of the present invention will be described below with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one. In addition, the configuration of each device illustrated in the following drawings is realized by, for example, executing a program read into a storage device on a computer (such as a PC or a portable terminal device). Further, these programs are stored in an information storage medium such as a CD-ROM or an optical disk, or distributed via a network such as the Internet and installed in a computer.

  FIG. 1 is a diagram illustrating a configuration of a system according to the present embodiment. The system according to the present embodiment includes a computer apparatus 1 such as an engineering workstation and a server 2 having a recording medium 3, and the server 2 is connected to the computer apparatus 1 via a network such as the Internet 4. Yes.

  The recording medium 3 stores an execution program, model formulas, model parameters, and the like and is held in the server 2. The recording medium 3 further has a CAD design tool 5 (circuit editor, layout editor, etc.). The CAD design tool 5 is downloaded to the computer apparatus 1 via the network 4. The downloaded CAD design tool 5 is stored in a local hard disk or memory or the like of the computer apparatus 1, and a semiconductor integrated circuit can be designed using the CAD design tool 5. The circuit editor and layout editor are a circuit creation tool (circuit editor: circuit Edit (er)) and a layout creation tool (layout Edit (er)). The circuit creation tool includes an RTL (Register Transfer Level) design and circuit synthesis tool. Layout creation tools include element design and automatic connection tools.

  In the method of designing a semiconductor integrated circuit according to the present embodiment, the occurrence of IR-Drop exceeding a design allowable limit value is prevented. Therefore, first, based on the amount of current that can be supplied to the power supply pad that supplies the power supply potential to the semiconductor integrated circuit (semiconductor chip), the power consumption as a power reference value that is the reference value of the power supplied to each power supply pad. Set the reference value. Next, the semiconductor chip area is divided until the area becomes a power consumption division area (determined area) equal to or lower than the power consumption reference value. When the division is completed, the power supply pad is arranged on the power supply wiring closest to the center of the determined area among the power supply wirings for supplying the power supply potential to the internal circuit of the semiconductor chip. In this way, by dividing the area of the semiconductor chip until the power consumption is less than the power consumption reference value, it is possible to prevent current from concentrating on a specific power supply pad and more easily determine the number and position of the power supply pads. can do.

  Hereinafter, the design method of the semiconductor integrated circuit according to the present embodiment will be described in more detail. FIG. 2 is a flowchart showing a semiconductor chip design method according to this embodiment. First, a power consumption reference value is set based on the amount of power that can be supplied to one power supply pad (step S21).

  Next, among the power supply wirings for supplying the power supply potential to the internal circuit of the semiconductor chip, the one having the smallest resistance value per unit area (hereinafter referred to as power supply wiring having a small ρS) is arranged in a direction substantially orthogonal to the wiring direction. A semiconductor chip area (hereinafter referred to as a chip area) is divided into two (step S22).

  The chip area is divided into areas where the power consumption in the area exceeds the power consumption reference value (further need to be divided) as the unconfirmed area (first area), and power consumption in the area is consumed. The area within the power reference value is referred to as a confirmed area (divided area). Here, a case will be described in which the area after the above-mentioned two division (hereinafter referred to as ½ area) is an undetermined area.

  Next, the ½ area is divided into a plurality of parts in a direction substantially parallel to the power supply wiring having a small ρS so that the power consumption of the ½ area falls within the power consumption reference value (step S23). As a result, all unconfirmed areas are determined areas. Then, the power supply pads are arranged on the power supply wiring with the small ρS closest to the center among the power supply wirings with the small ρS arranged in each fixed area (step S24).

  Here, when the power supply pad is arranged on the power supply wiring having a small ρS, the distance from the side substantially parallel to the wiring direction of the power supply wiring to the power supply wiring is long when the power supply wiring is located at the center of the chip area. Become. As a result, the length of the bonding wire becomes long and the assembly standard cannot be satisfied. However, from the two sides in the direction orthogonal to the direction of the power supply wiring with a small ρS, even when the power supply wiring is located at the center of the chip area, the power supply pad can be arranged at the peripheral portion, The length of the bonding wire can be shortened.

  In other words, when arranging the power supply pad, it is preferable to arrange it at the periphery of the chip area as much as possible. This is because if the power supply pad is arranged at the center of the chip area, the bonding wire becomes long and the assembly standard may not be satisfied.

  On the other hand, in the design method according to the present embodiment, first, the chip area is divided into two in the direction orthogonal to the power supply wiring having a small ρS. Therefore, each of the two divided areas has a side perpendicular to the power supply wiring having a small ρS. Since the distance from the side to the power supply pad on the power supply wiring with small ρS is less than ½ of the chip area, the bonding wire length can be shortened.

  Furthermore, by arranging the power supply pad on the power supply wiring having a small ρS, the power supply wiring having a small ρS and the substrate can be connected through the power supply pad. For this reason, the power supply potential can be efficiently supplied to the internal circuit by supplying power to the internal circuit using the power supply wiring having a small ρS.

  Next, the semiconductor chip dividing method will be described in more detail. FIG. 3 is a flowchart showing details of a method of dividing the chip area of the semiconductor chip. FIG. 4 is a diagram showing a semiconductor integrated circuit. The semiconductor integrated circuit 10 includes a semiconductor chip 42 and a package 43. The semiconductor chip 42 has a plurality of power supply lines L01 having a small ρS for supplying a power supply potential to the internal circuit, and a power supply pad 44 for connecting the package and the semiconductor chip 42. The package 43 has bonding leads 45 for connecting the semiconductor chip 42 and the package 43. The semiconductor integrated circuit 10 supplies power to the internal circuits in the semiconductor chip 42 by connecting the power supply pads 44 and the bonding leads 45 with bonding wires.

  5 to 7 are diagrams showing a chip area. In the figure, an area indicated by a thick black broken line indicates an area currently being processed. In addition, the numbers indicated by () in each area indicate power consumption in the area. Furthermore, it is assumed that a power supply wiring having a small ρS is wired in the vertical direction on the chip area. Further, the power consumption of the entire chip area is set to 700, and the power consumption reference value is set to 100. That is, in this process, the chip area is divided so that the power consumption in the area is less than 100.

  FIG. 5A shows an unconfirmed area. First, as shown in FIG. 5A, a selection area A01 (entire chip area) indicated by a thick black broken line is a processing target area, and the selection area A01 is divided into two in a direction orthogonal to the power supply wiring having a small ρS. To 1/2 area C01 and 1/2 area C02 (step S30).

  Next, power consumption in each ½ area C01, C02 is calculated. In this example, it is assumed that the power consumption of the ½ area C01 on the upper side of the paper is 375 and the power consumption of the ½ area C02 on the lower side of the paper is 325.

  Further, either one of the two areas is selected as both of these areas and set as a selection area A02 that is an area to be divided (step S31). In this example, as shown in FIG. 5B, first, the ½ area C01 is selected and set as the selection area A02.

  Next, as the initial value of the division number N, the number of division of the selection area is set to two divisions (N = 2) (step S32), and the selection area A02 is set in a direction parallel to the wiring direction of the power supply wiring having a small ρS Are equally divided by the division number N = 2 (step S33). As shown in FIG. 5B, the selection area A02 is equally divided into areas C03 and C04 with a division number N = 2.

  Next, the power consumption calculation for each equally divided area is performed (for example, in order from the left area), and it is determined whether the power consumption is within the power consumption reference value (step S34). Here, it is assumed that the power consumption of the area C03 is 75 and the power consumption of the area C04 is 300.

  If it is within the power consumption reference value, the confirmation flag stored in the local hard disk or memory of the computer apparatus 1 is set with the unconfirmed area as the confirmation area (step S35). If it is outside the power consumption reference value, the confirmation flag is not raised because it is an unconfirmed area (step S34: No). In FIG. 5B, the area C03 is determined as a confirmed area, and the area C04 is determined as an unconfirmed area.

  Next, it is determined whether all areas divided in step S33 are determined to be within the power consumption reference value (step S37), and if there is an area where it is not determined whether the area is within the power consumption reference value (Step S37: No), an area that is not determined whether it is within the power consumption reference value is selected (Step S36), and the process returns to Step S34 to calculate the power consumption in the selected area, and all the divided areas Determine whether the area is a confirmed area or an unconfirmed area.

  Next, when it is determined whether all the divided areas are within the power consumption reference value, the uncertain area is repeatedly divided. Specifically, the area C04 in FIG. 5B is divided again with the division number N = 2. FIG. 6A shows the chip area divided. FIG. 6A shows that the area C04 is a selection area A03 to be divided, the selection area A03 is divided into an area C05 and an area C06, and each power consumption is 150.

  When there are a plurality of unconfirmed areas of power consumption equal to or higher than the power reference value among a plurality of areas obtained by dividing the unconfirmed area, such as area C05 and area C06 in FIG. 6A, and they are adjacent to each other. Then, the plurality of adjacent unconfirmed areas are integrated, and the plurality of integrated unconfirmed areas are further divided by the number obtained by adding 1 to the number of the integrated regions.

  That is, when it is determined whether the power consumption reference value is within all the divided areas (step S37: Yes), adjacent unconfirmed areas are combined into one except for the confirmed area (step S38). ). It is determined whether there is a confirmed area among the unconfirmed areas divided into N in step S33 (step S39). If no area is confirmed (step S39: No), the division number is incremented by one (N = N + 1) Segmentation is performed (step S41). In step S39, if there is a confirmed area among the unconfirmed areas divided into N in step S33 (step S39: Yes), it is determined whether all areas are confirmed in step S40, and all areas are confirmed. Ends the process (step S40: Yes). When all the areas are not confirmed (step S40: No), the process returns to step S31 again.

  The power consumption in the areas C05 and C06 in FIG. 6A is 150, which is larger than 100, which is the power consumption reference value, so the area is not fixed (No in step S34).

  Since the area has not been confirmed, adjacent unconfirmed areas are integrated into one in step S38, and the original selection area A03 is restored. Since there is no fixed area in step S39, the process proceeds to step S41, where the division number N is increased by 1, and N = 3.

  Next, the process proceeds to step S33, and the selection area A03 is divided into three. FIG. 6B is a diagram illustrating a case where the selection area A03 is divided into three. Since the power consumption of the left area C07 obtained by dividing the selection area A03 into three is 100 and is equal to or less than the power consumption reference value 100, the process proceeds to step S35 and a confirmation flag is set to become the confirmation area C07.

  Next, in step S36, the next area is selected, and the power consumption of the middle area C08 obtained by dividing the selection area A03 into 100 is 100, which is less than the power consumption reference value 100. Therefore, the process proceeds to step S35, and a confirmation flag is set and confirmed. It becomes area C08. Similarly, since the power consumption of the area C09 is 100, a confirmation flag is set to become the confirmation area C09. In step S40, since not all areas are confirmed (step S40: No), the process returns to step S31, and the unconfirmed area C02 is selected as the selection area A04. Thereafter, the same process is performed for the selected area A04, and the process ends when all areas are determined areas whose power consumption is 100 or less.

  FIG. 7A shows a divided chip area. In FIG. 7A, the upper half of the chip area is divided into four divided areas C03, C07, C08, and C09, and the lower half is divided into fixed areas C10, C11, C12, and C13. FIG. 7B is a diagram in which a pad PA1 is provisionally arranged at the center of all the confirmed areas with respect to the confirmed area in FIG. 7A.

  Next, a method for determining the arrangement of the power supply pads will be described. The power supply pad is arranged on the power supply wiring having a small ρS that is closest to the center of the fixed area. When the chip area has an arrangement prohibition area where the power supply pad cannot be arranged based on at least the restrictions on the structure of the semiconductor, when the power supply pad is arranged, it is on the power supply wiring having a small ρS and the arrangement prohibition area. Place it in an area other than. FIG. 8 is a flowchart showing an operation for determining the arrangement of the power supply pads. FIG. 8 is a flowchart showing details of step S24 in FIG. 2, and shows processing for determining the arrangement of the power supply pads for each area divided to the power consumption reference value or less in step S23.

  First, in step S23 of FIG. 1, the division of the area is completed, and a pad is temporarily arranged at the center of each fixed area (step S51). Next, each temporarily placed pad is sequentially moved onto the power supply wiring with a small ρS in the vicinity of each temporarily placed pad (step S52). It is confirmed whether the place where the power supply pad is placed is an area where the pad placement is prohibited due to the bonding wire non-routable area or the like (step S53). If the area is outside the pad placement prohibited area (step S53: Yes), the position of the pad To end the process.

  In the case of the pad placement prohibited area (step S53: No), the power supply wiring having a small ρS is moved to the pad placement possible area (step S54). When all the pads have been moved to the area where the pads can be arranged, the process ends.

  FIG. 9 is a diagram showing a semiconductor chip 42g. The semiconductor chip 42g has a power supply line L01 having a small ρS and an arrangement prohibition area AX1, and is divided into fixed areas C03 and C07 to C13. The pad PF1 shows a state where the power supply pad is arranged at the final pad position after the movement. In step S54, the semiconductor chip 42g moves the temporarily placed pad PA1 onto the nearby power supply line L01 having a small ρS in step S52, and if the position where the pad is temporarily placed is the pad placement prohibited area AX1. , ΡS is moved to the area where the pads can be arranged on the power supply wiring with a small ρS.

  In this embodiment, the power consumption reference value of the power supply pad is set, and the area inside the chip is divided into two in the direction perpendicular to the power supply wiring having a small ρS, so that the area of ρS can be accommodated in the power consumption reference value. Since the power supply pads are further divided into a plurality of areas in parallel with the small power supply wiring, power consumption is not concentrated on some power supply pads. Therefore, IR-Drop exceeding the design allowable limit value does not occur, and the iteration is not repeated many times for the power supply pad arrangement of the semiconductor integrated circuit, so that TAT can be shortened.

Embodiment 2 of the present invention
In step S23 of FIG. 2, the semiconductor integrated circuit design method according to the present embodiment repeatedly divides an area inside the chip into two in a direction perpendicular to the power supply wiring having a small ρS in a direction substantially parallel to the power supply wiring. Instead of the divided area, the minimum area (minimum area), which is the smallest unit area that can be divided, is divided into the divided area (hereinafter referred to as 1/2 area) based on the internal circuit configuration of the semiconductor chip. A processing step of setting and integrating the minimum area in the ½ area until the sum of the power consumption in the minimum area is close to the power consumption determination value as the power reference value and is equal to or less than the power consumption determination value Have

Further, when determining the power consumption judgment value, the power consumption of the area in which the area inside the chip is divided into two in the direction perpendicular to the power supply wiring with small ρS is W ₀ , the power consumption reference value as the power reference value is W ₁ , and the minimum area When the maximum power consumption is W _M , the area inside the chip is divided into two areas perpendicular to the power supply wiring with a small ρS, and the power consumption determination value W ₂ = W ₀ / N ₀ To do. Then, when obtaining a definite area, sequential power consumption of the defined areas as integrated integrated area is sequentially integrated until the power determination value W ₂ near consumes minimal area.

  Further, when integrating the minimum areas, the minimum areas are integrated so as to form a rectangular area having a long side in the wiring direction of the power supply wiring with respect to the reference minimum area.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 10 is a flowchart showing a method of dividing a semiconductor chip into areas below the power consumption reference value. In the present embodiment, the process shown in FIG. 10 is performed in place of the process in step S23 of FIG. Other processes are the same as those shown in FIG. In the present embodiment, the power consumption of the semiconductor chip 80 is set to 700, the power consumption reference value is set to 100, and the power supply wiring having a small ρS is wired in the vertical direction as in FIG. To do.

  11 to 13 are diagrams showing the semiconductor chip 80. Areas C01 and C02 in FIG. 11 (a), C22 in FIG. 11 (b), and C24 in FIG. 12 (a) are unconfirmed areas. Area C21 in FIG. 11 (b), C23 in FIG. C25 and C26 in FIG. 12B and C27 to C30 in FIG. As in the first embodiment, the numbers in parentheses in the figure represent power consumption.

  In the present embodiment, the power consumption in the area inside the semiconductor chip is divided until the power consumption is equal to or lower than the power consumption reference value. However, unlike the first embodiment, the power consumption in the ½ area and the number of divisions are based on the power consumption. The average power consumption supplied from the power supply pad is obtained, and the region is determined in order from the end so as to be equal to or less than the average power consumption value.

  First, the area of the minimum area to be divided in advance is set (step S61). Next, one unconfirmed area is selected as the selected area for the unconfirmed area divided into two in step S22 of FIG. 2 (step S62). C01 in FIG. 11 (a) is selected to be a selection area A2 in FIG. 10 (b).

Next, the selection area A12 is divided into the minimum areas having the minimum unit area (area), and the power consumption for each minimum area is calculated (step S63). Next, the power consumption of the area divided into two in the direction orthogonal to the power supply wiring with small ρS is W ₀ , the power consumption reference value as the power reference value is W ₁ , and the maximum of the power consumption of the minimum area when the power consumption of the _{W M,} and the division number _{N 0} = power _W 0 / (power consumption levels _{W 1} - power _{W M)} to (step S64). The number obtained by rounding up the number of divisions N ₀ or less is the division number N (step S65). Figure 11 (a), the power consumption of undetermined area C01 and 375, if set to 1 the maximum power consumption W _M in the power consumption of the minimum area each calculated in step S64, the consumption of undetermined area C01 When the power 375 is divided by the power consumption reference value 100-1 (maximum power consumption of the minimum area) = 99, the division number N ₀ = 375 / 99≈3.7 is obtained (step S64). Next, as the division number N ₀ , the necessary division number N is obtained by rounding up the number after the decimal point (step S 65). Therefore, the division number N is 4.

Next, the power consumption determination value W ₂ is calculated by setting the power consumption determination value W ₂ = the power consumption W _{0 of the} undetermined area / the number N of divisions (step S66). Power determination value _{W 2} is a value 93.75 divided by the power consumption of undetermined area C01 division number 4. Consumption power determination value W ₂ obtained as described above. By integrating the minimum areas until the power consumption determination value W2 obtained in this way becomes a value equal to or greater than ₂ , the undecided area can be appropriately divided, and the power consumption of each power supply pad is almost equal. Can be.

For undetermined area within the selected area, for example, set the left minimum area of the determination area (step S67), determines whether the power consumption in the determination area less than the value W ₂ of power determination value (step S68), consumption if less than the value of the power determination value W _2, other minimum area is adjacent to the determined area, and bound the determination area is determined whether it is possible to enlarge (step S70), expanding possible, sequentially adjacent The determination area is expanded by combining the minimum area and the determination area (step S70). Here, since it is necessary to select the adjacent minimum area so that the determination area expands only within the selection area, it is necessary not to combine with the minimum area outside the selection area.

The power consumption of integrated within the area is a definite area make a determination flag Once beyond the power determination value W ₂ (step S69). In FIG. 11B, the determination area is enlarged with the minimum area at the left end of the selection area A2 as a reference, and when the power consumption becomes 94 or more, a confirmation flag is set to be the confirmation area C21. Here, when determining the power determination value W _2, (power W ₀ of undetermined _area) / - of N ₀ obtained in (power consumption levels W ₁ Maximum power consumption levels W _M of the minimum _area) The number below the decimal point is further rounded to N, and the power consumption determination value W ₂ = W ₀ / N ₀ is set. Therefore, the power consumption determination value W ₂ does not become larger than (power consumption reference value W ₁ −maximum power consumption reference value W _{M of the} minimum area), and further, the power consumption can be supplied to one power supply pad. It does not exceed the power consumption reference value set based on this. That is, when sequentially integrating the minimum areas, it is only necessary to determine whether the power consumption is equal to or higher than the power consumption determination reference value in step S69.

  Next, it is determined whether there is an undetermined area in the area selected in step S62 (step S73). If there is an undetermined area, the minimum area to the right of the confirmed area is set again as the determination area (step S74). Then, the process proceeds to a determination process after step S67. For example, FIG. 12A shows that the minimum area to the right of the confirmation area C21 is expanded as a determination area, and when the power consumption reaches 94, a confirmation flag is set to be the confirmation area C23.

Furthermore, it is power dissipation in the determination area less power determination value W ₂ (step S68: No), if there is no minimum area to bind to the determination area (Step S70: No), the determination area remaining undetermined area And a confirmation flag is set to establish a confirmation area (step S72). In FIG. 11B, the minimum area on the right side of the confirmed area C25 is expanded as a determination area. Here, the power consumption of the determination area is 93, but since there are no areas to be integrated, a confirmation flag is set to a confirmation area C26.

  Next, it is determined whether all the selected areas have been confirmed (step S75). If all the areas have not been confirmed, the process returns to step S62 and is repeated until all the areas are confirmed. To do.

  In FIG. 13A, the selection area A12 is confirmed by four divisions of the decision areas C21, C23, C25, and C26, and the selection area A13 is divided into four decision areas C27, C28, C29, and C30 by the same process. It is a figure which shows having been done. FIG. 13B is a diagram showing an example in which the pad PA1 is provisionally arranged at the center of all the confirmed areas.

  In Embodiment 2 of the present invention, the average power consumption supplied by one power supply pad is obtained based on the power consumption in the ½ area and the number of divisions, and the average power consumption is set as the power consumption determination value. The power consumption supplied from each power supply pad can be made more uniform.

  In the present embodiment, as in the first embodiment, the power consumption is not concentrated on a part of the power supply pads, so that IR-Drop exceeding the design allowable limit value does not occur. Iteration can be repeated and the TAT for determining the pad arrangement can be shortened.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Computer apparatus 2 Server 3 Recording medium 4 Internet 5 CAD design tool C01-C13, C21-C30 Area A01-A04 Selection area A11-A13 Selection area PA1 Pad 42 Semiconductor chip 43 Package 44 Power supply pad 45 Bonding lead 80 Semiconductor chip L01 Power supply Wiring PF1 pad

Claims (13)

Based on the amount of current that can be supplied to the power supply pad that supplies the power supply potential to the semiconductor chip, a power reference value that is a reference value for the power supplied to each power supply pad is set.
Dividing the semiconductor chip area until the area becomes a divided area of power consumption below the power reference value,
A method for designing a semiconductor integrated circuit, wherein the power supply pad is arranged on a power supply wiring closest to the center of the divided region among power supply wirings for supplying a power supply potential to an internal circuit of the semiconductor chip. When dividing the semiconductor chip region into a plurality of,
Dividing the semiconductor chip region into a first region by dividing the semiconductor chip region in a direction substantially orthogonal to a direction of a power supply wiring for supplying a power supply potential to an internal circuit of the semiconductor chip;
The first region is repeatedly divided in a direction substantially parallel to the power supply wiring until the power consumption of the first region is equal to or less than the power reference value, and is set as the divided region.
The method for designing a semiconductor integrated circuit according to claim 1, wherein the power supply pad is arranged on the power supply wiring closest to the center of the divided region.   The power supply wiring for arranging the power supply pad is the power supply wiring that is closest to the center of the divided region among the power supply wiring that supplies the power supply potential to the internal circuit of the semiconductor chip and has the smallest resistance value per unit area. The method for designing a semiconductor integrated circuit according to claim 1 or 2.   The semiconductor chip region has an arrangement prohibition region where the power supply pad cannot be arranged based on at least a semiconductor structural restriction. When the power supply pad is arranged, the semiconductor chip region is on the power supply wiring and the arrangement prohibition. 4. The method for designing a semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged in a region other than the region. When the first area is repeatedly divided, if there are a plurality of areas of power consumption equal to or higher than the power reference value among the plurality of areas obtained by dividing the first area, and the adjacent areas are adjacent to each other Integrating multiple areas
3. The method of designing a semiconductor integrated circuit according to claim 1, wherein the plurality of integrated first regions are further divided by a number obtained by adding 1 to the number of the integrated regions. Instead of repeatedly dividing the first region in a direction substantially parallel to the power supply wiring to be the divided region,
Based on the configuration of the internal circuit of the semiconductor chip, a minimum area that is a minimum unit area that can be divided into the first area is set,
3. The semiconductor integrated circuit according to claim 1, wherein the minimum area is integrated into the divided area until the total power consumption of the minimum area is a value close to the power reference value and equal to or less than the power reference value. Design method. When the power consumption of the entire semiconductor chip is W ₀ , the power reference value is W ₁ , and the maximum power consumption of the minimum area is W _M , the number of divisions N ₀ = W ₀ / (W ₁ −W _M ), Power consumption judgment value W ₂ = W ₀ / N ₀ ,
Wherein when obtaining the divided regions, the design of the semiconductor integrated circuit according to claim 6, wherein the power consumption of the minimum regions sequentially integrated integrated area is to the power determination value W sequentially integrated to the divided region to ₂ becomes close Method. When integrating the minimum area,
8. The method of designing a semiconductor integrated circuit according to claim 6, wherein the minimum area is integrated so as to be a rectangular area having a long side in the wiring direction of the power supply wiring with respect to the reference minimum area. A semiconductor chip;
A package for supplying a potential to the semiconductor chip,
The semiconductor chip is
Internal circuitry,
Power supply wiring for supplying a potential to the internal circuit;
A power supply pad for connecting the power supply wiring and the package,
A power reference value that is a reference value of power to be supplied is set on the power supply pad, based on the amount of current that can be supplied to supply power to the semiconductor chip.
The power supply pad divides the semiconductor chip area until the area becomes a divided area of power consumption equal to or lower than the power reference value, and among the power supply wiring for supplying a power supply potential to an internal circuit of the semiconductor chip, A semiconductor integrated circuit disposed on a power supply wiring closest to the center of the region. When dividing the semiconductor chip region into a plurality of,
Dividing the semiconductor chip region into a first region by dividing the semiconductor chip region in a direction substantially orthogonal to a direction of a power supply wiring for supplying a power supply potential to an internal circuit of the semiconductor chip;
When the first region is repeatedly divided in a direction substantially parallel to the power supply wiring until the power consumption of the first region is equal to or less than the power reference value,
The semiconductor integrated circuit according to claim 9, wherein the power supply pad is disposed on the power supply wiring closest to the center of the divided region.   The power supply wiring for arranging the power supply pad is the power supply wiring that is closest to the center of the divided region among the power supply wiring that supplies the power supply potential to the internal circuit of the semiconductor chip and has the smallest resistance value per unit area. The semiconductor integrated circuit according to claim 9 or 10. Instead of repeatedly dividing the first region in a direction substantially parallel to the power supply wiring to be the divided region,
Based on the configuration of the internal circuit of the semiconductor chip, a minimum area that is a minimum unit area that can be divided into the first area is set,
11. The semiconductor integrated circuit according to claim 9, wherein the minimum areas are integrated into the divided area until the total power consumption of the minimum area is a value close to the power reference value and equal to or less than the power reference value. When the power consumption of the entire semiconductor chip is W ₀ , the power reference value is W ₁ , and the maximum power consumption of the minimum area is W _M , the number of divisions N ₀ = W ₀ / (W ₁ −W _M ), Power consumption judgment value W ₂ = W ₀ / N ₀ ,
The divided region, a semiconductor integrated circuit according to claim 12, wherein the power consumption of the minimum regions sequentially integrated integrated region are those that are sequentially integrated until the neighboring power determination value W _2.

Images