JP2011141140A - Apparatus and method for lsi test - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and method for LSI test to reduce a test time without causing malfunction. <P>SOLUTION: The LSI test apparatus includes a test unit, a determination unit, a selection unit, and a control unit. The test unit tests in parallel a test block including designated one or more circuit blocks of a semiconductor integrated circuit having a plurality of circuit blocks which can be tested singly. The determination unit determines the quality of the operation of the circuit block on the basis of the results of the test by the test unit. The selection unit, when the test block includes a circuit block which has been determined to be faulty operation, divides the test block into a plurality of block groups. At least one block group out of the plurality of block groups includes only a circuit block which has been determined to be false operation. The control unit gives instructions for retesting the block group including only the circuit block which has been determined to be false operation to the test unit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an LSI test apparatus and a test method.

  In a test for detecting a failure in an LSI, a test pattern for failure detection is input to the circuit under test using a dedicated test circuit incorporated in the LSI circuit, and the output from the circuit under test is an expected value ( The failure is detected by checking whether the expected value). Examples of the dedicated test circuit include a scan circuit and a Logic BIST (Logic Built-In Self-Test: see FIG. 1). However, due to the recent increase in leakage current due to the miniaturization of the LSI diffusion process structure and the increase in the scale of the circuit, the influence of the fluctuation of the power supply when the circuit operates simultaneously and the sudden voltage drop due to the performance limit of the test equipment It's getting bigger. As a result, the operation of the internal circuit becomes unstable, and malfunctions are likely to occur. In particular, in the scan test and the Logic BIST test method, the simultaneous operation rate of the LSI circuit is generally higher than that in actual use, and the influence of the simultaneous operation tends to be remarkable.

  Another major problem is an increase in variation in leakage current between production lots. The power supply voltage drop due to simultaneous operation during the LSI test also varies greatly between manufacturing lots, which causes the LSIs that are likely to malfunction and those that are less likely to malfunction to be manufactured.

  A Logic BIST that is one of test methods for detecting a failure in an internal circuit of an LSI will be described. Logic BIST is applied to an LSI including a test pattern generation circuit (TPG: Test Pattern Generator) and an output result analysis circuit (ORA: Output Response Analysis). The test pattern generation circuit generates a test pattern that is input to a circuit to be tested. The output result analysis circuit analyzes the output result from the internal circuit.

  The circuit under test has two operation modes, a normal mode and a shift mode. In the normal mode, the circuit under test operates with a normal circuit configuration. In the shift mode, the data lines of the flip-flops of the circuit under test are connected in a daisy chain to form a plurality of scan chains. The input of each scan chain is connected to a test pattern generation circuit, and the output is connected to an output result analysis circuit. Therefore, when the mode is switched to the shift mode, data can be easily input from the test pattern generation circuit to each flip-flop in the LSI. In addition, data stored in the flip-flop in the normal mode can be serially output to the output result analysis circuit when the shift mode is switched. The output result analysis circuit analyzes the received data and outputs a test result. The test result is stored in the memory unit of the LSI test apparatus from the output terminal of the LSI via the interface unit. The LSI test apparatus determines whether the output test result matches the expected value. If they match, the LSI test apparatus issues a PASS determination, and if they do not match, issues a FAIL determination.

  In the case of an LSI in which the test circuit is divided into a plurality of blocks, it is possible to perform a test on a plurality of previously selected blocks in parallel (a set of blocks is referred to as a block group). Further, by determining a block group so that there are no untested blocks and testing each block group serially, it is possible to finally test all blocks.

  As shown in FIG. 1, in an LSI including circuit blocks 1 to 4, when the circuit block 1 and the circuit block 2 are collectively grouped into a block group A, and the circuit block 3 and the circuit block 4 are collectively grouped into a block group B, All circuit blocks are included in any block group. “Test each block group serially (in time series)” means that the circuit blocks 1 and 2 included in the block group A are tested in parallel (simultaneously), and then the circuit blocks included in the block group B. 3 and 4 are tested in parallel (simultaneously). By testing in this way, it is possible to test all the circuit blocks 1 to 4 while reducing the test time. In other words, when all blocks are tested simultaneously, the test time can be shortened the most, and the test time increases as the number of blocks to be serially tested increases.

  With reference to the flowchart shown in FIG. 2, a test flow in which each block group performs a failure detection test serially will be described.

  The LSI test apparatus supplies a failure detection pattern to each block group, and tests each block group in turn (step S303).

  The LSI test apparatus compares the test result output from the LSI with the expected value (step S304). If the output test result matches the expected value (step S305—YES), the LSI test apparatus makes a PASS determination (step S306). If there is a discrepancy between the output test result and the expected value (step S305—NO), a FAIL judgment is made (step S307). An LSI for which a FAIL judgment has been made is a defective product whose circuit does not operate correctly.

  When all the circuit blocks included in the LSI are tested in parallel, the power supply may be shaken due to the simultaneous operation of the circuits. In addition, an abrupt voltage drop may occur due to the performance limit of the LSI test apparatus or test jig / tool. Due to these effects, the operation of the internal circuit becomes unstable and may malfunction. In order to avoid such a malfunction, a test flow is adopted in which a plurality of block groups are determined in advance and each block group is tested in order.

  In addition, when an LSI is manufactured by a process having a large variation in leakage current, a large difference in the voltage drop of the LSI power supply occurs between manufacturing lots. Therefore, an LSI that is likely to malfunction due to simultaneous operation and an LSI that is less likely to malfunction are manufactured. For this reason, the LSI test apparatus serially tests a block group determined so as not to cause a malfunction even in a production lot having the largest leakage current. However, the test time becomes longer as the number of block groups increases. In such a method, a test is carried out with the same combination of blocks even in an LSI of a production lot with a small leakage current. However, LSIs of such production lots can often be tested without causing malfunction even with a smaller number of block groups. For this reason, the test is performed using a wasteful time.

  As a method for shortening the test time, a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2004-362157, an address assignment method thereof, and a semiconductor device control method are known. The semiconductor device, its address allocation method, and semiconductor device control method have the same main configuration, and a plurality of function macros that generate the same output signal for a predetermined input signal, and a plurality of selections corresponding to them Provide signal output. When a common address is received, at least two of the plurality of selection signal outputs are simultaneously activated, and selection means for simultaneously selecting at least two of the plurality of function macros is provided. By accessing the common address, a plurality of function macros are operated in parallel, and the processing time of the semiconductor device is shortened. In such a method, since the same function is tested at the same time, test data (test pattern) can be supplied at the same time, but the test is not performed in consideration of the influence on the simultaneous operation.

JP 2004-362157 A

  The present invention provides an LSI test apparatus and an LSI test method that reduce test time without causing malfunction.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the “DETAILED DESCRIPTION”. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In an aspect of the present invention, the LSI test apparatus (10) includes a test unit (120), a determination unit (130), a selection unit (140), and a control unit (110). The test unit (120) tests in parallel a test block including one or more designated circuit blocks (34) of the semiconductor integrated circuit (30) including a plurality of circuit blocks (34) that can be independently tested. The determination unit (130) determines the quality of the operation of the circuit block (34) based on the result of the test by the test unit (120). When the test block includes the circuit block (34) determined to be defective by the determination unit (130), the selection unit (140) distributes the test block to a plurality of block groups. At least one block group of the plurality of block groups includes only a circuit block determined to be malfunctioning. The control unit (110) instructs the test unit to retest the block group including only the circuit blocks determined to be malfunctioning.

  In another aspect of the present invention, an LSI test method includes a step of testing in parallel, a step of determining whether the operation of the circuit block is good based on a result of the test, a step of distributing, and a step of retesting. To do. In the step of testing in parallel, a test block including one or more designated circuit blocks of a semiconductor integrated circuit including a plurality of circuit blocks that can be independently tested is tested in parallel. In the allocating step, when the test block includes a circuit block determined to be malfunctioning, the test block is allocated to a plurality of block groups. At least one block group of the plurality of block groups includes only a circuit block determined to be malfunctioning. In the retesting step, a block group including only the circuit blocks determined to be malfunctioning is retested as a test block.

  According to the present invention, it is possible to provide an LSI test apparatus and an LSI test method that perform a test without causing a malfunction and without unnecessarily extending a test time, and shortening the test time.

It is a block diagram which shows the structure of LSI which mounts a test exclusive circuit. It is a flowchart which shows a test procedure. 1 is a diagram showing a configuration of an LSI test system according to an embodiment of the present invention. It is a figure which shows the structure of the test program run with the LSI test device which concerns on embodiment of this invention. 1 is a block diagram showing a configuration of an LSI to be tested according to an embodiment of the present invention. 3 is a flowchart showing an operation of the LSI test apparatus according to the embodiment of the present invention. It is a flowchart which shows the division | segmentation operation | movement of a test block group. It is a flowchart which shows other operation | movement of the LSI test apparatus which concerns on embodiment of this invention.

  Embodiments of the present invention will be described with reference to the drawings.

  As shown in FIG. 3, the LSI test system according to the embodiment of the present invention includes an LSI test apparatus 10, an LSI 30 to be tested, an interface including a test board for connecting the LSI test apparatus 10 and the LSI 30, and the like. Part (I / F part) 20. The LSI test apparatus 10 executes a test program indicating a test flow, and determines whether the operation of the LSI 30 is good or bad. The test program is stored in the auxiliary storage unit 16. The test program is transferred to the memory unit 13 based on an instruction from the input unit 11 such as a keyboard or the auxiliary input unit 15 such as a mouse by a user operation during the test execution. The central processing unit 12 executes a test program stored in the memory unit 13 and outputs a test result to the display unit 14. The test result may be stored in the auxiliary storage unit 16 and used as electronic data by other devices.

  As shown in FIG. 4, the test program includes a control unit 110, a test unit 120, a determination unit 130, and a block selection unit 140. The control unit 110 controls the test unit 120, the determination unit 130, and the block selection unit 140 to manage the test flow, and determines whether the operation of the LSI 30 is good or bad. The test unit 120 controls a clock supplied to the LSI 30 based on an instruction from the control unit 110, supplies test data (pattern) to the LSI 30, and executes a test. The determination unit 130 determines whether or not the circuit block included in the LSI 30 operates normally based on the test result output from the LSI 30. The block selection unit 140 selects a circuit block included in the LSI 30 to be tested based on the determination result of the determination unit 130.

  In the present embodiment, the LSI 30 to be tested is equipped with a Logic BIST. As shown in FIG. 5, the LSI 30 to be tested includes circuit blocks 34-1 to 3-4 and a TAP circuit (Test Access Port circuit) 32. The circuit blocks 34-1 to 4-4 each include a control circuit (CTRL) 362, a test pattern generation circuit (TPG) 364, an output result analysis circuit (ORA) 366, and a scan chain 368. In the present embodiment, four blocks of the circuit blocks 34-1 to 4-4 will be described as an example, but the number of blocks is not limited to four. Here, when it demonstrates without specifying any of the circuit blocks 34-1 to 34-4, it demonstrates as the circuit block 34. FIG.

  The TAP circuit 32 monitors the data and clock input from the LSI test apparatus 10 and controls the internal circuit of the LSI 30 during the test. The control circuit 362 generates a control signal for executing a command received from the TAP circuit 32 and supplies the control signal to a circuit in the circuit block 34. In addition, the control circuit 362 sends the test result from the output result analysis circuit 366 to the TAP circuit 32. That is, the TAP circuit 32 receives a test control signal from the LSI test apparatus 10 via a TDI (Test Data In) terminal, and exchanges a control signal with the control circuit 362 of each circuit block 34. Further, the TAP circuit 32 receives and processes the test result from the control circuit 362 of each circuit block 34 and outputs it to the LSI test apparatus 10 from a TDO (Test Data Out) terminal. The test pattern generation circuit 364 generates a test pattern based on the received data under the control of the control circuit 362 and supplies it to the scan chain 368. The output result analysis circuit 366 takes in and analyzes the data indicating the test result output from the scan chain 368 and outputs the test result to the control circuit 362.

  When testing the LSI 30, first, a signal for controlling the circuit blocks 34-1 to 4-4 is sent from the LSI test apparatus 10 to the TAP circuit 32 via the TDI terminal. The TAP circuit 32 generates a control signal corresponding to the circuit block 34 that performs the test operation based on the data fetched from the LSI test apparatus 10, and sends the control signal to the control circuit 362 of the circuit block 34 that performs the test. The control circuit 362 supplies clocks and data to the circuits in the circuit block 34 and controls the test pattern generation circuit 364 and the output result analysis circuit 366 to operate. In the circuit block 34 that does not execute the test, the clock is stopped, and the test pattern generation circuit 364 and the output result analysis circuit 366 are stopped. By stopping the operation of the test pattern generation circuit 364 and the output result analysis circuit 366, the leakage current is suppressed, and the influence of the simultaneous operation on the circuit block 34 that executes the test is suppressed.

  When the test using the predetermined test pattern is completed, the test result is temporarily stored in a dedicated register circuit provided in the control circuit 362 or the output result analysis circuit 366. After the test of the test patterns of all the circuit blocks 34 executed in parallel is completed, the control circuit 362 sends the temporarily stored test results to the TAP circuit 32. The TAP circuit 32 sends the test result serially from the TDO terminal to the LSI test apparatus 10.

  Here, in the present embodiment, the test pattern has a failure detection pattern and a simultaneous operation pattern. The failure detection pattern is a test pattern applied in a conventional LSI operation test, and is a pattern intended to detect a failure of a circuit in the LSI 30. The simultaneous operation pattern is a test pattern for confirming whether or not each circuit block 34-1 to 4-4 of the LSI 30 malfunctions due to the influence of the simultaneous operation. That is, the test pattern is generated so that as many circuits as possible operate simultaneously, and the simultaneous operation pattern creates a situation in which the influence of the simultaneous operation is likely to be given to other circuit blocks. By operating the plurality of circuit blocks 34 according to the simultaneous operation pattern, it is possible to confirm whether or not malfunction occurs due to the influence of the simultaneous operation. The shorter the simultaneous operation pattern, the shorter the test time.

  With reference to FIGS. 6 and 7, the operation of the LSI test system according to the present embodiment will be described.

  The LSI 30 is first tested using a simultaneous operation pattern. All the circuit blocks 34-1 to 3-4 are registered in the untested block group list as one block group. That is, all the circuit blocks 34-1 to 3-4 are operated simultaneously to test whether there is a malfunction due to the influence of the simultaneous operation (step S502).

  One of the untested block groups registered in the untested block group list is selected as the test block group (step S504). Immediately after the start, all circuit blocks 34-1 to 4-4 are only registered as one untested block group, and the untested block group including all circuit blocks 34-1 to 4-4 is selected as the test block group. .

  All circuit blocks included in the test block group are tested in parallel with the simultaneous operation pattern (step S506). Immediately after the start of the test, all the circuit blocks 34-1 to 3-4 in the LSI 30 operate simultaneously, and are most susceptible to the simultaneous operation. When the test of the simultaneous operation of all the circuit blocks included in the test block group is completed, the test result of each circuit block is serially output from the TDO terminal. The LSI test apparatus 10 determines pass / fail based on the test result.

  When there is a circuit block whose output result does not match the expected value, that is, when there is a circuit block that has caused a malfunction (NO in step S508), the LSI test apparatus 10 checks the number of blocks included in the test block group. . When only one circuit block is included in the test block group (step S510-YES), since only the circuit block is performing a test operation, the influence of the simultaneous operation cannot be reduced by dividing the circuit block. Therefore, the LSI test apparatus 10 determines that the circuit block is defective, and determines the LSI 30 to be tested as a FAIL determination (step S524).

  When a plurality of circuit blocks are included in the test block group (step S510-NO), the test block group is divided into a plurality of block groups (step S530).

  As shown in FIG. 7, when the circuit block included in the test block group includes a circuit block for PASS determination (step S532-NO), the block group is divided by passing the PASS determination circuit blocks together. Register to the list. Since the circuit block does not malfunction even if it is affected by the simultaneous operation in the simultaneous operation, the plurality of circuit blocks may be collectively set as a pass block group. The circuit blocks determined as FAIL are grouped into one untested block group and registered in the untested block group list (step S536). As compared with the block group before the test, the circuit block of the PASS determination is included as few as the separated circuit blocks, and the simultaneous operation test for the new untested block group is performed.

  When there is no circuit block for PASS determination in the test block group and all circuit blocks are FAIL determination (step S532-YES), the circuit block for FAIL determination is divided into a plurality of arbitrary block groups, and each is as an untested block group Register in the untested block group list (step S534). It is preferable to divide into two or three block groups so that as many circuit blocks as possible can be operated simultaneously.

  When the test block group is divided and registered in the untested block group list, as shown in FIG. 6, the process returns to step S504, and one of the block groups registered in the untested block group list is the test block. Selected as a group (step S504). A clock is supplied to the circuit blocks included in the test block group by an instruction input from the TDI terminal, and the test pattern generation circuit 364 and the output result analysis circuit 366 are made operable. In the circuit blocks not included in the selected test block group, the supply of the clock is stopped, and the test pattern generation circuit 364 and the output result analysis circuit 366 are stopped. The test is performed by running the simultaneous operation pattern in parallel for all the circuit blocks included in the test block group after eliminating the unnecessary simultaneous operation. In this way, when a FAIL determination circuit block is included in the test based on the simultaneous operation pattern, the circuit block group capable of simultaneous operation is extracted and the block group is subdivided.

  On the other hand, when the output results of all the circuit blocks included in the test block group match the expected value (step S508—YES), the LSI test apparatus 10 registers the test block group in the pass block group as a PASS determination. (Step S512). Thereafter, if there remains an untested block group registered in the untested block group list (step S514-YES), the test is performed on the untested block group from step S504, and the simultaneous operation pattern test is performed. In this way, the set of circuit blocks included in the LSI 30 is registered in the acceptable block group list while being subdivided.

  When there is no untested block group registered in the untested block group list, that is, when all the blocks included in the LSI 30 belong to one of the passed block groups and are registered in the passed block group list (step S514-). NO), the simultaneous operation pattern test is terminated, and the failure detection by the failure detection pattern is performed. That is, the circuit block group included in the acceptable block group is simultaneously tested by the failure detection pattern. Based on the passed block group list, the test is performed in time series for each passing block group, such that when the testing of one circuit block group is completed, the next circuit block group is tested (step S516). At this time, a clock is supplied to the circuit blocks included in the block group to be tested, and the test pattern generation circuit 364 and the output result analysis circuit 366 are in an operable state. In circuit blocks not included in the block group to be tested, the clock is stopped and the test pattern generation circuit 364 and the output result analysis circuit 366 are stopped. In such a state, the failure detection pattern is run in parallel for all circuit blocks included in the test block group, and the test is performed.

  If all circuit blocks included in the LSI 30 are determined to be PASS in the test based on the failure detection pattern (step S518—YES), the LSI test apparatus 10 determines PASS and sets the LSI 30 as a pass product (step S522). In the test using the failure detection pattern, if any one of the circuit blocks has malfunctioned (NO in step S518), FAIL is determined and the LSI 30 is determined as a defective product (step S524).

  As described above, the test flow of the present embodiment is roughly divided into a part for determining a combination of circuit blocks and a part for detecting a failure. In the part that determines the combination of circuit blocks, the simultaneous operation pattern is used to extract circuit blocks that are likely to malfunction due to the effect of simultaneous operation, and the optimum combination of circuit blocks that does not malfunction even if the simultaneous operation pattern is run in parallel A large number of block groups are determined (steps S502 to S514, S530). In the part that performs the failure detection, the failure detection pattern is serially run for the determined block group to detect the failure of the circuit in a state where the influence of the simultaneous operation is small (steps S516 to S524).

  In order to perform a failure detection test so as not to cause a malfunction due to simultaneous operation in a production lot with a large leakage current, it is necessary to allocate circuit blocks in the LSI 30 to an appropriate number of block groups. On the other hand, in a production lot with a small leakage current, a test should be performed without causing malfunction due to simultaneous operation even in a block group that includes more circuit blocks than the production lot with a large leakage current (the number of block groups decreases). Can do. In the present invention, the optimal number of block groups is determined so as not to cause malfunction of the circuit due to simultaneous operation in accordance with the leakage current of the LSI manufacturing lot, and the failure detection test is executed, so that the number of block groups is reduced. Can be suppressed. Therefore, an increase in test time can be suppressed.

  Here, the LSI on which Logic BIST is mounted has been described, but the present invention can also be applied to an LSI having a scan circuit as long as the clock supply can be controlled for each block from the LSI test apparatus.

  Also, the test time can be shortened by using only the failure detection pattern without using the simultaneous operation pattern. The test procedure will be described with reference to FIG.

  As shown in FIG. 8, first, a test is performed in parallel with a failure detection pattern for all circuit blocks included in the LSI 30 (step S602).

  As a result of the test, when all the circuit blocks are determined to be PASS, that is, when there is no circuit block that is determined to be FAIL (YES in step S604), no failed circuit is detected. Assuming that all circuit blocks are operating normally, the LSI test apparatus 10 makes a PASS determination with the LSI 30 as an acceptable product, and ends the test.

  As a result of the test, if there is a circuit block that is determined to be FAIL (step S604-NO), it is checked whether there is a circuit block that is determined to be PASS (step S612). When the circuit block that has been determined to be PASS and the circuit block that has been determined to be FAIL are mixed (YES in step S612), the circuit block that has been determined to be FAIL is tested in parallel with a failure detection pattern (step S624). That is, the LSI test apparatus 10 supplies a clock to the circuit block group that has been determined as FAIL via the TAP circuit 32, and puts the test pattern generation circuit 364 and the output result analysis circuit 366 into an operating state. The clocks of other circuit blocks (circuit blocks that have passed PASS determination) are stopped, and the test pattern generation circuit 364 and the output result analysis circuit 366 are stopped. In such a state, a test using a failure detection pattern is performed in parallel on the circuit block that has been determined as FAIL.

  When the test ends, the process returns to step S604, and a pass / fail determination is performed. By going through this loop, circuit blocks that have been determined to be PASS are extracted, and circuit blocks that have been determined to be FAIL are reduced.

  As a result of the test, when there is no circuit block that is determined to be PASS (step S612), the number of circuit blocks that are determined to be FAIL is checked (step S614). If there is one circuit block that has been determined to be FAIL (step S614: YES), the LSI test apparatus 10 has detected the failure as a defective product because the LSI 30 has detected a failure even when the influence of the simultaneous operation is suppressed. (Step S626).

  If there are a plurality of circuit blocks that are determined to be FAIL (step S614-NO), the circuit block that is determined to be FAIL is assigned to a plurality of block groups (step S618). The number of blocks included in each of the plurality of block groups is arbitrary. The LSI test apparatus 10 tests each block group in time series based on the failure detection pattern (step S620). At this time, the circuit blocks included in each block group are tested in parallel.

  If all the circuit blocks are determined to be PASS (step S622—YES), there is no circuit that has detected a failure. Therefore, the LSI test apparatus 10 determines PASS with the LSI 30 as an acceptable product (step S606), and performs the test. finish. If there is a circuit block that has been determined to be FAIL (step S622-NO), it means that a failure has been detected even when the influence of the simultaneous operation is suppressed, and the LSI test apparatus 10 performs a FAIL determination with the LIS 30 as a defective product ( Step S626), the test is terminated.

  In such a flow, since it is not necessary to apply the simultaneous operation pattern, the change from the conventional method is less and easier to apply than the flow shown in FIGS. However, since the test time based on the failure detection pattern is longer than the test time based on the simultaneous operation pattern, the test time tends to be longer.

  As described above, according to the present invention, the LSI can be tested so that the test time becomes as short as possible while suppressing malfunction caused by simultaneous operation.

The above embodiments can be implemented in combination as long as there is no contradiction.
Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 10 LSI test apparatus 11 Input part 12 Central processing part 13 Memory part 14 Display part 15 Auxiliary input part 16 Auxiliary memory part 20 Interface part 30 Test LSI
32 TAP circuit 34, 34-1-4 circuit block 110 control unit 120 test unit 130 determination unit 140 block selection unit 362 control circuit (CTRL)
364 Test pattern generation circuit (TPG)
366 Output result analysis circuit (ORA)
368 scan chain

Claims (15)

A test unit for testing in parallel a test block including one or more designated circuit blocks of a semiconductor integrated circuit including a plurality of circuit blocks that can be independently tested;
A determination unit that determines the quality of the operation of the circuit block based on a result of the test by the test unit;
When the test block includes a circuit block that is determined to be malfunctioning by the determination unit, a selection unit that distributes the test block to a plurality of block groups, and at least one block group of the plurality of block groups includes the operation Includes only circuit blocks determined to be defective,
An LSI test apparatus comprising: a control unit that instructs the test unit to retest a block group including only the circuit blocks determined to be malfunctioning. The selection unit includes a group of blocks including the circuit block determined to be defective in operation and the operation good when the test block includes a circuit block determined to be defective and a circuit block determined to be good in operation. The LSI test apparatus according to claim 1, wherein the LSI test apparatus is assigned to a block group including the determined circuit block. 3. The selection unit according to claim 1, wherein when the test block includes only a plurality of circuit blocks determined to be malfunctioning, the selection block distributes the circuit blocks determined to be malfunctioning to a predetermined number of block groups. LSI test equipment. The control unit performs the test until all the circuit blocks included in the semiconductor integrated circuit are determined to be good in operation, or until the test block includes only one circuit block determined to be defective in operation. The LSI test apparatus according to claim 2 or 3, wherein an instruction is given to repeat the block allocation and the retest. The LSI test apparatus according to claim 1, wherein the selection unit distributes all the circuit blocks included in the semiconductor integrated circuit to one test block for an initial test. The test unit is generated so that many circuits included in the circuit block operate simultaneously, and the test block is used for the test block by using a simultaneous operation pattern for confirming whether the circuit block malfunctions due to the influence of the simultaneous operation. The LSI test apparatus according to claim 5, wherein the included circuit blocks are tested in parallel to extract the circuit blocks that can be operated simultaneously. After all the circuit blocks included in the semiconductor integrated circuit are included in the circuit block determined to be in good operation, the operation is determined to be good using a failure detection pattern for detecting a failure in the circuit block. 7. The LSI test apparatus according to claim 5, wherein a block group including the circuit blocks is tested in time series. Testing in parallel a test block including one or more specified circuit blocks of a semiconductor integrated circuit comprising a plurality of independently testable circuit blocks;
Determining the quality of the operation of the circuit block based on the result of the test;
When the test block includes a circuit block determined to be malfunctioning, the step of allocating the test block to a plurality of block groups, and at least one block group of the plurality of block groups is determined to be malfunctioning Includes only circuit blocks,
Retesting a block group including only the circuit blocks determined to be defective as the test block. An LSI test method. The distributing step includes a group of blocks including the circuit blocks determined to be defective in operation, when the test block includes a circuit block determined to be defective in operation and a circuit block determined to be good in operation; The LSI testing method according to claim 8, further comprising a step of allocating to a block group including the determined circuit block. The distribution step includes a step of distributing the circuit blocks determined to be malfunctioning to a predetermined number of block groups when the test block includes only a plurality of circuit blocks determined to be malfunctioning. 9. The LSI test method according to 9. The retesting step is performed when all of the circuit blocks included in the semiconductor integrated circuit are determined to be in good operation, or when the test block includes only a circuit block determined to be 1 of the operation failure. The LSI test method according to claim 9, further comprising a step of terminating the test. The LSI testing method according to claim 8, wherein the distributing step distributes all the circuit blocks included in the semiconductor integrated circuit to one test block for an initial test. The step of testing and the step of retesting are generated so that many circuits included in the circuit block operate simultaneously, and a simultaneous operation pattern for confirming whether or not the circuit block malfunctions due to the influence of the simultaneous operation. The LSI testing method according to claim 12, further comprising: testing the circuit blocks included in the test block in parallel by using the method to extract the circuit blocks that can be operated simultaneously. After all the circuit blocks included in the semiconductor integrated circuit are included in the circuit block determined to be in good operation, the operation is determined to be good using a failure detection pattern for detecting a failure in the circuit block. 14. The LSI testing method according to claim 12, further comprising a step of testing a block group including the circuit blocks in a time series.   15. A program for causing a computer to execute the LSI test method according to claim 8.

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