JP2011035410A - Trench-gate power mosfet equipped with protecting diode - Google Patents

Abstract

To provide a trench gate type MOSFET that prevents breakdown at the bottom of a trench, avoids damage to the MOSFET, and has improved on-resistance characteristics.
The power MOSFET includes a trench gate that defines a plurality of MOSFET cells. A protective diffusion is preferably created in the inactive cell to form a diode connected in parallel to the channel region in each MOSFET. The protective diffusion prevents impact ionization and the resulting generation of carriers near the corner of the gate trench and prevents damage to the gate oxide layer. In addition, the diode is designed to have a breakdown voltage, which can limit the strength of the electric field across the gate oxide layer. By eliminating the deep central diffusion, the cell density can be increased and the on-resistance of the MOSFET can be improved.
[Selection] Figure 3

Description

  The present invention relates to power FETs, and in particular to MOSFETs whose gates are placed in trenches formed on the surface of silicon.

  This patent application is a US patent filed on Oct. 31, 1997, which is a continuation-in-part of U.S. Patent Application No. 08 / 459,555 filed on June 2, 1995 (patent attorney specification number M-3278). -4P). This patent application includes US patent application Ser. No. 08 / 884,826, filed Jun. 30, 1997 and 08 / 429,414, filed Apr. 26, 1995, and registered on Oct. 7, 1997. Related to 5,674,766. The entirety of each prior application is referred to and made a part of this application.

  The trench gate type MOSFET is one of the MOSFETs, and the gate is formed in a trench formed on the surface of silicon and extending inward. The gates are formed in a grid-like geometric pattern, which defines the individual cells of the MOSFET, and the pattern usually takes the form of a closed polygon (square, hexagon, etc.) or a series of It is in the shape of a striped or rectangular shape that penetrates each other. Current flows in a vertical channel formed adjacent to the sides of the trench. The trench is filled with a conductive gate material, typically doped polysilicon, and is insulated from the silicon by a dielectric layer usually made of silicon dioxide.

  Two important characteristics with respect to power MOSFETs are the breakdown voltage, ie, the voltage at which current begins to conduct during an off condition, and the on resistance, ie, the resistance that conducts current during an on condition. The on-resistance of a MOSFET generally changes in proportion to the cell density, and this means that as the number of cells per unit area increases, the total “gate width” (periphery of each cell) increases and the current passes through it. This is because it flows. The breakdown voltage of the MOSFET mainly depends on the doping concentration and the arrangement of the source, body and drain regions in each MOSFET cell.

  MOSFETs are generally formed in a lightly doped epitaxial layer of grown silicon on a heavily doped silicon substrate. The gate trench typically extends into the epitaxial layer, is often square, and has a flat bottom defined by corners. This shape creates the problem that when the MOSFET is turned off, the electric field reaches a maximum near the corner of the gate trench. This causes avalanche breakdown and impact ionization, resulting in the generation of carriers. When carriers are generated within the mean free path of the silicon / gate oxide boundary, the carriers have sufficiently high energy to pass through the boundary and may be injected into the gate oxide. Carriers that can overcome the silicon / silicon dioxide energy barrier are often referred to as “hot carriers”. Hot carrier injection can cause extreme damage to the gate oxide layer, causing changes in threshold voltage, transconductance or on-resistance, thereby damaging or destroying the MOSFET.

  U.S. Pat. No. 5,072,266 (Patent Document 1) discloses a technique for suppressing voltage breakdown in the vicinity of a gate by forming a deep central body diffusion portion extending under a bottom surface of a trench in a MOSFET cell. Disclose. This deep central diffusion creates an electric field so that breakdown occurs in the bulk silicon away from the gate and where hot carriers do not reach the gate oxide. A cross-sectional view of a MOSFET based on US Pat. No. 5,072,266 is shown in FIG. 1, showing a trench gate 11, an N + source region 12, an N + substrate (drain) 13, an N− epitaxial layer 14 and deep. A MOSFET cell 10 including a central P + diffusion 15 is shown. Note that the lowest part of the P + diffusion 15 is below the bottom surface of the gate 11.

  The doping of the deep P + diffusion is higher than the doping of the P-body 16 in the channel region indicated by the dashed line and denoted by reference numeral 17. As a result, the distance Ys between the gate trenches must be kept above a certain minimum value. Otherwise, deep P + dopant will diffuse into the channel 17 and increase the threshold voltage Vtn of the device. The value of Ys, together with the thickness of the gate, determines the cell density and serves to determine the on-resistance of the MOSFET.

The deeper P + diffusion limits the current spread in the N− epitaxial layer 14. 20 and 21 show simulations of current lines for a conventional MOSFET having a flat bottom P-body region and a MOSFET having a deep P + diffusion, respectively. The current line of FIG. 21 is limited to a divergence angle (analytical approximation used to describe the uniformity of the epitaxial current) of approximately 45-47 ° (measured with a 95% current line), resulting in Compared to the device described in FIG. 20, the N-epitaxial region is utilized suboptimally and has a higher specific on-resistance. The conventional device has a large current spread angle in the range of 73 to 78 °, and the formula x = (Y _CELL −Y _G ) 2 tan θ (where θ is the current spread angle, Y _CELL is the full width of the MOSFET cell, and Y _G is the gate) Achieves uniform conduction at a fairly shallow depth estimated by the distance between trenches). This relationship is shown in FIG. It has been found that the presence of a deep P + region increases the depth at which uniform conduction is achieved within the N-epitaxial region from 0.5 microns to 1.6 microns.

  To make extremely low voltage, low on-resistance power MOSFETs, device dimensions are generally reduced. Specifically, the cell density is increased and the epitaxial layer is thinned until the gate trench is where it extends into the heavily doped substrate. Such a MOSFET is shown as MOSFET 20 in FIG. 2A.

  This creates a whole new set of design criteria. Referring to FIG. 2A, the corner 21C of the gate trench 21 is surrounded by the N + substrate 13, so that the electric field at this location drops completely between the gate oxide layers. Although hot carrier formation in the silicon is reduced, the high electric field on the gate oxide layer still degrades or damages the device. Under one condition, when the gate is biased to approximately the same potential as the source and body (ie when the device is turned off), a significant concern is that the gate oxide layer at the bottom of the trench spans between the devices. It means that you have to withstand the voltage. This is because there is no epitaxial layer for absorbing a part of this potential difference as compared with the embodiment of FIG.

An equivalent circuit for MOSFET 20 is shown in FIG. 2B. Diode D _DB represents the PN junction between N-epitaxial layer 14 and P-body region 22, and capacitor C _GD represents the capacitor between gate oxide layers 21A.

US Pat. No. 5,072,266

  An object of the present invention is to provide a trench gate type MOSFET that prevents breakdown at the bottom of the trench, avoids damage to the MOSFET, and has improved on-resistance characteristics.

  The trench gate type MOSFET of the present invention is formed in a semiconductor chip consisting of a substrate alone or a substrate on which an upper epitaxial layer is deposited. The gate of the MOSFET is formed in a trench that extends downward from the surface of the chip. The MOSFET includes a source region of a first conductivity type, a body region of a second conductivity type, and a drain region of the first conductivity type, which are vertically arranged along the sidewall of the trench. The gate trench may extend into the epitaxial layer and may pass through the epitaxial layer into the substrate.

  The MOSFET is formed as a plurality of cells defined by the gate trench. The cell can be of any shape. For example, the cells can be square or hexagonal, or a series of parallel stripes or rectangles. In accordance with the present invention, a second conductivity type protective diffusion is created in the chip, which forms the first conductivity type PN junction in the epitaxial layer or substrate. This PN junction functions as a diode. The metal layer couples the protective diffusion (ie, the diode terminal) to the source region of the MOSFET cell so that the diode is connected in parallel to the channel of the MOSFET cell.

  In one preferred embodiment, the protective diffusion is formed in certain cells in a selected pattern across the MOSFET.

  The protective diffusion of the second conductivity type operates to reduce the strength of the electric field between the gate oxides and at the corners of the trench and limit hot carrier formation near the trench. In certain embodiments, the trench extends into the epitaxial layer. Avalanche breakdown can be induced by many mechanisms (reachthrough, radius of curvature, etc.) as long as the avalanche region is spatially separated from the gate trench. The diode also acts as a voltage clamp, thereby limiting the voltage across the gate oxide layer. In certain embodiments, the trench extends into the substrate and the gate oxide must withstand the full voltage drop across the MOSFET.

  In one preferred embodiment, one cell containing a protective diffusion (“diode cell”) repeats a pattern across the MOSFET for a selected number of active MOSFET cells (“active cells”). Provided. The number of diode cells per active cell is determined by MOSFET design criteria. In general, for example, MOSFET cells that are expected to suffer more breakdown require a higher percentage of diode cells.

  Also, due to the presence of the diode cell, a large portion of the drain-body diode current flows when the MOSFET operates using body diode forward conduction. Such an operation (referred to as the third quadrant operation of an N-channel device) usually occurs when the inductor or motor is driven by push-pull, ie, a pair of bridged MOSFETs. The high diode current in the active cell results in charge storage, which degrades diode turn-off (forced diode reverse recovery), and when a high reverse voltage is applied again between the devices, parasitic source − May cause snapback of the body-drain active cell NPN bipolar transistor.

  As described above, by forming the diode cell according to the present invention, it is possible to provide a trench gate type MOSFET that prevents breakdown at the bottom of the trench, avoids damage to the MOSFET, and has improved on-resistance characteristics. .

FIG. 6 is a cross-sectional view of a conventional trench gate type MOSFET having a deep central diffusion for reducing the electric field at the corners of the trench. FIG. 2 is a cross-sectional view of a conventional trench gate type MOSFET including A and B, A having no deep central diffusion portion and a trench extending in the substrate, and B is an equivalent circuit diagram for the MOSFET of A. 1 is a cross-sectional view of a first embodiment of the present invention having a protective diffusion in an adjacent MOSFET cell. A is a cross-sectional view of a second embodiment of the present invention comprising A and B, A having a protective diffusion in an adjacent MOSFET cell, and a trench extending into the substrate, and B is equivalent to A MOSFET It is a circuit diagram. It is a top view of the conventional MOSFET cell. 1 is a plan view of a square cell MOSFET according to the present invention. FIG. FIG. 7 is a detailed plan view of the square cell MOSFET of FIG. 6. It is a top view of the stripe MOSFET by this invention. It is another sectional drawing of the 2nd Example by this invention. It is sectional drawing of the 3rd Example by this invention. It is sectional drawing of the 4th Example by this invention. It is sectional drawing of the 5th Example by this invention. It is sectional drawing of the 6th Example which has a wide protection cell. It is a top view of the 6th example shown in FIG. It is a figure which shows each process of the process of manufacturing MOSFET shown by FIG. It is a figure which shows each process of the process of manufacturing MOSFET shown by FIG. It is a figure which shows each process of the process of manufacturing MOSFET shown by FIG. It is a figure which shows each process of the process of manufacturing MOSFET shown by FIG. It is a figure which shows each process of the process of manufacturing MOSFET shown by FIG. FIG. 6 shows a simulation of current lines in a MOSFET having a flat bottom body region and a MOSFET having a deep central body diffusion, as disclosed in US Pat. No. 5,072,266. FIG. 6 shows a simulation of current lines in a MOSFET having a flat bottom body region and a MOSFET having a deep central body diffusion, as disclosed in US Pat. No. 5,072,266. FIG. 5 is a MOSFET showing the geometric relationship between current spreading angle and depth in the epitaxial layer, where uniform conduction is achieved. 6 is a graph showing specific on-resistance as a function of cell density for MOSFETs having deep central diffusions and MOSFETs having distributed diode cells. It is a graph showing the variation of the specific on-resistance as a function of gate bias for MOSFET, each having a cell density of 12Mcells / in ² and 32Mcells / in ^2. FIG. 6 shows a simulation of the current line in a MOSFET having MOSFET cells operating in a linear region during normal conduction and undergoing avalanche breakdown. FIG. 5 shows a simulation of the current line in a MOSFET having a diode cell operating in a linear region during normal conduction and undergoing avalanche breakdown. 6 is a graph showing unclamped inductive switching current and drain voltage in a MOSFET. It is a figure which shows the measured IV characteristic and breakdown characteristic of MOSFET. FIG. 5 shows the on-resistance of various components of a packaged MOSFET as a function of gate bias. FIG. 6 is a simulation showing the location of avalanche breakdown in a flat bottom MOSFET with a relatively thick gate oxide layer. FIG. FIG. 6 is a simulation showing the location of avalanche breakdown in a flat bottom MOSFET with a relatively thin gate oxide layer. FIG. FIG. 6 is a graph showing breakdown voltage as a function of normalized gate oxide thickness for a MOSFET having a deep central body diffusion. The MOSFET has a flat bottom body region and has distributed diode cells according to the present invention. It is a graph which shows the IV characteristic of MOSFET. Graph showing specific on-resistance as a function of gate bias for thin (12-V gate rating) and thick (20-V gate rating) oxide MOSFETs with cell densities of 12 Mcells / in ² and 32 Mcells / in ² It is. 1 is a cross-sectional view of a “reach through” type MOSFET structure including MOSFET cells and diode cells. FIG. FIG. 6 is a graph showing breakdown voltage as a function of epitaxial layer thickness in a 20-V drain, 12-V gate N-channel MOSFET using a “reach through” approach. FIG. 6 is a graph showing breakdown voltage as a function of epitaxial layer thickness in a 30-V drain, 20-V gate N-channel MOSFET using a “reach through” approach. FIG. 4 is a cross-sectional view of a “step epi” type MOSFET structure including a MOSFET cell and a diode cell. FIG. 6 is a graph showing breakdown voltage as a function of lower epi sublayer dopant concentration in a 20-V drain, 12-V gate N-channel MOSFET using a “stepped epi” approach. Figure 7 is a graph showing breakdown voltage in a diode cell (horizontal axis) as a function of lower epi sublayer resistivity and dopant concentration. Figure 7 is a graph showing various data for a 30-V drain, 20-V gate N-channel MOSFET using a "step epi" approach. Figure 7 is a graph showing various data for a 30-V drain, 20-V gate N-channel MOSFET using a "step epi" approach. Figure 7 is a graph showing various data for a 30-V drain, 20-V gate N-channel MOSFET using a "step epi" approach. FIG. 6 is a graph showing various data for a 30-V drain, 20-V gate P-channel device using a “reach through” approach. FIG. 6 is a graph showing the breakdown voltage of a diode cell and the breakdown voltage for the diode and MOSFET as a function of epi concentration for different implant doses and drive-in times for diode diffusion. FIG. 6 is a graph showing the breakdown voltage of a diode cell and the breakdown voltage for the diode and MOSFET as a function of epi concentration for different implant doses and drive-in times for diode diffusion. FIG. 5 is a graph showing breakdown voltage for N-type diode diffusion as a function of P-epi layer thickness for six different implantation doses. FIG. FIG. 6 is a graph showing breakdown voltage for N-type diode diffusion as a function of implantation dose for seven different P-epi layer thicknesses.

  A first embodiment of the present invention is shown in FIG. The trench gate type MOSFET 30 is formed in the epitaxial layer 14 grown on the upper surface of the N + substrate 13. The gate 31 is formed in the trench 32 and is separated from the semiconductor material by the oxide layer 31A. The cell 35 of the MOSFET 30 also includes a P− body region 33, a shallow P + contact region 33 </ b> A, and an N + source region 34. The metal layer 36 contacts the P− body region 33 and the N + source region 34 and short-circuits between them.

  The N + substrate 13 functions as a drain of the MOSFET 30 and is in contact with the bottom surface thereof. Alternatively, a buried N + layer can be used as the drain instead of the N + substrate, and the drain can be contacted from the top side of the structure, for example using an N + sinker region and an upper contact.

  In the adjacent cell 37, a protective deep P + diffusion portion 38 is formed. The diffusion portion 38 forms a PN junction portion 39 together with the N-epitaxial layer 14. The metal layer 36 is in contact with the protective diffusion 38 so that the PN junction 39 represents a diode connected in parallel with the channel of the cell 35.

  The protective diffusion 38 limits the strength of the electric field and consequently the carrier formation that occurs near the corners of the trench 32, thereby eliminating the need for a deep central diffusion in the MOSFET cell 35. Without the deep P + center diffusion, the size of MOSFET cell 35 is substantially reduced and the cell density of MOSFET 30 is significantly increased. For example, the width of each side of the N + source region 34 is reduced to about 1.0 μm, and the width of the contact between the metal layer 36 and the P + contact region for the P− body 33 is reduced to about 1.0 μm, so that the trench The total width between 31 can be approximately 3.5 μm. Actually, the total width between the trenches 31 is set to 5.0 μm. This is in contrast to a minimum width of about 8.0 μm for a MOSFET cell that includes a deep central diffusion (see FIG. 1).

  FIG. 4A shows a MOSFET 40 that includes a MOSFET cell 41 similar to the cell shown in FIG. 2A. That is, the trench 43 extends through the N− epitaxial layer 14 into the N + substrate 13, and the cell 41 does not include a deep central P + diffusion. In the adjacent cell 42, the protective P + diffusion portion 44 is formed, and the lower joint portion of the diffusion portion 44 reaches the upper surface of the N + substrate 13.

FIG. 4B shows an equivalent circuit diagram for the MOSFET 40. Since the corners of the trench 43 are located in the N + substrate 13 and the heavily doped N + substrate 13 cannot withstand a strong electric field, the problem of the electric field at the corners of the trench is almost negligible. Instead, the strength of the electric field between the gate 45 and the N + substrate 13, that is, the strength of the electric field applied between the gate oxide layers 45A becomes a significant factor. This position is represented by the capacitor _{CGD in} FIG. 4B. PN junction between the P- body region 22 and N- epitaxial layer 14 is represented by a diode _{D DB,} P + PN junction between the diffusion portion 44 and the N + substrate 13 by the diode _{D P + / N +} Represented. As shown here, both of the diode D _DB and the diode D _{P + / N +} are connected in parallel with the channel of the MOSFET cell 41.

  FIG. 5 shows a plan view of the conventional MOSFET 10 shown in FIG. A protective deep P + region 15 is shown in the center of each square cell and is surrounded by an N + source region 12 and a gate 11. In FIG. 5, four complete cells are shown.

  FIG. 6 is a plan view of the MOSFET 30 shown in FIG. The plan view of MOSFET 40 shown in FIG. 4A will be shown as well. Since the protection P + region at the center of each cell is deleted, the cell dimensions are reduced. Also shown is a cell (often referred to as a “diode cell”) that includes a P + diffusion. In FIG. 6, there is one diode cell for every eight active MOSFET cells (9 cells in total).

  FIG. 7 shows a detailed plan view of the three cells shown in FIG. 6 (two active MOSFET cells and one diode cell). In FIG. 7, Ys represents the cross-sectional width of the trench (not to be confused with the gate width W). Assuming that there is one diode cell for every n cells, the following equation gives the total area of n cells.

(Equation 1)
^{_{A = (Y G + Y S}} ) 2 + (n-1) (Y G + Y S) 2 = n (Y G + Y S) 2

  Since n-1 of these cells is an active MOSFET cell, the total gate width W in the n cells is equal to:

(Equation 2)
W = 4Y _S (n−1)

  Accordingly, the area to width ratio A / W (a goodness index indicating how efficiently the gate width W is accommodated within the area A) is equal to:

(Equation 3)
A / W = (Y _G + Y _S ) ²

  Thus, the ratio A / W to the MOSFET including the diode cell is increased by a factor n (n-1) as compared with the conventional MOSFET having no diode cell. This “penalty” factor stems from the fact that the diode cell does not conduct current and approaches 1 as n increases. The loss is offset by an increase in the total gate width (and hence current capacity) obtained by increasing the cell density of the device. In general, n is determined by the frequency with which the MOSFET is expected to break down. Devices that are expected to break down more frequently will generally require lower n values, i.e., more diode cells than the total number of cells. In the extreme case where there is only one other inactive cell (ie, a diode cell), N = 2 and n / n-1 = 2, and the efficiency gain of this structure is Limited by minutes. On the other hand, for example, if only one of all 21 cells is a diode cell, n = 21 and n / n-1 = 21/20, indicating that there is virtually no loss due to that diode.

As noted above, the presence of a deep P + region as disclosed by US Pat. No. 5,072,266 limits the current spread in the epitaxial region, thereby increasing the on-resistance. FIG. 23 is a graph showing specific on-resistance (R _DS A) as a function of cell density in a MOSFET with a deep P + diffusion (curve 170) and a MOSFET with distributed diode cells (curve 172). As shown therein, the intrinsic on-resistance of a MOSFET having a deep P + diffusion reaches a certain minimum value, but then the current is concentrated and the threshold voltage is increased by the P + body dopant entering the channel. The result increases. In MOSFETs with distributed diode cells, current spreading is improved, and the improvement becomes more significant with increasing cell density, thus achieving a significant improvement in on-resistance. In the graph of FIG. 23, the on-resistance of the active flat bottom cell improves 31% to 35 mΩ-cm ² as a result of simply increasing the divergence angle (see 12 Mcells / in ² in FIG. 23). Further increasing the cell density to 32 Mcells / in ² achieves an improvement of 28%, mainly as a result of improved channel resistance from a lower A / W factor. The net effect is an approximate 51% reduction in die resistance for the 30-VN channel trench gate MOSFET compared to the previous one at 12 Mcells / in ² when multiplied by these improvements. FIG. 24 shows the change in intrinsic R _DS A as a function of gate bias for the two devices. For devices with a 20-V gate rating, the threshold voltage was held at 2.9 V to be consistent with the rated operation at 10- and 4.5-V gate bias.

  The avalanche capability of the 1-of-N clamp MOSFET was analyzed using unclamped inductive switching (UIS) simulation. The device had one diode cell for every 16 active MOSFET cells. FIG. 25 shows the current line of the device operating in the linear region during normal conduction before switching, and FIG. 26 shows the current line after the device has been inductively switched. As shown there, avalanche breakdown occurs in the diode cell and induces all current, and no impact ionization, pre-avalanche or high gate oxide field was measured in the active MOSFET cell in the “off” state. .

The test was performed using an SO-8 size MOSFET operating at a 10-A rating using an unclamped inductive switching (UIS) tester (AOT ILT-200 Inductive Load Tester). FIG. 27 shows that the measured UIS current exceeded 7 times the rated operating current of the MOSFET and the current density reached 950 A / cm ² or higher. An increase in avalanche breakdown voltage was observed during the UIS from 36V nominal breakdown (see FIG. 28) to 46V without any MOSFET damage.

When using 32 Mcells / in ² technology, a 0.574 cm × 0.427 cm MOSFET sized for a D ² PAK type package was designed, fabricated and assembled. This device using 1,075,620 active MOSFET cells was the first power MOSFET to achieve ULSI class fabrication technology (> 1 million transistors). As shown in FIG. 28, the measured die showed a saturation current in excess of 140 A with a gate bias of 4.0 V, as well as a drain current at 5 V that remained linear beyond 300 A (tester limit). . The gate charge was measured at 195 nC with Vgs = 10 V, and the corresponding packaged overall on-resistance was 3.1 mΩ, as shown in FIG. After subtracting the measured package resistance of 1.1 mΩ, the resulting die resistance of less than 2.0 mΩ is the lowest value reported to date to our knowledge. However, simulation and measurement of on-resistance in smaller dies (see circle in FIG. 29) suggests that spreading resistance in the top metal of the MOSFET can cause resistance additions on the order of 0.5 mΩ. . Thus, packaging generally accounts for 33% of the total resistance of the product being packaged. With a specific on-resistance of only 0.25 mΩcm ² , the 32 Mcells / in ² MOSFET has the lowest specific on-resistance to our knowledge of any 30-V power MOSFET ever fabricated, It is not affected by the UIS, reliability, and area scaling limitations of similar devices.

  A special problem appears when scaling a 1-of-n design when operating at low gate bias. For a MOSFET having a rated gate oxide breakdown voltage of 20 V or higher when the gate oxide is thick (defined here as having a normalized gate oxide thickness η = 100%, ie 1) The effect of the trench gate on the PN junction field is minimal. As shown in FIG. 30, the P-channel without voltage clamping from a deep P + diffusion as disclosed in the above referenced Bulucea patent or from a distributed diode as disclosed herein The MEDICI simulation of the device shows the avalanche breakdown that occurs at the PN junction. However, to optimize the MOSFET during low voltage operation, the gate oxide layer is scaled down (ie thinned) to achieve a low threshold voltage (no channel punch-through) and high channel transconductance. There must be. In the case of thin gate oxide, for example η = 35% as shown in FIG. 31, field plate induced (FPI) avalanche breakdown occurs at a location adjacent to the gate electrode that does not coincide with the PN junction, This lowers the breakdown voltage of the device and exposes the gate oxide to the risk of hot carrier generation. In the case of a MOSFET having a deep diffusion according to the above-referenced Bulucea patent, the diode clamp cell is FPI (see FIG. 32) as a result of the gate being electrostatically shielded by the depletion region associated with the deep diffusion. Low sensitivity. In order to protect a MOSFET having a flat bottom body region, the breakdown voltage of the 1-of-N diode is set substantially lower than the voltage at which FPI breakdown occurs (see FIG. 32). By overcoming the FPI problem, the higher cell density can be fully utilized to improve the utilization of the epitaxial region and reduce the channel resistance (which suppresses the total on-resistance at low gate bias).

P-channel MOSFETs were fabricated according to the 1-of-N principle described herein. The drain of the MOSFET was designed for 20V operation by known techniques. The cell density was set to 32 Mcells / in ² , the gate oxide was thinned to η = 60%, and the threshold voltage was set to 1.3V. A die for a 10-A rated SO-8 size package that induces 50A or more with a gate bias of only 2.5V was used. FIG. 33 shows the IV characteristics of the device. As shown in FIG. 34, specific on resistance measured is 850μΩ-cm ² at a gate bias of 2.5V, it was 750μΩ-cm ² at a gate bias of 2.7V. To our knowledge, this is the lowest reported on-resistance for P-channel MOSFETs at low gate bias (<3V) operation. The on-resistance measured with a gate bias of 4.5V was only 526 μΩ-cm ² . The on-resistance of the SO-8 package is 11 mΩ, to the best of our knowledge, the lowest on-resistance reported so far for P-channel devices with a gate bias of 4.5V.

  In conclusion, having a regular distribution of inactive deep P + cells in a vertical trench FET provides a voltage clamping mechanism that limits the carrier generation rate and electric field at or near the corners of the trench gate. In the presence of electrical overload, device reliability and survivability are thereby improved without limiting on-resistance or cell density. The deep P + region need not extend to the end of the trench and can be made smaller than the cell configuration if desired. If the trench overlaps the N + substrate, the deep P + region need not extend below the trench, in which case a PIN diode may be formed between the deep P + region and the N + substrate (see FIG. 11). ). A graph showing the breakdown voltage of a PIN diode (such as diode D2 in FIG. 11) as a function of the doping concentration and width of the intermediate, or “inherent” region is M.M. Sze “Physics of Semiconductor Devices” 2nd edition (John Wiley & Sons, 1981, p. 105, FIG. 32), which is incorporated by reference.

Using the "one-of-n" technology of the present invention, the size of the MOSFET cell is significantly reduced, thereby reducing ¹² to 32 Mcells / in ² (5 cells) without sacrificing area and body contact quality. / Cm ² ), the cell density can be increased. The parameter “n” can vary from 2 (every other cell) to a large number such as 64 or more. Thus, the ability of the MOSFET to withstand avalanche breakdown can be controlled by design, albeit with a loss in on-resistance compared to a completely flat bottom cell represented by the factor n / n-1. In many instances, this loss factor can be adjusted within a few percent of an ideal flat bottom device.

  FIG. 8 shows a plan view of another MOSFET cell in which the cells are striped. In the MOSFET 80, the cells 81, 82, 83 and 84 are active MOSFET cells, and the cell 85 is a diode cell including a protective P + diffusion. Each cell 81-84 includes a P + contact region 87 and an N + source region 88. Two contact holes 89 are shown in FIG. 8 and contact the metal layer (not shown) with the P + region 87 and N + source region 88 of the MOSFET cells 81-84 and the P + region 86 of the diode cell 85. Used to provide a part. The contact holes 89 can be arranged in various patterns across the cells 81-85. A contact hole 90 for contacting the gate 91 is also shown.

Another use of the P + diode cell is to clamp the drain voltage to protect the gate oxide layer from overload due to excessive electric field between the gate and the N + substrate. This situation is particularly caused in embodiments where the trench extends into the substrate and therefore the gate oxide layer at the bottom of the trench is exposed to the entire potential difference between the gate and the substrate. Silicon dioxide can withstand a voltage equal to about 8 MV / cm. With a safety factor of 50%, X _OX · 4 MV / cm (where X _OX is the gate oxide thickness in cm) is generally considered as the maximum voltage applied between the gate oxide layers during manufacture. Therefore, the breakdown voltage of the diode formed by the protective P + diffusion should not exceed X _OX · 4 MV / cm. For example, when using an oxide layer having a thickness of 400 Angstroms, the oxide layer is destroyed at about 32V, but the maximum voltage should be limited to 16V for reliable operation.

  Figures 9-11 show cross-sectional views of several alternative embodiments according to the present invention. FIG. 9 shows a MOSFET 92 in which a trench extends into the N + substrate. A thin layer of the N− epitaxial layer remains in the MOSFET cell 93, but in the diode cell 94, the protective P + diffusion reaches the upper surface of the N + substrate 13. In the MOSFET 100 shown in FIG. 10, the P− body region in the MOSFET cell 101 extends to the upper surface of the N + substrate 13, and the N− doped region of the epitaxial layer is not left. In the MOSFET 110 shown in FIG. 11, a thin portion of the epitaxial layer 14, doped P− or N− is left in each of the MOSFET cell 111 and the MOSFET cell 112.

9-11, diode D1 represents the PN junction in the MOSFET cell, diode D2 represents the PN junction in the protective diode cell, and capacitor C1 is the gate oxide layer abutting the gate and N + substrate. Represents. In all three cases, the relationship BV _D2 <50% · BV _C1 must be maintained. However, BV _D2 is the breakdown voltage of the diode D2, and BV _C1 is the breakdown voltage of the capacitor C1. Further, the breakdown voltage of the diode D2 is smaller than the breakdown voltage of the diode D1 in each case.

  MOSFET 120 is shown in FIG. 12 and is represented in the same manner as the conventional MOSFET shown in FIG. 2A. Diode D1 represents a PIN diode formed in the center of each MOSFET cell by a combination of a shallow P + contact region, a P-body and an N + substrate. In the MOSFET 120, the breakdown voltage of the PIN diode D1 is set to be lower than 50% of the breakdown voltage of the capacitor C1, and the breakdown voltage of the capacitor represents the thickness of the gate oxide layer expressed in cm. Calculated based on 8 MV / cm. As a result, in MOSFET 120, if breakdown occurs, it will occur in the central region of the individual cell and at a voltage that does not damage the gate oxide.

  Yet another embodiment is shown in FIGS. 13 and 14, which is a cross-sectional view taken along the line XIIIA-XIIIA shown in the plan view of FIG. The MOSFET 130 includes a cell 121 and a wide cell 131 including a deep P + region 132. The deep P + region 132 functions as a protection against the gate oxide layer of the cell 121, while it functions as an active MOSFET cell and has an N + source region 133. Thus, although the cell 131 reduces the total cell density of the MOSFET, there is less loss associated with on-resistance than when the cell 131 performs only a protection function and does not pass current. As with the MOSFET 120 of FIG. 12, the cell 121 is generally smaller than when each cell contains a protective deep P + region.

  While there are many ways to fabricate a MOSFET according to the present invention, FIGS. 15-19 illustrate a typical method for fabricating the MOSFET 30 shown in FIG.

  In FIG. 15, the starting point is a conventional N + substrate 13 with an N-epitaxial layer 14 grown on the top surface using a known method.

A thick oxide layer 140 is grown, masked and etched, and a thin oxide layer 141 is grown on top of the substrate where the deep P + region 38 is to be formed. Thereafter, a deep P + region 38 is implanted through the thin oxide layer 141 at a dose of 1 × 10 ¹⁴ to 7 × 10 ¹⁵ cm ⁻² and an energy of 60-100 keV. The resulting structure is shown in FIG. The oxide layers 140 and 141 are removed.

In one variation of the method, a thick oxide layer 142 is grown and then removed by photomasking except on the deep P + region 38, and a thin oxide layer 143 is grown. The thin oxide layer 143 is masked and removed from the portion of the structure where the trench is to be formed, as shown in FIG. The trench is masked and etched using known techniques such as reactive ion etching or plasma dry etching. The trench is oxidized to form a gate oxide layer 31A and polysilicon is deposited in the trench until it overflows from the top surface of the trench. The polysilicon is then doped with phosphorus by POCl ₃ pre-deposition or ion implantation at a dose of 5 × 10 ¹³ to 5 × 10 ¹⁵ cm ⁻² and an energy of 60 keV to give a sheet resistance of 20-70 Ω / □. For P-channel devices, the polysilicon is doped with boron using ion implantation to a sheet resistance of approximately 40-120 Ω / □. The polysilicon is then etched until the trench surface returns to a flat surface, except where the mask protects, so that it can generally contact the metal layer.

A P-body 33 is then implanted through the thin oxide layer 143 (eg, boron is implanted with a dose of 1 × 10 ¹³ to 4 × 10 ¹⁴ cm ⁻² and an energy of 40-100 keV). A similar method is used in fabricating P-channel devices, except that the dopant is phosphorus. The resulting structure is shown in FIG.

The N + source region is then masked and arsenic ion implantation (or boron implantation for P-channel devices) with a dose of 5 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² and energy of 20-100 keV. The resulting structure is shown in FIG.

Subsequent to the formation of the N + source region 38, a new mask is formed and the shallow P + region 33A used to contact the P− body has a dose of 1 × 10 ¹³ to 5 × 10 ¹⁴ cm ⁻² and 20−. It is introduced by ion implantation with an energy of 80 keV. Alternatively, as shown in FIG. 19, the shallow P + region 33A is implanted with a P-type dopant through the same mask used in forming contact holes for the N + source region / P + contact region and the deep P + region. It is formed by doing. Using this technique, several P-type dopants are implanted into the N + source region 34, but the level of the P-type dopant is not high enough to concentrate the N-type ions in the N + source region. .

  A thin oxide layer is thermally grown. BPSG is then deposited on the surface of the substrate. The BPSG flows instantaneously from approximately 850 ° C. to 950 ° C. in order to flow smoothly and to flatten the die surface shape. Contact holes are etched in the oxide and BPSG layers and a metal layer 36 is deposited to form contact between the source and body regions and the deep P + region through the contact holes. Thereby, MOSFET 30 shown in FIG. 3 is generated.

  The die is then passivated using SiN or BPSG and the pad mask window is etched to facilitate bonding.

  A series of simulations and experiments were performed to determine the range of parameters that produced various commercially available products. They are 20-V and 30-V rated drain potentials, 12-V and 20-V rated gate potentials, and N-channel and P-channel devices. It was desired to specify the range of parameters that make the device that the “1-of-N” diode cell would break down before the MOSFET cell. Two approaches were used. One (i) a “reach-through” approach involving the use of a PIN-type diode with a breakdown voltage determined primarily by the thickness of the intermediate layer, and (ii) includes two sub-layers A “step epi” approach where the epitaxial layer is used with a deep diffusion in the diode cell that overlays the underside of the sublayer.

  The first set of tests dealt with a “reach-through” structure of the type shown in FIG. 35, including MOSFET cell 270 and diode cell 272. The diode cell includes a deep P + diffusion 274 extending 3 μm below the surface of the epitaxial layer. FIG. 35 shows an N-channel device. P-channel devices have the same overall structure, but will have opposite conductivity types

  The results of the test are shown in FIG. 36, where the vertical axis is the breakdown voltage, the horizontal axis is in the range of 2 to 6 μm and is the “flat” portion (Xepi (flat)) of the epitaxial layer, ie N The portion that is relatively constant in the concentration of the N-type dopant before it begins to increase in the transition region between the epitaxial layer and the N + substrate. This transition area is indicated by the hatched area 276 in FIG.

FIG. 36 shows test data associated with 20-V drain, 12-V gate, and N-channel devices. The first set of curves 280, 282 and 284 show that the N-epitaxial layer has dopant concentrations of 1.0 × 10 ¹⁶ cm ⁻³ , 2.0 × 10 ¹⁶ cm ⁻³ and 3.0 × 10 ¹⁶ cm ^{−, respectively. 3} shows the breakdown voltage of the device when ³ . The thickness of the gate oxide layer is 300 Å and the target drain rating is 20V. When Xepi (flat) is less than 3 μm thick, breakdown occurs in diode cell 272 and increases with Xepi (flat)). When Xepi (flat) is thicker than approximately 4 μm thick, breakdown occurs in MOSFET 270 and therefore the breakdown voltage is independent of Xepi (flat).

Curves 286 and 288 in FIG. 36 show the breakdown voltage between MOSFET cell 270 and diode cell 272 at N-epitaxial concentrations of 2.0 × 10 ¹⁶ cm ⁻³ and 3.0 × 10 ¹⁶ cm ⁻³ , respectively. Show the difference between. Assuming that the breakdown voltage difference between the MOSFET cell and the diode cell can be tolerated to approximately 5V, an N-epi concentration of 2.0 × 10 ¹⁶ cm ⁻³ and an Xepi (flat) of 3 μm are satisfactory. Will bring a device. In other situations, other devices having parameters within the range shown in FIG. 36 will yield satisfactory results.

FIG. 37 shows a similar set of curves for a “reach-through” 30-V drain, 20-V gate and N-channel device with a gate oxide layer thickness of 500 Å. Curves 290, 292 and 294 show the device when the concentration of N-epi is 5.0 × 10 ¹⁵ cm ⁻³ , 1.0 × 10 ¹⁶ cm ⁻³ and 2.0 × 10 ¹⁶ cm ⁻³ , respectively. Indicates breakdown voltage. Curves 296, 298, and 299 indicate MOSFET cells when the N-epitaxial concentrations are 5.0 × 10 ¹⁵ cm ⁻³ , 1.0 × 10 ¹⁶ cm ⁻³ , and 2.0 × 10 ¹⁶ cm ⁻³ , respectively. The difference between the breakdown voltage of 270 and the diode cell 272 is shown.

  The curves in FIGS. 36 and 37 were created by simulation. Data points (squares, triangles, diamonds, etc.) represent actual experimental results.

FIG. 39 shows the experimental results obtained from the device shown in FIG. 38, which is a sub-layer N-epi1 that includes “stepped” N-epi layers, ie, has different concentrations of N-type dopants. And N-epi2, which are described in US Pat. No. 5,674,766, filed Oct. 7, 1997. This is a “step epi device” with a 20-V drain and a 12-V gate. The upper sublayer N-epi2 is 3.5 microns thick (Xepi2), but in other embodiments N-epi2 is in the range of 2 μm to 5 μm. The trench and P-body region in MOSFET cell 300 extends only into upper sublayer N-epi2, but the deep P + diffusion in diode cell 302 passes through N-epi2 and into lower sublayer N-epi1. Extend. For P-channel devices, the conductivity type will be reversed. In FIG. 39, the horizontal axis represents the dopant concentration of the lower sublayer N-epi1 and varies from 1.0 × 10 ¹⁶ cm ⁻³ to 1.0 × 10 ¹⁸ cm ⁻³ . Curves 310, 312 and 314 are when the upper sublayer N-epi2 has dopant concentrations of 5.0 × 10 ¹⁵ cm ⁻³ , 1.0 × 10 ¹⁶ cm ⁻³ and 1.5 × 10 ¹⁶ cm ⁻³ , respectively. The breakdown voltage of the device is shown. Dashed lines 316, 318, and 319 indicate when the sublayer N-epi1 has a dopant concentration of 5.0 × 10 ¹⁵ cm ⁻³ , 1.0 × 10 ¹⁶ cm ⁻³ , and 1.5 × 10 ¹⁶ cm ⁻³ , respectively. The difference between the breakdown voltage of MOSFET cell 300 and diode cell 302 is shown. In these embodiments, the sublayer N-epi1 is sufficiently thick so that the breakdown voltage of the MOSFET cell 300 and the diode cell 302 does not depend on the thickness of the sublayer N-epi1.

  FIG. 40 is a graph showing breakdown voltage (horizontal axis) in the diode cell as a function of resistivity (left vertical axis) and dopant concentration (right vertical axis) of the lower sublayer N-epi1.

41, 42 and 43 show similar data for a step epi N-channel device having a 30-V drain and a 20-V gate. In FIG. 41, curve 330 shows the breakdown voltage of the MOSFET cell, curve 332 shows the breakdown voltage of the diode cell, and curve 334 shows the difference between the breakdown voltage in the MOSFET cell and the diode cell. The dopant concentration for the lower epi sublayer was 4 × 10 ¹⁶ cm ⁻³ and the upper sublayer was 3.5 μm thick. The horizontal axis represents the dopant concentration of the upper epi sublayer and is in the range of 5.0 × 10 ¹⁵ cm ^{−3 to} 2.5 × 10 ¹⁶ cm ⁻³ . This range can be extended to 3.0 × 10 ¹⁶ cm ⁻³ , with 2.0 × 10 ¹⁶ cm ⁻³ being a suitable concentration.

Figures 42 and 43 show data for similar devices in different forms. In FIG. 42, curve 340 shows the breakdown voltage for the MOSFET cell, curve 342 shows the breakdown voltage for the diode cell, and curve 344 shows the difference between the two values. The dopant concentrations for the upper and lower epi sublayers were 1.0 × 10 ¹⁶ cm ⁻³ and 4.0 × 10 ¹⁶ cm ⁻³ , respectively. The horizontal axis represents the thickness of the upper sublayer, which is in the range of 2 μm to 5 μm, and is officially 3 μm. In FIG. 43, curve 350 shows the breakdown voltage for the MOSFET cell, curve 352 shows the breakdown voltage for the diode cell, and curve 354 shows the difference between the two values. The dopant concentration and thickness of the upper epi sublayer were 1.0 × 10 ¹⁶ cm ⁻³ and 3.5 μm, respectively. The horizontal axis represents the dopant concentration of the lower epi sublayer, which is in the range of 1.0 × 10 ¹⁶ cm ^{−3 to} 5.0 × 10 ¹⁶ cm ⁻³ , preferably 4.0 × 10 ¹⁶ cm ⁻³ . is there.

FIG. 44 shows similar data for a 30-V drain, 20-V gate P-channel device, which utilizes a “reach-through” approach. Curves 360, 362 and 364 show the breakdown voltage of the diode cell when the thickness of the P-epi layer is changed from 4 μm to 8 μm, and are 5.0 × 10 ¹⁵ cm ⁻³ and 1.0 × 10 ¹⁶ , respectively. This represents a P-epi concentration of cm ⁻³ and 2.0 × 10 ¹⁶ cm ⁻³ . Curves 366, 368 and 369 show the difference between the breakdown voltage of the MOSFET cell and the diode cell, respectively, at the same level of P-epi concentration.

45 and 46 show data for a P-channel 20-V drain, 12-V gate device, which used a “reach-through” approach. In both figures, breakdown voltage is depicted as a function of P-epi layer thickness. Curves 370 and 380 show the diode breakdown voltage at a P-epi dopant concentration of 5.0 × 10 ¹⁵ cm ⁻³ , and curves 372 and 382 indicate a P-epi dopant concentration of 1.0 × 10 ¹⁶ cm ^−3. And the curves 374 and 384 show the diode breakdown voltage at a P-epi dopant concentration of 2.0 × 10 ¹⁶ cm ⁻³ . Curves 376 and 386 show the difference in breakdown voltage between the diode and MOSFET cells at a P-epi dopant concentration of 5.0 × 10 ¹⁵ cm ⁻³ , and curves 378 and 388 are 1.0 × 10 ¹⁶ cm. ³ shows the difference in breakdown voltage between a diode cell and a MOSFET cell at a P-epi dopant concentration of ⁻³ , curves 379 and 389 show the difference between the diode cell at a P-epi dopant concentration of 2.0 × 10 ¹⁶ cm ⁻³ and The difference in breakdown voltage from the MOSFET cell is shown.

In P-channel 20-V drain devices, it is somewhat difficult to break down the diode cell before the MOSFET cell. When using thinner gate oxides, as noted above, FPI breakdown tends to occur before PN junction breakdown. Thus, either increasing the dose of implantation used to form the diffusion in the diode cell, or using a special drive-in process to increase the depth of the diode diffusion. May be necessary. FIG. 45 shows the result of a “standard” implantation dose of 1.0 × 10 ¹⁵ cm ⁻² , but using two drive-ins at 1050-1100 ° C. for 1-3 hours. FIG. 46 shows the result of an implantation dose of 4.0 × 10 ¹⁵ cm ⁻² , using two drive-ins at 1050-1100 ° C. for 1-3 hours.

FIG. 47 shows the breakdown voltage for an N-type diode diffusion of approximately 3 μm depth with six different implantation doses, 1.0 × 10 ¹⁵ cm ⁻² (curve 390), 2.0 × 10 ¹⁵ cm ^{−. 2} (curve 391), 3.0 × 10 ¹⁵ cm ⁻² (curve 392), 4.0 × 10 ¹⁵ cm ⁻² (curve 393), 5.0 × 10 ¹⁵ cm ⁻² (curve 394), 6. In the case of 0 × 10 ¹⁵ cm ⁻² (curve 395), it is shown as a function of the thickness of the P-epi layer.

  FIG. 48 shows the breakdown voltage for N-type diode diffusions approximately 3 μm deep with seven different P-epi layer thicknesses: 9.0 μm (curve 400), 8.75 μm (curve 401), 8.5 μm ( Curves 402), 8.25 μm (curve 403), 8.0 μm (curve 404), 7.75 μm (curve 405), and 7.5 μm (curve 406) are shown as a function of implantation dose.

  The above examples are merely illustrative and not limiting. Numerous alternative embodiments in accordance with the broad principles of the present invention will be apparent to those skilled in the art.

10 MOSFET cell 11 trench gate 12 N + source region 13 N + substrate 14 N-epitaxial layer 15 deep P + diffusion 16 P-body 17 channel 20 MOSFET cell 21 gate trench 21A gate oxide layer 21C gate trench corner 22 P-body region 30 Trench gate type MOSFET
31 gate 31A gate oxide layer 32 trench 33 P-body region 33A P + contact region 34 N + source region 35 MOSFET cell 36 metal layer 37 adjacent MOSFET cell 38 diffusion portion 39 PN junction portion 40 MOSFET
41 MOSFET cell 42 Adjacent cell 43 Trench 44 Protective P + diffusion 45 Gate 45A Gate oxide layer 80 MOSFET
81 Active MOSFET cell 82 Active MOSFET cell 83 Active MOSFET cell 84 Active MOSFET cell 85 Diode cell 86 P + region 87 P + contact region 88 N + source region 89 Contact hole 90 Contact hole 91 Gate 92 MOSFET
93 MOSFET cell 100 MOSFET
101 MOSFET cell 110 MOSFET
111 MOSFET cell 112 MOSFET cell 120 MOSFET
121 cell 130 MOSFET
131 Cell 132 Deep P + Region 133 N + Source Region 140 Thick Oxide Layer 141 Thin Oxide Layer 142 Thick Oxide Layer 143 Thin Oxide Layer 170 MOSFET Curve 172 with Deep P + Diffusion Section Curve for MOSFET with Distributed Diode Cells 270 MOSFET cell 272 Diode cell 274 Deep P + diffusion portion 276 Shaded region 280-299 Curve 300 MOSFET cell 302 Diode cell 310-314 Curve 316-319 Broken line 330-406 Curve

Claims (2)

A trench gate type power MOSFET,
A substrate,
An epitaxial layer of a first conductivity type;
A semiconductor material having a transition region between the substrate and the epitaxial layer, wherein the epitaxial layer has a constant dopant concentration along a thickness direction, the transition region from the epitaxial layer to the Having the semiconductor material with a dopant concentration increasing toward the substrate;
The epitaxial layer is
A gate formed in the trench and separated from the epitaxial layer by an oxide layer, wherein the trench is formed in and from the surface of the epitaxial layer, and the trench defines a plurality of MOSFET cells; Each of the cells has a source region of the first conductivity type and a body region of a second conductivity type adjacent to the source region, and the source region and the body region are in contact with a side surface of the trench, The gate,
A deep diffusion portion of the second conductivity type formed inside the epitaxial layer,
A PN junction between the deep diffusion and the portion of the epitaxial layer located above the transition region and below the deep diffusion forms a diode inside the epitaxial layer;
The trench gate type power MOSFET, wherein the PN junction is in contact with the trench on a side surface opposite to the side surface of the trench with which the source region and the body region are in contact. A trench gate type power MOSFET,
A substrate,
A first conductivity type first epitaxial layer formed on the substrate;
A semiconductor material positioned on the first epitaxial layer and having a first conductivity type and including a second epitaxial layer having a different dopant concentration from the first epitaxial layer;
The second epitaxial layer is
A gate formed in the trench and separated from the second epitaxial layer by an oxide layer, wherein the trench is formed therein from the surface of the second epitaxial layer, and the trench includes a plurality of MOSFET cells. Each of the MOSFET cells has a source region of the first conductivity type and a body region of a second conductivity type adjacent to the source region, wherein the source region and the body region are side surfaces of the trench. And the body region is adjacent to the drain region of the first conductivity type, and the gate,
A deep diffusion portion of the second conductivity type extending through the second epitaxial layer and extending into the first epitaxial layer;
A PN junction between the deep diffusion part and each part of the first epitaxial layer and the second epitaxial layer in contact with the deep diffusion part forms a diode,
The trench gate type power MOSFET, wherein the PN junction is in contact with the trench on a different surface opposite to the side of the trench with which the source region and the body region are in contact.

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