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JP2011035334A - Semiconductor device - Google Patents

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JP2011035334A
JP2011035334A JP2009182937A JP2009182937A JP2011035334A JP 2011035334 A JP2011035334 A JP 2011035334A JP 2009182937 A JP2009182937 A JP 2009182937A JP 2009182937 A JP2009182937 A JP 2009182937A JP 2011035334 A JP2011035334 A JP 2011035334A
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sealing material
semiconductor element
wire
semiconductor device
electrode
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JP2011035334A5 (en
JP5586185B2 (en
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Ryo Kuwabara
涼 桑原
Atsushi Yamaguchi
敦史 山口
Hideki Miyagawa
秀規 宮川
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Panasonic Corp
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Panasonic Corp
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    • H10W72/075
    • H10W72/5449
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Abstract

【課題】材料の充填性向上とワイヤ流れの抑制、及びパッケージの放熱性向上を同時に実現することを目的とする。
【解決手段】ワイヤ5の周囲をフィラー充填量の少ない封止材料1で樹脂封止し、それを含めた全体をフィラー充填量の多い封止材料2で樹脂封止することにより、材料の充填性向上とワイヤ流れの抑制、及びパッケージの放熱性向上を同時に実現することができる。
【選択図】図1
An object of the present invention is to simultaneously improve material filling properties, suppress wire flow, and improve heat dissipation of a package.
Filling a material by sealing the periphery of a wire with a sealing material having a small filler filling amount, and sealing the whole including the resin with a sealing material having a large filler filling amount. It is possible to simultaneously improve the performance, suppress the wire flow, and improve the heat dissipation of the package.
[Selection] Figure 1

Description

本発明は、半導体素子とボンディングワイヤを樹脂封止してなる半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor element and a bonding wire are sealed with resin.

集積回路が形成された半導体素子と、これと基板とを電気的に接続する構造としてワイヤボンディング構造とフリップチップ構造が挙げられる。これらの構造を封止材料により包埋することにより、半導体装置が形成される。なかでも、ワイヤボンディング構造においては、放熱効率を考慮して充填剤を多く含んだ封止材料を用いてパッケージングする際、ワイヤに高い圧力がかかり、ワイヤ流れによる不良や電極との接続不良が発生するという問題がある。封止材料の流動性を向上させるためには、封止材料に充填されるフィラーの量を減らすことが有効である。そのため、ワイヤ流れの問題に対し特許文献1では、樹脂硬化体内層と外層の2層構造を取り、内層すなわちワイヤと接する材料の充填剤量を減らしてワイヤへの圧力を低減する方法を取っている。また、電極との接続不良という課題に対して、特許文献2では、半導体素子を積層する構造において、ワイヤボンディング後に1段目の素子と基板との間にアンダーフィルを注入することで、仮にアンダーフィルが基板側の電極に達しても接続不良は生じない構造を取っている。   As a structure for electrically connecting a semiconductor element on which an integrated circuit is formed and a substrate, there are a wire bonding structure and a flip chip structure. A semiconductor device is formed by embedding these structures with a sealing material. In particular, in the wire bonding structure, when packaging is performed using a sealing material containing a large amount of a filler in consideration of heat dissipation efficiency, high pressure is applied to the wire, resulting in defects due to wire flow and poor connection with the electrode. There is a problem that occurs. In order to improve the fluidity of the sealing material, it is effective to reduce the amount of filler filled in the sealing material. Therefore, Patent Document 1 takes a method of reducing the pressure on the wire by taking a two-layer structure of a resin-cured inner layer and an outer layer and reducing the amount of filler in the inner layer, that is, the material in contact with the wire. Yes. In addition, with respect to the problem of poor connection with an electrode, in Patent Document 2, in a structure in which semiconductor elements are stacked, an underfill is injected between a first-stage element and a substrate after wire bonding, thereby temporarily underlining. Even if the fill reaches the electrode on the substrate side, a connection failure does not occur.

一方近年では、LSIの集積度の向上とともにチップの発熱量が増し、封止材料の放熱性向上が要求されている。放熱性の向上に対してはフィラーの種類、充填量を変更し、例えば、フィラーの量を多くすることによって放熱性の向上を図っている(例えば、特許文献3参照)。   On the other hand, in recent years, the amount of heat generated by the chip has been increased along with the improvement of the degree of integration of LSI, and there has been a demand for improving the heat dissipation of the sealing material. For improvement in heat dissipation, the type and filling amount of the filler are changed, for example, the heat dissipation is improved by increasing the amount of the filler (for example, see Patent Document 3).

特開平8−162573号公報JP-A-8-162573 特開2005−191229号公報JP 2005-191229 A 特開2008−106181号公報JP 2008-106181 A

しかしながら、近年の半導体装置では、さらなる放熱性の向上が要求されるようになってきている。
本発明の半導体装置は、上記のような課題を解決するため、材料の充填性向上とワイヤ流れの抑制、及びパッケージの放熱性向上を同時に実現することを目的とする。
However, in recent semiconductor devices, further improvement in heat dissipation has been demanded.
In order to solve the above-described problems, the semiconductor device of the present invention aims to simultaneously improve the material filling property, suppress the wire flow, and improve the heat dissipation property of the package.

上記目的を達成するために、本発明の半導体装置は、第1の電極を備える半導体素子搭載基板と、前記半導体素子搭載基板に搭載されて第2の電極を備える半導体素子と、前記第1の電極と前記第2の電極とを接続するワイヤと、前記ワイヤの周囲の少なくとも一部に設けられる第1の封止材料からなる第1の樹脂硬化体層と、前記半導体素子上及び前記ワイヤ上並びに前記第1の樹脂硬化体層上を含む前記半導体素子搭載基板の半導体素子搭載面を樹脂封止する前記第1の封止材料よりフィラー充填率が多い第2の封止材料からなる第2の樹脂硬化体層とを有し、前記第1の封止材料の方が前記第2の封止材料より流動性が高く、前記第2の封止材料の方が前記第1の封止材料より放熱性が高いことを特徴とする。   In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor element mounting substrate including a first electrode, a semiconductor element mounted on the semiconductor element mounting substrate and including a second electrode, and the first device. A wire connecting the electrode and the second electrode, a first cured resin layer made of a first sealing material provided on at least a part of the periphery of the wire, the semiconductor element, and the wire And a second sealing material having a higher filler filling rate than the first sealing material for resin-sealing the semiconductor element mounting surface of the semiconductor element mounting substrate including the first cured resin layer. The first sealing material has a higher fluidity than the second sealing material, and the second sealing material is the first sealing material. It is characterized by higher heat dissipation.

また、前記第1の封止材料の粘度が1.0Pa・s以上30Pa・s以下であり、前記第2の封止材料の熱伝導率が1.0w/m・k以上5.0w/m・k以下とすることが好ましい。   Further, the viscosity of the first sealing material is 1.0 Pa · s or more and 30 Pa · s or less, and the thermal conductivity of the second sealing material is 1.0 w / m · k or more and 5.0 w / m. -It is preferable to set it as k or less.

また、前記第1の封止材料のフィラー充填率が5w%以上40wt%以下であることが好ましい。
また、前記第2の封止材料のフィラー充填率が60w%以上95wt%以下であることが好ましい。
Moreover, it is preferable that the filler filling rate of said 1st sealing material is 5 to 40 wt%.
Moreover, it is preferable that the filler filling rate of said 2nd sealing material is 60 to 95 wt%.

また、前記第1の封止材料から前記半導体素子の少なくとも一部が露出し、露出した面が前記第2の封止材料と接することが好ましい。
また、前記露出した面の周囲に前記第2の電極が形成されていることが好ましい。
Further, it is preferable that at least a part of the semiconductor element is exposed from the first sealing material, and the exposed surface is in contact with the second sealing material.
Further, it is preferable that the second electrode is formed around the exposed surface.

また、前記第1の電極あるいは前記第2の電極の少なくとも一方が前記第1の封止材料で覆われることが好ましい。
また、前記第1の電極及び前記第2の電極の両方が前記第1の封止材料で覆われることが好ましい。
Moreover, it is preferable that at least one of the first electrode or the second electrode is covered with the first sealing material.
Moreover, it is preferable that both the first electrode and the second electrode are covered with the first sealing material.

また、前記第1の封止材料が、前記ワイヤから前記半導体素子搭載基板及び前記半導体素子に至る領域までに充填されることが好ましい。
また、前記半導体素子搭載基板と前記半導体素子とで形成される角部が前記第1の封止材料で充填されることが好ましい。
Moreover, it is preferable that the first sealing material is filled from the wire to a region extending from the wire to the semiconductor element mounting substrate and the semiconductor element.
Moreover, it is preferable that corners formed by the semiconductor element mounting substrate and the semiconductor element are filled with the first sealing material.

また、前記ワイヤの前記ワイヤと平行する全方向に隣接する領域に前記第1の封止材料が充填されることが好ましい。
また、前記第1の封止材料から前記半導体素子の角部が露出し、露出した面が前記第2の封止材料と接することが好ましい。
Moreover, it is preferable that the first sealing material is filled in a region adjacent to the wire in all directions parallel to the wire.
Moreover, it is preferable that a corner portion of the semiconductor element is exposed from the first sealing material, and an exposed surface is in contact with the second sealing material.

また、前記半導体素子搭載基板に前記半導体素子を接着させるダイボンドとして前記第1の封止材料を用いることが好ましい。
また、前記ダイボンドとして用いられる前記第1の封止材料が前記接着される半導体素子からはみ出すことが好ましい。
Further, it is preferable to use the first sealing material as a die bond for bonding the semiconductor element to the semiconductor element mounting substrate.
Moreover, it is preferable that the first sealing material used as the die bond protrudes from the semiconductor element to be bonded.

また、前記半導体素子搭載基板の前記第2の封止材料が封止される領域内に、前記封止される領域の周囲と、前記半導体装置を中心とした放射状に溝を形成することが好ましい。   In addition, it is preferable to form grooves radially around the semiconductor device and in the region around the semiconductor device, in the region where the second sealing material of the semiconductor element mounting substrate is sealed. .

以上により、材料の充填性向上とワイヤ流れの抑制、及びパッケージの放熱性向上を同時に実現することができる。   As described above, it is possible to simultaneously realize improvement in material filling, suppression of wire flow, and improvement in heat dissipation of the package.

以上のように、ワイヤの周囲をフィラー充填量の少ない封止材料で樹脂封止し、それを含めた全体をフィラー充填量の多い封止材料で樹脂封止することにより、材料の充填性向上とワイヤ流れの抑制、及びパッケージの放熱性向上を同時に実現することができる。   As described above, resin filling with a sealing material with a small filler filling amount around the wire and resin sealing with the sealing material with a large filler filling amount improves the filling of the material. In addition, it is possible to simultaneously suppress the wire flow and improve the heat dissipation of the package.

本発明の半導体装置の構造を示す概略図Schematic showing the structure of the semiconductor device of the present invention 本発明の半導体装置における電極周辺の封止材料充填の様子を示す概略図Schematic which shows the mode of sealing material filling of the electrode periphery in the semiconductor device of this invention 本発明の半導体装置における半導体素子周辺の封止材料充填の様子を示す概略図Schematic which shows the mode of the sealing material filling of the semiconductor element periphery in the semiconductor device of this invention 本発明の半導体装置の製造方法を説明する概略図Schematic explaining the manufacturing method of the semiconductor device of this invention 本発明の半導体装置の製造方法を説明する概略図Schematic explaining the manufacturing method of the semiconductor device of this invention 本発明の半導体装置の製造方法における樹脂材料充填方法を示す概略図Schematic which shows the resin material filling method in the manufacturing method of the semiconductor device of this invention

まず、図1を用いて本発明の半導体装置の特徴を説明する。
図1は本発明の半導体装置の構造を示す概略図であり、封止領域を明確にするために断面図と平面図を示し、平面図では樹脂硬化体層の内部構造を透視的に示している。
First, features of the semiconductor device of the present invention will be described with reference to FIG.
FIG. 1 is a schematic view showing the structure of a semiconductor device of the present invention, showing a cross-sectional view and a plan view in order to clarify the sealing region, and the plan view shows the internal structure of the cured resin layer in perspective. Yes.

本発明の半導体装置は、図1に示すように、半導体素子3を搭載する半導体素子搭載基板4の片面に半導体素子3が搭載され、この半導体素子3の電極7aはワイヤ5を介して半導体素子搭載基板4の電極7bと接続されており、半導体素子3が搭載された半導体素子搭載基板面側のみが封止材料等の樹脂硬化体層によって封止された半導体装置であって、フィラー充填量が少ない封止材料1をワイヤ5上部やワイヤ5下部といったワイヤ5周辺部の少なくとも一部に充填・硬化し、封止材料1よりもフィラー充填量の多い封止材料2で封止材料1を含む全面を覆ってパッケージングする構造をとることを特徴とする。フィラー充填率を低くして流動性を向上させた封止材料1をワイヤ5およびワイヤ5下部等のワイヤ5周辺部のみに充填させることにより、封止材料2導入時のワイヤ流れを効果的に防止できるとともに、封止材料1の硬化後、半導体素子搭載基板4の封止領域上の封止材料1が充填されていない領域全面に放熱性の高い封止材料2を充填することにより、ワイヤ5周辺以外の全面を放熱性の高い封止材料2で樹脂封止することができるため、封止材料2が封止材料1や半導体素子3と接する面積を大きくすることができ、パッケージ全体の放熱性を著しく向上させることが可能となる。   In the semiconductor device of the present invention, as shown in FIG. 1, the semiconductor element 3 is mounted on one surface of a semiconductor element mounting substrate 4 on which the semiconductor element 3 is mounted, and an electrode 7 a of the semiconductor element 3 is connected to the semiconductor element via a wire 5. A semiconductor device that is connected to the electrode 7b of the mounting substrate 4 and in which only the semiconductor element mounting substrate surface side on which the semiconductor element 3 is mounted is sealed with a cured resin layer such as a sealing material, the filler filling amount Filling and curing at least a part of the periphery of the wire 5 such as the upper part of the wire 5 and the lower part of the wire 5 and curing the sealing material 1 with the sealing material 2 having a larger filler filling amount than the sealing material 1 It is characterized by having a structure of covering the entire surface including the packaging. By filling only the peripheral part of the wire 5 such as the wire 5 and the lower part of the wire 5 with the sealing material 1 whose flowability is improved by reducing the filler filling rate, the wire flow at the time of introducing the sealing material 2 is effectively performed. In addition, after the sealing material 1 is cured, the entire surface of the sealing region of the semiconductor element mounting substrate 4 that is not filled with the sealing material 1 is filled with the sealing material 2 having a high heat dissipation property. 5 Since the entire surface other than the periphery can be resin-sealed with the sealing material 2 having high heat dissipation, the area where the sealing material 2 is in contact with the sealing material 1 and the semiconductor element 3 can be increased, and the entire package It becomes possible to remarkably improve heat dissipation.

ここで、封止材料1の粘度が1.0〜30Pa・sとなるようにフィラー充填率を調整することによりワイヤを損傷しない流動性を確保することができ、そのために、一般的には、封止材料1のフィラー充填率を5w%〜40w%にする必要があり、約40w%とすることがより好ましい。フィラー充填率を5w%未満にして粘度が1.0Pa・s未満になると粘度が低すぎて封止樹脂1をワイヤ5周囲に保持することが困難となり、フィラー充填率を40w%より大きくして粘度が30Pa・sを超えると粘度が高くなってワイヤ5の流れや塗付機からの吐出不良が発生するからである。また、封止材料2の熱伝導率を0.2〜0.7w/m・kとなるようにフィラー充填率を調整することにより十分な放熱性を確保することができ、そのために、一般的には、封止材料2のフィラー充填率を60w%〜95w%にする必要があり、約95w%とすることがより好ましい。フィラー充填率を60w%未満にして熱伝導率を0.2w/m・k未満にすると封止材料1との熱伝導率の差が小さいため放熱効率を十分確保できず、フィラー充填率を95w%より大きくして熱伝導率を0.7w/m・kより大きくすると流動性が小さすぎてパッケージ内の空隙の原因となるからである。   Here, the fluidity which does not damage a wire can be secured by adjusting the filler filling rate so that the viscosity of the sealing material 1 is 1.0 to 30 Pa · s. The filler filling rate of the sealing material 1 needs to be 5 w% to 40 w%, and more preferably about 40 w%. If the filler filling rate is less than 5 w% and the viscosity is less than 1.0 Pa · s, the viscosity is too low to make it difficult to hold the sealing resin 1 around the wire 5, and the filler filling rate is made larger than 40 w%. This is because when the viscosity exceeds 30 Pa · s, the viscosity increases, and the flow of the wire 5 or the discharge failure from the coating machine occurs. Moreover, sufficient heat dissipation can be ensured by adjusting the filler filling rate so that the thermal conductivity of the sealing material 2 is 0.2 to 0.7 w / m · k. For this, the filler filling rate of the sealing material 2 needs to be 60 w% to 95 w%, and more preferably about 95 w%. If the filler filling rate is less than 60 w% and the thermal conductivity is less than 0.2 w / m · k, the difference in thermal conductivity with the sealing material 1 is small, so that sufficient heat dissipation efficiency cannot be secured, and the filler filling rate is 95 w. This is because if the thermal conductivity is larger than 0.7% and the thermal conductivity is larger than 0.7 w / m · k, the fluidity is too small to cause voids in the package.

また、フィラーとしては、アルミナ,シリカ,AlN,BN,MgO,ZnOなどを用いることができ、分散性に影響する比重や、熱伝導性,コスト,充填性などの観点からアルミナを用いることが好ましい。   As the filler, alumina, silica, AlN, BN, MgO, ZnO or the like can be used, and it is preferable to use alumina from the viewpoints of specific gravity affecting the dispersibility, thermal conductivity, cost, filling properties, and the like. .

以下、詳細な構成について、図1〜図3を用いて説明する。
図2は本発明の半導体装置における電極周辺の封止材料充填の様子を示す概略図、図3は本発明の半導体装置における半導体素子周辺の封止材料充填の様子を示す概略図であり、図3(b)は図3(a)の直線Bにおける断面図である。
Hereinafter, the detailed configuration will be described with reference to FIGS.
2 is a schematic view showing a state of filling a sealing material around an electrode in the semiconductor device of the present invention, and FIG. 3 is a schematic view showing a state of filling a sealing material around a semiconductor element in the semiconductor device of the present invention. 3 (b) is a cross-sectional view taken along line B in FIG. 3 (a).

上記半導体装置において、封止材料1のワイヤ5およびワイヤ下部を充填する構造において、ワイヤ5が接する素子側あるいは半導体素子搭載基板側の電極の少なくとも一方を覆うように封止材料1を充填することが好ましい。図2(a)の直線Aに沿って切り取ったときの断面図を図2(b)、(c)に示す。図2(b)に示すように、電極7a、7bとワイヤ5の間に封止材料1を充填せず、封止材料2も回り込むことができずに空隙10が残ると、内部に含まれる空気の膨張・収縮の繰り返しに伴い、ワイヤに圧力が集中するため、破損の原因となる。また、封止材料2が回り込むことによってもワイヤ5が変形,破損する場合がある。そこで、図2(c)に示すように、完全にワイヤ下部の空隙を無くすように封止材料1を充填することにより、ワイヤの破損を防止できるとともに、熱伝導率の低い空気の層を極力無くし、パッケージの放熱性を向上させることができる。また、より好ましくは、素子側の電極7a、半導体素子搭載基板側の電極7bの両方を覆うように封止材料1を充填する構造をとることにより、さらに放熱性を向上させることができる。   In the semiconductor device, in the structure in which the wire 5 and the wire lower part of the sealing material 1 are filled, the sealing material 1 is filled so as to cover at least one of the electrode on the element side or the semiconductor element mounting substrate side with which the wire 5 contacts. Is preferred. 2B and 2C show cross-sectional views taken along the straight line A in FIG. As shown in FIG. 2 (b), if the sealing material 1 is not filled between the electrodes 7a, 7b and the wire 5, and the sealing material 2 cannot wrap around and the gap 10 remains, it is included inside. As the air expands and contracts repeatedly, the pressure concentrates on the wire, causing damage. Further, the wire 5 may be deformed or damaged when the sealing material 2 wraps around. Therefore, as shown in FIG. 2 (c), by filling the sealing material 1 so as to completely eliminate the gap below the wire, the wire can be prevented from being damaged and an air layer having a low thermal conductivity can be formed as much as possible. This can improve the heat dissipation of the package. More preferably, the heat dissipation can be further improved by adopting a structure in which the sealing material 1 is filled so as to cover both the electrode 7a on the element side and the electrode 7b on the semiconductor element mounting substrate side.

上記各半導体装置において、図1に示すように、ワイヤ下部の空間8が、半導体素子3および半導体素子搭載基板4で形成される角まで封止材料1によって完全に充填されていることが好ましい。図1に示すように、封止材料1によって、ワイヤ5の周りだけでなく、半導体素子3に接する部分にまでも封止材料1を充填し、この空間の空隙発生を抑制することにより、半導体素子3を補強し、かつワイヤの損傷を防止することができるとともに、電極7a、7bの周囲と同様に、空気の層を極力無くすことにより、パッケージの放熱性をさらに向上させることができる。   In each of the above semiconductor devices, as shown in FIG. 1, it is preferable that the space 8 below the wire is completely filled with the sealing material 1 up to the corner formed by the semiconductor element 3 and the semiconductor element mounting substrate 4. As shown in FIG. 1, the sealing material 1 fills the sealing material 1 not only around the wire 5 but also into the portion in contact with the semiconductor element 3 and suppresses the generation of voids in this space. The element 3 can be reinforced and damage to the wire can be prevented, and the heat dissipation of the package can be further improved by eliminating the air layer as much as possible around the electrodes 7a and 7b.

上記各半導体装置において、封止材料1の充填・硬化時に半導体素子3の一部の表面を露出させ、その露出した表面を覆うように封止材料2を封止することが好ましい。図1に示すように、封止材料2と半導体素子3の例えば上面中心部9を直接接触させることにより、放熱性の高い封止材料2が半導体素子3からの発熱を直接パッケージ外部へと伝導させることが可能となり、パッケージ全体の放熱性を向上させることができる。特に好ましくは、前記露出されている一部の表面は、半導体素子3表面の周囲近傍に設けられている上面電極7aの形成領域の内部領域とする。これにより、少なくとも電極7a周囲を封止材料1で充填してワイヤ5の変形,破損を防止し、それ以外の半導体素子3表面を封止材料2と接触させることにより放熱性を向上させることができる。   In each of the semiconductor devices described above, it is preferable that a part of the surface of the semiconductor element 3 is exposed when the sealing material 1 is filled and cured, and the sealing material 2 is sealed so as to cover the exposed surface. As shown in FIG. 1, the sealing material 2 and the semiconductor element 3 are brought into direct contact with, for example, the center 9 on the upper surface, so that the sealing material 2 with high heat dissipation directly conducts heat generated from the semiconductor element 3 to the outside of the package. It is possible to improve the heat dissipation of the entire package. Particularly preferably, the exposed part of the surface is an internal region of the formation region of the upper surface electrode 7 a provided in the vicinity of the periphery of the surface of the semiconductor element 3. Thereby, at least the periphery of the electrode 7a is filled with the sealing material 1 to prevent the wire 5 from being deformed or damaged, and the heat dissipation can be improved by bringing the other surface of the semiconductor element 3 into contact with the sealing material 2. it can.

上記各半導体装置において、半導体素子3を半導体素子搭載基板4に接着するためのダイボンドとして、半導体素子3と半導体素子搭載基板4との間に封止材料1を使用して固定することが好ましい。図1に示すように、封止材料1をダイボンドとして用いることにより、半導体素子3の下面および側面が同じ材料で封止されることになり、熱応力の差による半導体素子3自体の変形が抑制される効果があるとともに、同じ材料を用いることでコスト低減にも繋がると考えられる。さらに、充填性がよいため、未充填空隙による空気の層を極力無くすことができ、パッケージの放熱性を向上させることができる。さらに好ましくは、半導体素子3と半導体素子搭載基板4の接する界面を上面側から見た際に、ダイボンドとして用いる封止材料1を半導体素子3の外側にはみ出させることが好ましい(図3(a))。図3(c)に示すように、封止材料1のはみ出しが無い場合、封止材料2を充填する際に、ワイヤ5の無い部分では、封止材料2が半導体素子3に到達しととしても、半導体素子3と半導体素子搭載基板4が接する角部への充填が困難である。しかしながら、図3(d)に示すように、封止材料1のはみ出し12がある場合、材料が半導体素子3に到達すると、はみ出し12に沿って、上向きに封止材料2の流れが作られるため、封止材料2の充填がスムーズになるとともに、空隙の発生も抑制できる。これにより、充填時のタクトを短縮でき、パッケージ全体としての放熱性を向上させることができる。   In each of the above semiconductor devices, it is preferable to fix the semiconductor element 3 between the semiconductor element 3 and the semiconductor element mounting substrate 4 by using the sealing material 1 as a die bond for bonding the semiconductor element 3 to the semiconductor element mounting substrate 4. As shown in FIG. 1, by using the sealing material 1 as a die bond, the lower surface and the side surface of the semiconductor element 3 are sealed with the same material, and deformation of the semiconductor element 3 itself due to a difference in thermal stress is suppressed. It is considered that the same material can be used and the cost can be reduced. Furthermore, since the filling property is good, the air layer due to the unfilled voids can be eliminated as much as possible, and the heat dissipation property of the package can be improved. More preferably, when the interface between the semiconductor element 3 and the semiconductor element mounting substrate 4 is viewed from the upper surface side, it is preferable that the sealing material 1 used as a die bond protrudes outside the semiconductor element 3 (FIG. 3A). ). As shown in FIG. 3C, when the sealing material 1 does not protrude, when the sealing material 2 is filled, the sealing material 2 reaches the semiconductor element 3 in the portion where the wire 5 is not present. However, it is difficult to fill the corners where the semiconductor element 3 and the semiconductor element mounting substrate 4 are in contact. However, as shown in FIG. 3D, when there is an overhang 12 of the sealing material 1, when the material reaches the semiconductor element 3, the flow of the encapsulating material 2 is made upward along the overhang 12. Moreover, the filling of the sealing material 2 becomes smooth and the generation of voids can be suppressed. Thereby, the tact time at the time of filling can be shortened, and the heat dissipation as the whole package can be improved.

上記各半導体装置において、ワイヤ5の周囲の内、各ワイヤ5の隣接方向に対する両側にも封止材料1を充填し、ワイヤ5の側面部に封止材料1からなる構造13を設ける構成とすることが好ましい。図3(e)に示すように、ワイヤ5側面に封止材料1が充填されていない場合、ワイヤ5側面への封止材料2の充填性が悪く、空隙を発生するおそれがある。したがって、図3(f)に示すように、ワイヤ5両側に封止材料1を充填することにより、封止材料2の流動をスムーズにし、充填性を向上することができる。これにより、充填時のタクトを短縮でき、パッケージ全体としての放熱性が向上する。   In each of the semiconductor devices described above, the sealing material 1 is filled on both sides of the periphery of the wire 5 with respect to the adjacent direction of the wire 5, and the structure 13 made of the sealing material 1 is provided on the side surface of the wire 5. It is preferable. As shown in FIG. 3E, when the sealing material 1 is not filled on the side surface of the wire 5, the filling property of the sealing material 2 on the side surface of the wire 5 is poor, and a void may be generated. Therefore, as shown in FIG. 3F, by filling the both sides of the wire 5 with the sealing material 1, the flow of the sealing material 2 can be made smooth and the filling property can be improved. Thereby, the tact at the time of filling can be shortened and the heat dissipation as the whole package improves.

上記各半導体装置において、半導体素子3表面の4隅の角部11には封止材料1を充填せず、角部11を直接封止材料2と接触させることが好ましい。図3(b)に示すように、封止材料1が半導体素子3の角部11を露出することにより、放熱性の高い封止材料2と半導体素子3とが直接接するため、パッケージ全体としての放熱性が著しく向上させることができる。   In each of the semiconductor devices described above, it is preferable that the corners 11 at the four corners of the surface of the semiconductor element 3 are not filled with the sealing material 1 and the corners 11 are directly brought into contact with the sealing material 2. As shown in FIG. 3B, since the sealing material 1 exposes the corner 11 of the semiconductor element 3, the sealing material 2 with high heat dissipation and the semiconductor element 3 are in direct contact with each other. The heat dissipation can be remarkably improved.

上記各半導体装置において、図1に示すように、半導体素子搭載基板4表面に溝6を切ることが好ましい。この溝6は、少なくとも半導体素子搭載基板4と封止材料2が接する領域に設けられ、封止材料2形成領域の外周に形成される溝と、封止材料2形成領域内部に半導体素子3搭載領域から外周方向に放射状に形成される溝とからなる。封止材料2の流動性は低いため、空隙等の充填不良が生じることがあるが、溝6を切ることにより、封止材料2の流動性を確保することができる。さらに、封止材料2の周囲にバリが生じることがあるが、封止材料2を囲うように溝6を形成することにより、溝6を越えて周囲に封止材料2が濡れ広がることが抑制され、バリの発生を抑制することができる。これにより、封止材料2のムダを削減するとともに、タクトを短縮し、半導体素子搭載基板4と封止材料2の接触する表面積を増やすことにより、封止材料2からの放熱性をさらに向上させることもできる。   In each of the semiconductor devices described above, it is preferable to cut a groove 6 on the surface of the semiconductor element mounting substrate 4 as shown in FIG. The groove 6 is provided at least in a region where the semiconductor element mounting substrate 4 and the sealing material 2 are in contact with each other, the groove formed in the outer periphery of the sealing material 2 forming region, and the semiconductor element 3 mounted in the sealing material 2 forming region. It consists of grooves formed radially from the region in the outer circumferential direction. Since the fluidity of the sealing material 2 is low, filling defects such as voids may occur. However, the fluidity of the sealing material 2 can be ensured by cutting the grooves 6. Further, burrs may be generated around the sealing material 2, but by forming the groove 6 so as to surround the sealing material 2, it is possible to suppress the sealing material 2 from spreading out around the groove 6. Thus, the generation of burrs can be suppressed. As a result, the waste of the sealing material 2 is reduced, the tact time is shortened, and the surface area where the semiconductor element mounting substrate 4 and the sealing material 2 come into contact is increased, thereby further improving the heat dissipation from the sealing material 2. You can also.

次に、図4〜図6を用いてこの半導体装置の具体的な作製方法を例示する。
図4,図5は本発明の半導体装置の製造方法を説明する概略図であり、平面図と直線Cにおける断面図からなる。図6は本発明の半導体装置の製造方法における樹脂材料充填方法を示す概略図である。
Next, a specific method for manufacturing the semiconductor device is illustrated with reference to FIGS.
4 and 5 are schematic views for explaining a method of manufacturing a semiconductor device according to the present invention, which includes a plan view and a cross-sectional view along a straight line C. FIG. FIG. 6 is a schematic view showing a resin material filling method in the semiconductor device manufacturing method of the present invention.

ここで用いる封止材料1、2は以下の通りである。
封止材料1:CV5314PAX (パナソニック電工製)
フィラー充填率40wt%
封止材料2:高放熱封止材料
フィラー充填率95wt%
まず、半導体素子3を半導体素子搭載基板4に実装するため、図4(a)に示すように、ダイボンドとして封止材料1を、半導体素子搭載基板4の半導体素子3形成領域よりはみ出させて適量印刷または塗布を行い、半導体素子3を搭載したのちに硬化する。この際の材料供給は、スクリーン印刷機または塗布装置で供給する。
The sealing materials 1 and 2 used here are as follows.
Sealing material 1: CV5314PAX (manufactured by Panasonic Electric Works)
Filler filling rate 40wt%
Sealing material 2: High heat dissipation sealing material
Filler filling rate 95wt%
First, in order to mount the semiconductor element 3 on the semiconductor element mounting substrate 4, as shown in FIG. 4A, the sealing material 1 is protruded from the semiconductor element 3 formation region of the semiconductor element mounting substrate 4 as an appropriate amount as a die bond. After printing or coating and mounting the semiconductor element 3, it is cured. In this case, the material is supplied by a screen printer or a coating device.

次に、図4(b)に示すように、半導体素子搭載基板4上の電極7bと半導体素子3上面の電極7aをワイヤ5で接続する。ワイヤ5の供給はワイヤボンディング装置を用いて行う。   Next, as shown in FIG. 4B, the electrode 7 b on the semiconductor element mounting substrate 4 and the electrode 7 a on the upper surface of the semiconductor element 3 are connected by the wire 5. Supply of the wire 5 is performed using a wire bonding apparatus.

次に、図5(a)に示すように、封止材料1をワイヤ5の周囲およびワイヤ5近辺の半導体素子搭載基板4、半導体素子3上等に塗布する。この際、塗布機には非接触塗布機S−920(アシムテック製)などを用いてワイヤ5の間から塗布する。ワイヤ5下およびワイヤ5の上側にかかるまで塗布を行う。その後、半導体素子搭載基板4と半導体素子3の界面で、ワイヤ5のない部分にも先述した塗布機にて封止材料1の塗布を行い、所定の硬化条件で硬化する。   Next, as shown in FIG. 5A, the sealing material 1 is applied on the semiconductor element mounting substrate 4, the semiconductor element 3, and the like around the wire 5 and in the vicinity of the wire 5. At this time, the non-contact coating machine S-920 (manufactured by Asymtec) is used as the coating machine, and the coating is performed between the wires 5. The coating is performed until it reaches under the wire 5 and above the wire 5. Thereafter, the sealing material 1 is applied to the portion where the wires 5 are not present at the interface between the semiconductor element mounting substrate 4 and the semiconductor element 3 by the above-described coating machine and cured under predetermined curing conditions.

最後に、図5(b)に示すように、半導体素子3上や封止材料1上を含む半導体素子搭載基板4上の封止材料2塗布領域に封止材料2を充填する。充填方法としては、封止材料2の形態により、真空印刷法またはトランスファーモールド法を用いる。封止材料2が液状熱硬化樹脂の場合、真空印刷法を用い、タブレット状の場合はトランスファーモールド法を用いる。   Finally, as shown in FIG. 5B, the sealing material 2 is filled in the sealing material 2 application region on the semiconductor element mounting substrate 4 including the semiconductor element 3 and the sealing material 1. As a filling method, a vacuum printing method or a transfer molding method is used depending on the form of the sealing material 2. When the sealing material 2 is a liquid thermosetting resin, a vacuum printing method is used, and when it is a tablet, a transfer molding method is used.

特にトランスファーモールド法を用いる場合、図6に示すように、封止材料2はゲート口16から注入され、矢印に示されるように充填が進んでいく。
なお、ダイボンド材料と封止材料1は同じ材料でなくても良い。
In particular, when the transfer molding method is used, as shown in FIG. 6, the sealing material 2 is injected from the gate port 16 and the filling proceeds as shown by the arrows.
Note that the die bond material and the sealing material 1 may not be the same material.

本発明は、材料の充填性向上とワイヤ流れの抑制、及びパッケージの放熱性向上を同時に実現することができ、半導体素子とボンディングワイヤを樹脂封止してなる半導体装置等に有用である。   INDUSTRIAL APPLICABILITY The present invention can simultaneously improve material filling properties, suppress wire flow, and improve heat dissipation of a package, and is useful for a semiconductor device or the like in which a semiconductor element and a bonding wire are sealed with a resin.

1 封止材料
2 封止材料
3 半導体素子
4 半導体素子搭載基板
5 ワイヤ
6 溝
7a 電極
7b 電極
8 空間
9 中心部
10 空隙
11 角部
12 はみ出し
13 構造
16 ゲート口
DESCRIPTION OF SYMBOLS 1 Sealing material 2 Sealing material 3 Semiconductor element 4 Semiconductor element mounting substrate 5 Wire 6 Groove 7a Electrode 7b Electrode 8 Space 9 Center part 10 Space | gap 11 Corner | angular part 12 Projection 13 Structure 16 Gate port

Claims (15)

第1の電極を備える半導体素子搭載基板と、
前記半導体素子搭載基板に搭載されて第2の電極を備える半導体素子と、
前記第1の電極と前記第2の電極とを接続するワイヤと、
前記ワイヤの周囲の少なくとも一部に設けられる第1の封止材料からなる第1の樹脂硬化体層と、
前記半導体素子上及び前記ワイヤ上並びに前記第1の樹脂硬化体層上を含む前記半導体素子搭載基板の半導体素子搭載面を樹脂封止する前記第1の封止材料よりフィラー充填率が多い第2の封止材料からなる第2の樹脂硬化体層と
を有し、前記第1の封止材料の方が前記第2の封止材料より流動性が高く、前記第2の封止材料の方が前記第1の封止材料より放熱性が高いことを特徴とする半導体装置。
A semiconductor element mounting substrate comprising a first electrode;
A semiconductor element mounted on the semiconductor element mounting substrate and provided with a second electrode;
A wire connecting the first electrode and the second electrode;
A first cured resin layer made of a first sealing material provided on at least a part of the periphery of the wire;
The filler filling rate is higher than that of the first sealing material for resin-sealing the semiconductor element mounting surface of the semiconductor element mounting substrate including the semiconductor element, the wire, and the first resin cured body layer. A second cured resin layer made of the sealing material, and the first sealing material has higher fluidity than the second sealing material, and the second sealing material The semiconductor device is characterized in that it has higher heat dissipation than the first sealing material.
前記第1の封止材料の粘度が1.0Pa・s以上30Pa・s以下であり、前記第2の封止材料の熱伝導率が1.0w/m・k以上5.0w/m・k以下とすることを特徴とする請求項1記載の半導体装置。   The viscosity of the first sealing material is 1.0 Pa · s to 30 Pa · s, and the thermal conductivity of the second sealing material is 1.0 w / m · k to 5.0 w / m · k. The semiconductor device according to claim 1, wherein: 前記第1の封止材料のフィラー充填率が5w%以上40wt%以下であることを特徴とする請求項1または請求項2のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, wherein a filler filling rate of the first sealing material is 5 w% or more and 40 wt% or less. 前記第2の封止材料のフィラー充填率が60w%以上95wt%以下であることを特徴とする請求項1〜請求項3のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a filler filling rate of the second sealing material is 60 w% or more and 95 wt% or less. 前記第1の封止材料から前記半導体素子の少なくとも一部が露出し、露出した面が前記第2の封止材料と接することを特徴とする請求項1〜請求項4のいずれかに記載の半導体装置。   5. The device according to claim 1, wherein at least a part of the semiconductor element is exposed from the first sealing material, and the exposed surface is in contact with the second sealing material. Semiconductor device. 前記露出した面の周囲に前記第2の電極が形成されていることを特徴とする請求項5記載の半導体装置。   The semiconductor device according to claim 5, wherein the second electrode is formed around the exposed surface. 前記第1の電極あるいは前記第2の電極の少なくとも一方が前記第1の封止材料で覆われることを特徴とする請求項1〜請求項6のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein at least one of the first electrode and the second electrode is covered with the first sealing material. 前記第1の電極及び前記第2の電極の両方が前記第1の封止材料で覆われることを特徴とする請求項7記載の半導体装置。   8. The semiconductor device according to claim 7, wherein both the first electrode and the second electrode are covered with the first sealing material. 前記第1の封止材料が、前記ワイヤから前記半導体素子搭載基板及び前記半導体素子に至る領域までに充填されることを特徴とする請求項1〜請求項8のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first sealing material is filled from the wire to a region extending from the wire to the semiconductor element mounting substrate and the semiconductor element. 前記半導体素子搭載基板と前記半導体素子とで形成される角部が前記第1の封止材料で充填されることを特徴とする請求項9記載の半導体装置。   The semiconductor device according to claim 9, wherein a corner formed by the semiconductor element mounting substrate and the semiconductor element is filled with the first sealing material. 前記ワイヤの前記ワイヤと平行する全方向に隣接する領域に前記第1の封止材料が充填されることを特徴とする請求項9または請求項10のいずれかに記載の半導体装置。   11. The semiconductor device according to claim 9, wherein the first sealing material is filled in a region adjacent to the wire in all directions parallel to the wire. 前記第1の封止材料から前記半導体素子の角部が露出し、露出した面が前記第2の封止材料と接することを特徴とする請求項1〜請求項11のいずれかに記載の半導体装置。   12. The semiconductor according to claim 1, wherein a corner portion of the semiconductor element is exposed from the first sealing material, and an exposed surface is in contact with the second sealing material. apparatus. 前記半導体素子搭載基板に前記半導体素子を接着させるダイボンドとして前記第1の封止材料を用いることを特徴とする請求項1〜請求項12のいずれかに記載の半導体装置。   13. The semiconductor device according to claim 1, wherein the first sealing material is used as a die bond for bonding the semiconductor element to the semiconductor element mounting substrate. 前記ダイボンドとして用いられる前記第1の封止材料が前記接着される半導体素子からはみ出すことを特徴とする請求項13記載の半導体装置。   14. The semiconductor device according to claim 13, wherein the first sealing material used as the die bond protrudes from the semiconductor element to be bonded. 前記半導体素子搭載基板の前記第2の封止材料が封止される領域内に、前記封止される領域の周囲と、前記半導体装置を中心とした放射状に溝を形成することを特徴とする請求項1〜請求項14のいずれかに記載の半導体装置。   Grooves are formed radially around the region to be sealed and around the semiconductor device in a region of the semiconductor element mounting substrate where the second sealing material is sealed. The semiconductor device according to claim 1.
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