JP2011035325A - Semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

When a bipolar transistor is operated, it is possible to suppress destruction of an end portion on a collector side in a base region.
A base region is formed in a well. The emitter region 170 is formed in the base region 150 and is shallower than the base region 150. The collector region 140 is formed in the well 110 and is located outside the base region 150. The first buried region 180 is at least partially located in the base region 150 and has a higher impurity concentration than the base region 150. The first buried region 180 is at least partially located between the emitter region 170 and the collector region 140 in plan view. The first buried region 180 overlaps at least one side of the edge of the emitter region 170 and does not overlap the entire surface of the emitter region 170.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a bipolar transistor as an element for protecting an internal circuit from an abnormal current and a method for manufacturing the semiconductor device.

  Bipolar transistors are sometimes used to protect transistors and the like constituting a circuit from abnormal current such as static electricity (for example, Patent Documents 1 to 3).

In particular, Patent Document 1 describes a semiconductor device having the following bipolar transistor. A buried n ⁺ region is formed in the substrate, and an n-type semiconductor substrate for forming a bipolar transistor is formed above the n ⁺ region. An n-type region is formed between the semiconductor substrate and the buried n ⁺ region. The n-type region has a higher impurity concentration than the semiconductor substrate and a lower impurity concentration than the n ⁺ region. Thus, it is described that generation of hot spots is suppressed, and as a result, electrostatic withstand voltage is improved.

In Patent Document 2, a semiconductor device having the following bipolar transistor is formed. A buried n ⁺ region is formed in the substrate, and an n-type semiconductor substrate for forming a bipolar transistor is formed above the n ⁺ region. A base sink p-type region including the emitter and base of the bipolar transistor is formed on the semiconductor substrate. The base sink p-type region has a lower portion connected to the buried n ⁺ region. Thus, it is described that generation of hot spots is suppressed, and as a result, electrostatic withstand voltage is improved.

JP 2007-202202 A JP 2007-194509 A JP 2000-236070 A

  As a result of investigation by the present inventor, it has been found that when the emitter is formed in the base region and the collector is formed outside the base region, the end of the base region on the collector side is easily destroyed. For this reason, in order to improve the withstand capability of the bipolar transistor, it is necessary to make the end portion on the collector side of the base region difficult to be destroyed.

According to the present invention, a first conductivity type well formed on a substrate;
A second conductivity type base region formed in the well;
A high-concentration base region of a second conductivity type formed in a part of a surface layer of the base region and having an impurity concentration higher than that of the base region;
An emitter region of a first conductivity type formed in the base region and shallower than the base region;
A first conductivity type collector region formed in the well and located outside the base region;
A first conductivity region of a second conductivity type, at least part of which is located in the base region and having a higher impurity concentration than the base region;
With
In plan view, the first embedded region is
At least a portion is located between the emitter region and the collector region;
A semiconductor device is provided that overlaps at least one side of the edge of the emitter region and does not overlap the entire surface of the emitter region.

  When an abnormal current such as static electricity flows through a bipolar transistor as a protective element, if the current concentrates on a specific part of the bipolar transistor, the current concentrated part generates heat, which can destroy the bipolar transistor. is there. When an emitter is formed in the base region and a collector is formed outside the base region, the collector-side end portion of the base region is easily destroyed. The cause of this is that before the bipolar transistor is operated, a current due to the avalanche effect flows out at the collector-side end of the base region, and due to this current, the potential gradient at the collector-side end of the base region is steep. It is thought to become.

  On the other hand, in the present invention, the first buried region is formed. The first buried region is at least partially located between the emitter region and the collector region in plan view, and overlaps the collector region side edge of the emitter region. The first buried region does not overlap the entire surface of the emitter region. For this reason, even if a current due to the avalanche effect flows out at the collector-side end portion of the base region, the potential gradient caused by this current is relaxed by the first buried region. Therefore, when the bipolar transistor operates, the end of the base region on the collector side is prevented from being destroyed.

According to the present invention, a step of forming a first conductivity type well on a substrate;
Forming a second conductivity type base region located in the well on the substrate;
A second conductivity type high-concentration base region having a higher impurity concentration than the base region and located in a part of a surface layer of the base region on the substrate, and located in the base region from the base region Forming a shallow first conductivity type emitter region and a first conductivity type collector region located in the well and outside the base region, respectively.
With
After the step of forming the well, the method includes a step of forming a first conductive region of a second conductivity type at least partially located in the base region and having a higher impurity concentration than the base region,
In plan view, the first embedded region is
At least a portion is located between the emitter region and the collector region;
A method of manufacturing a semiconductor device is provided that overlaps at least one side of the edge of the emitter region and does not overlap the entire surface of the emitter region.

  According to the present invention, when the bipolar transistor operates, it is possible to suppress the destruction of the end portion on the collector side in the base region.

(A) is sectional drawing which shows the structure of the bipolar transistor which the semiconductor device which concerns on 1st Embodiment has, (b) is sectional drawing which shows the structure of the field effect transistor which a semiconductor device has It is. FIG. 2 is a plan view of the bipolar transistor shown in FIG. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIGS. 1 and 2. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIGS. 1 and 2. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIGS. 1 and 2. It is a graph explaining the effect | action and effect of 1st Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a graph explaining the effect | action and effect of 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. FIG. 10 is a plan view of the bipolar transistor shown in FIG. It is a graph explaining the effect | action and effect of 3rd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 5th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 7th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 8th Embodiment. FIG. 17 is a plan view of the bipolar transistor shown in FIG. It is a figure which shows distribution of the impurity concentration of the bipolar transistor used for simulation. It is a figure which shows the flow of the collector current immediately after a bipolar transistor turns on. It is a figure which shows the flow of a collector current when a collector current becomes large enough. It is a graph which shows the result of the TLP test concerning an Example (solid line) and a comparative example (dotted line).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
1A and 1B are cross-sectional views showing a part of the configuration of the semiconductor device according to the first embodiment. FIG. 1A shows a configuration of a bipolar transistor as a protective element included in a semiconductor device, and FIG. 1B shows a field-effect transistor as a protected element included in the semiconductor device. The configuration is shown. FIG. 2 is a plan view of the bipolar transistor shown in FIG. In FIG. 2, the separation well 190 is not shown for the sake of explanation. FIG. 1A shows a cross section taken along the line AA ′ of FIG.

  First, the configuration of the bipolar transistor will be described with reference to FIGS. The bipolar transistor includes a first conductivity type (eg, n-type) well 110, a second conductivity type (eg, p-type) base region 150, a second conductivity type high-concentration base region 160, and a first conductivity type formed on the substrate 100. A conductive type emitter region 170, a first conductive type collector region 140, and a second conductive type first buried region 180 are provided. The base region 150 is formed in the well 110. The high concentration base region 160 is formed in a part of the surface layer of the base region 150 and has a higher impurity concentration than the base region 150. The emitter region 170 is formed in the base region 150 and is shallower than the base region 150. The collector region 140 is formed in the well 110 and is located outside the base region 150. The first buried region 180 is at least partially located in the base region 150 and has a higher impurity concentration than the base region 150. The first buried region 180 is at least partially located between the emitter region 170 and the collector region 140 in plan view. The first buried region 180 overlaps at least one of the edges of the emitter region 170, for example, the edge on the collector region 140 side, and does not overlap the entire surface of the emitter region 170. Further, the first buried region 180 does not overlap the high concentration base region 160.

That is, the first buried region 180 is a distance w ₁ from the end on the high concentration base region 160 side to the end on the high concentration base region 160 side in the emitter region 170 (the direction toward the high concentration base region 160 is positive) And the distance w ₂ from the end on the collector region 140 side to the end on the collector region 140 side of the emitter region 170 (toward the high-concentration base region 160). The direction is a positive direction, and the direction toward the collector region 140 is a negative direction). The first embedded region 180 has a lower end located below the lower end of the base region 150.

  The substrate 100 has a configuration in which a second conductivity type epitaxial growth layer 104 is formed on a second conductivity type semiconductor substrate 102. The well 110, the collector region 140, and the base region 150 are formed in the epitaxial growth layer 104. A second conductive region 120 of the first conductivity type is formed on the substrate 100. The second buried region 120 is formed on the entire lower surface of the well 110 and is connected to the collector region 140 via the first conductivity type sink region 130. Therefore, the collector current of the bipolar transistor flows from the emitter region 170 to the collector region 140 via the second buried region 120 and the sink region 130.

  The epitaxial growth layer 104 has a second conductivity type isolation well 190. The isolation well 190 is provided to isolate the bipolar transistor from other regions, and is formed so as to surround the bipolar transistor in plan view.

  The epitaxial growth layer 104 has an element isolation region 200 on the surface. The element isolation region 200 is formed by, for example, the LOCOS oxidation method, but may be formed by the STI method. The element isolation region 200 separates the collector region 140, the high-concentration base region 160, the emitter region 170, and the isolation well 190 from other regions.

A part of the base region 150 is located below the element isolation region 200. In the first buried region 180, the distance w ₂ from the edge on the collector region 140 side to the emitter region 170 is larger than the distance t from the lower end of the base region 150 to the lower end of the element isolation region 200.

  Silicide layers 145, 165, and 175 are formed on the surfaces of the collector region 140, the high concentration base region 160, and the emitter region 170, respectively.

  Next, the configuration of a field effect transistor as a protected element will be described with reference to FIG. The field effect transistor is formed in the second conductivity type well 310, and includes a gate insulating film 352, a gate electrode 350, a first conductivity type drain region 370, a first conductivity type drain extension region 372, and a first conductivity type. A conductive type source region 360, a second conductive type back gate electrode 380, and a second conductive type low concentration impurity region 382 are provided. The well 310 is formed in the epitaxial growth layer 104. The source region 360 and the back gate electrode 380 are formed in the low concentration impurity region 382. A common silicide layer 384 is formed on the surface layer of the source electrode 360 and the back gate electrode 380. That is, the source electrode 360 and the back gate electrode 380 are connected to each other by the silicide layer 384. The drain extension region 372 has a lower impurity concentration than the drain region 370. A silicide layer 374 is formed on the surface layer of the drain region 370.

  A first conductivity type buried region 320 and a first conductivity type sink region 330 are formed in the substrate 100. The buried region 320 is formed on the entire lower surface of the well 310, and the sink region 330 is formed so as to surround the side of the well 310. That is, the well 310 is surrounded by the buried region 320 and the sink region 330. A high-concentration impurity layer 340 of the first conductivity type is formed on the surface layer of the sink region 330. The high concentration impurity layer 340 has an impurity concentration higher than that of the sink region 330 and is connected to the drain region 370 by wiring (not shown) in the wiring layer on the substrate 100. That is, the high concentration impurity layer 340 functions as a second drain region. Note that a silicide layer 342 is formed on the surface layer of the high concentration impurity layer 340.

  The element isolation region 200 surrounds the field-effect transistor and partly surrounds the drain region 370 and the high-concentration impurity layer 340 so as to isolate them from others.

  3, 4, and 5 are cross-sectional views illustrating a method of manufacturing the semiconductor device illustrated in FIGS. 1 and 2. 3A, FIG. 4A, and FIG. 5A correspond to FIG. 1A, and FIG. 3B, FIG. 4B, and FIG. ) Corresponds to FIG. 1B. In this semiconductor device manufacturing method, first, a well 110 and a base region 150 are formed in this order on a substrate 100. Next, a high-concentration base region 160, an emitter region 170, and a collector region 140 are formed on the substrate 100, respectively. Then, after the step of forming the well 110, a step of forming the first buried region 180 is provided. This will be described in detail below.

  First, as shown in FIGS. 3A and 3B, by selectively implanting a first conductivity type impurity (for example, As) into the semiconductor substrate 102, the second buried region 120 and the buried region 320 are formed. Form. Next, an epitaxial growth layer 104 is formed on the semiconductor substrate 102. Next, the well 110, the well 310, the element isolation region 200, and the sink region 130 are formed in this order. In this step, impurities in the second buried region 120 and the buried region 320 are diffused, and the second buried region 120 and the buried region 320 extend to the epitaxial growth layer 104. In the step of forming the sink region 130, the sink region 330 is also formed.

  Next, as shown in FIGS. 4A and 4B, a resist pattern (not shown) is formed on the substrate 100, and impurities of the second conductivity type are implanted into the substrate 100 using the resist pattern as a mask. Thereby, the base region 150 is formed. In this step, a low concentration impurity region 382 and a separation well 190 are also formed. Thereafter, the resist pattern is removed.

  Next, a resist pattern (not shown) is formed on the substrate 100, and a first conductivity type impurity is implanted into the substrate 100 using the resist pattern as a mask. As a result, the drain extension region 372 is formed. Thereafter, the resist pattern is removed. Next, the gate insulating film 352, the gate electrode 350, and the sidewalls of the gate electrode 350 are formed over the substrate 100.

  Next, as shown in FIGS. 5A and 5B, a resist pattern (not shown) is formed on the substrate 100, and impurities of the second conductivity type are implanted into the substrate 100 using the resist pattern as a mask. Thereby, the first buried region 180 is formed. Thereafter, the resist pattern is removed.

  Thereafter, as shown in FIG. 1, a resist pattern is formed on the substrate 100, and impurities of the first conductivity type are implanted using the resist pattern as a mask. Thereby, the collector region 140, the emitter region 170, the high concentration impurity layer 340, the source region 360, and the drain region 370 are formed. Thereafter, the resist pattern is removed. Next, a resist pattern is formed on the substrate 100, and impurities of the second conductivity type are implanted using the resist pattern as a mask. Thereby, the high concentration base region 160 and the back gate electrode 380 are formed. Thereafter, the resist pattern is removed. Thereafter, silicide layers 145, 165, and 175 are formed. At this time, silicide layers 342, 374, and 384 are also formed in the field effect transistor.

  Next, the operation and effect of this embodiment will be described with reference to FIG. According to this embodiment, the bipolar transistor has the first buried region 180. The first buried region 180 is at least partially located between the emitter region 170 and the collector region 140 in plan view, and overlaps the edge of the emitter region 170 on the collector region 140 side. . The first buried region 180 does not overlap the entire surface of the emitter region 170.

In such a configuration, when a voltage V _ce is applied between the emitter region 170 and the collector region 140, holes and electrons are generated at a certain voltage. Holes and electrons are generated at the end of the base region 150 on the collector region 140 side (point P in FIG. 6), and holes and electrons increase due to the avalanche effect. The generated electrons flow toward the sink region 130 and the collector region 140, but the generated holes move toward the high concentration base region 160. For this reason, the potential of the base region 150 increases as it approaches the end portion on the collector region 140 side from the high concentration base region 160.

Here, when the first buried region 180 is not formed, the electric field concentrates on the end portion on the collector region 140 side, so that the base-emitter junction is turned on and the bipolar transistor starts to operate (Q in FIG. 6). point). For this reason, the collector current I _c is concentrated at the end of the base region 150 on the collector region 140 side, and destruction occurs when the amount of I _c becomes a constant value (point R). The point R is determined by the avalanche breakdown voltage between the base region 150 and the well 110.

On the other hand, when the first buried region 180 is formed, since the first buried region 180 has a high impurity concentration, the potential gradient in the first buried region 180 is relaxed. Accordingly, the base-emitter junction is turned on in the first buried region 180, and the bipolar transistor starts to operate (point Q in FIG. 6). For this reason, the collector current is dispersed in the first buried region 180 and is not concentrated on a specific portion. Therefore, the current amount I _c to thermal breakdown occurs is increased.

  Therefore, by forming the first buried region 180, the end of the base region 150 on the collector region 140 side is prevented from being destroyed when the bipolar transistor operates. Therefore, the withstand capability of the bipolar transistor is improved.

The distance w ₂ from the edge of the first buried region 180 on the collector region 140 side to the emitter region 170 is larger than the distance t from the lower end of the base region 150 to the lower end of the element isolation region 200. Therefore, after the bipolar transistor is turned on, the collector current flowing from the emitter region 170 flows in the depth direction instead of the lateral direction in FIG. 1A, that is, not in the end portion of the base region 150 but in the second buried region 120. It becomes easy. Therefore, the bipolar transistor can be further prevented from being destroyed at the end of the base region 150.

  The first buried region 180 is formed after the element isolation region 200 is formed. For this reason, the amount of heat applied to the substrate 100 after forming the first buried region 180 can be reduced, and the diffusion of the impurities forming the first buried region 180 by heat can be suppressed.

  In addition, since the lower end of the first embedded region 180 is located below the lower end of the base region 150, the lower end of the first embedded region 180 is compared to the case where the lower end of the first embedded region 180 is located above the lower end of the base region 150. Thus, the first buried region 180 is easily formed.

(Second Embodiment)
FIG. 7A and FIG. 7B are cross-sectional views showing the configuration of the semiconductor device according to the second embodiment, and correspond to FIG. 1A and FIG. 1B in the first embodiment. It is a figure to do. As shown in FIG. 7A, the semiconductor device according to the first embodiment except that the bipolar transistor has a low-concentration base region 152 of the second conductivity type (for example, p-type). The configuration is similar to that of a semiconductor device.

  The low-concentration base region 152 is located between the base region 150 and the collector region 140 in plan view and has a lower impurity concentration than the base region 150. In the example shown in this drawing, the low-concentration base region 152 is formed below the element isolation region 200 and connects the sink region 130 and the base region 150. The first buried region 180 is provided so as not to overlap the low concentration base region 152.

  The semiconductor device manufacturing method shown in FIG. 7 is the same as the semiconductor device manufacturing method according to the first embodiment, except that the low concentration base region 152 is formed after the step shown in FIG. It is the same. The low-concentration base region 152 is formed, for example, by forming a resist pattern on the substrate 100 and implanting a second conductivity type impurity into the substrate 100 using the resist pattern as a mask.

Next, the operation and effect of this embodiment will be described with reference to FIG. According to this embodiment, the same effect as that of the first embodiment can be obtained. Further, since the low-concentration base region 152 is formed, the potential gradient between the base region 150 and the collector region 140 is relaxed. Therefore, when went up voltage V _ce between the emitter region 170 and the collector region 140, a voltage V _ce necessary for holes and electrons are generated increases as compared with the first embodiment (FIG. P point of 8). Since the first buried region 180 is provided so as not to overlap the low concentration base region 152, the effect of the low concentration base region 152 is not hindered by the first buried region 180.

(Third embodiment)
FIGS. 9A and 9B are cross-sectional views showing the configuration of the semiconductor device according to the third embodiment, and correspond to FIGS. 7A and 7B in the second embodiment. It is a figure to do. FIG. 10 is a plan view of the bipolar transistor shown in FIG. In FIG. 10, the separation well 190 is not shown for the sake of explanation. FIG. 9A shows the AA ′ cross section of FIG. 9A and 10, this semiconductor device is the same as the semiconductor device according to the second embodiment except that the first buried region 180 is formed so as to surround the emitter region 170. It is the same composition. The semiconductor device manufacturing method according to the present embodiment is the same as the semiconductor device manufacturing method according to the second embodiment.

  The first buried region 180 is not formed in at least a part below the emitter region 170, and has a hollow portion 182 that overlaps the emitter region 170 in plan view. The first embedded region 180 has an inner peripheral edge overlapping the emitter region 170 in plan view. The first buried region 180 does not overlap the high concentration base region 160.

  Next, the operation and effect of this embodiment will be described with reference to FIG. According to this embodiment, the same effect as that of the second embodiment can be obtained. Further, since the first buried region 180 is formed so as to surround the emitter region 170, the collector current flowing from the emitter region 170 after the bipolar transistor is turned on passes through the hollow portion 182 instead of the lateral direction in FIG. This makes it easier to flow downward. For this reason, it is suppressed that a collector current concentrates on the specific part, especially the edge part by the side of the collector area | region 140 among the base areas 150. FIG. Therefore, the amount of current (point R) when the bipolar transistor breaks increases, and the withstand capability of the bipolar transistor increases.

(Fourth embodiment)
12A and 12B are cross-sectional views showing the configuration of the semiconductor device according to the fourth embodiment, and correspond to FIGS. 1A and 1B in the first embodiment. is doing. The semiconductor device according to the present embodiment is the same as the semiconductor device according to the first embodiment except for the configuration of a field effect transistor as a protected element.

  In this embodiment, the field effect transistor includes a well 310, a gate insulating film 352, a gate electrode 350, a first conductivity type drain region 370, a first conductivity type source region 360, as shown in FIG. An element isolation region 200 and a second conductivity type third buried region 390 are provided. The gate insulating film 352 and the gate electrode 350 are formed on the well 310. The drain region 370 is provided in the well 310. The source region 360 is formed in the well 310 and is positioned so as to sandwich the gate electrode 350 between the source region 360 and the drain region 370. A part of the element isolation region 200 separates the channel region located under the gate electrode 350 from the source region 360. The third buried region 390 is formed in the well 310 and has a higher impurity concentration than the well 310. The third buried region 390 is on the channel region side of the element isolation region 200 that separates the channel region and the source region 360 from at least the end of the source region 360 opposite to the gate electrode 350 side in plan view. It is formed over the edge part.

  The field effect transistor includes a source extension region 362, a drain extension region 372, and a back gate electrode 380. In addition, as in the first embodiment, a buried region 320, a sink region 330, and a high-concentration impurity layer 340 are formed on the substrate 100.

  In the method of manufacturing the semiconductor device according to this embodiment, the third buried region 390 is formed together with the first buried region 180 in the step of forming the first buried region 180, the low concentration shown in FIG. Except for the point that the impurity region 382 is not formed and the point that the source extension region 362 is formed in the step of forming the drain extension region 372, this is the same as the method for manufacturing the semiconductor device according to the first embodiment.

  According to this embodiment, the same effect as that of the first embodiment can be obtained. The field effect transistor shown in FIG. 12 operates as a parasitic bipolar transistor because the back gate electrode 380 operates as a base, the source region 360 operates as an emitter, and the drain region 370 operates as a collector. Sometimes. As a result of studies by the present inventors, it has been found that the parasitic bipolar transistor is easily turned on when the base resistance is high. In contrast, in the present embodiment, since the third buried region 390 is formed, the base resistance of the parasitic bipolar transistor can be lowered. For this reason, the parasitic bipolar transistor is difficult to turn on.

  In addition, since the first buried region 180 and the third buried region 390 can be formed in the same process, an increase in the number of manufacturing steps of the semiconductor device can be suppressed.

  In the second or third embodiment, the configuration of the field effect transistor as the protected element may be the same as that of this embodiment. Even if it does in this way, the effect similar to this embodiment can be acquired.

(Fifth embodiment)
FIG. 13A and FIG. 13B are cross-sectional views showing the configuration of the semiconductor device according to the fifth embodiment, and correspond to FIG. 1A and FIG. 1B in the first embodiment. is doing. In the semiconductor device according to the present embodiment, the element isolation region 200 is not formed between the high-concentration base region 160 and the emitter region 170 and is connected to each other by the silicide layer 175 and the lower end of the isolation well 190 is The configuration is the same as that of the semiconductor device according to the first embodiment except that the semiconductor substrate 102 is reached.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Note that the second to fourth embodiments may have the same configuration as that of the present embodiment.

(Sixth embodiment)
FIG. 14 is a cross-sectional view showing the configuration of the semiconductor device according to the sixth embodiment, which corresponds to FIG. 1A in the first embodiment. The semiconductor device according to this embodiment is different from the semiconductor device according to the first embodiment in the following points.

First, the substrate 100 does not have the epitaxial growth layer 104 but is formed of a semiconductor substrate. The bipolar transistor is formed on this semiconductor substrate. Further, the bipolar transistor does not have the second buried region 120, and has the first conductivity type low-concentration impurity layer 132 instead of the sink region 130 shown in FIG. The low concentration impurity layer 132 is shallower than the well 110.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

(Seventh embodiment)
FIG. 15 is a cross-sectional view showing the configuration of the semiconductor device according to the seventh embodiment. In this semiconductor device, the field effect transistor shown in FIG. 1B in the first embodiment is operated as a bipolar transistor. That is, the back gate electrode 380 and the second conductivity type low-concentration impurity region 382 function as a base region, the source region 360 functions as an emitter region, and the drain region 370 and the drain extension region 372 function as a collector region. The first buried region 180 is formed so that at least part of the low-concentration impurity region 382 is included. In the example shown in this drawing, the first buried region 180 is formed so as to surround the back gate electrode 380 in plan view.

Although not shown, the semiconductor device also has a field effect transistor as a protected element in this embodiment. The configuration of this field effect transistor is the same as that of the first embodiment.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

(Eighth embodiment)
FIG. 16A and FIG. 16B are cross-sectional views showing the configuration of the semiconductor device according to the eighth embodiment, and correspond to FIG. 9A and FIG. 9B in the third embodiment. It is a figure to do. FIG. 17 is a plan view of the bipolar transistor shown in FIG. In FIG. 17, the separation well 190 is not shown for the sake of explanation. FIG. 16A shows the AA ′ cross section of FIG. This semiconductor device has a double base structure in which a high concentration base region 160 is provided on both sides of an emitter region 170 as shown in FIGS.

  In the present embodiment, the first buried region 180 is formed so as to surround the emitter region 170. The first buried region 180 is not formed at least at a part below the emitter region 170 and has a hollow portion 182 that overlaps the emitter region 170 in plan view. In plan view, the first embedded region 180 has an inner peripheral edge overlapping the emitter region 170 and an outer peripheral edge overlapping the high-concentration base region 160.

Except for the points described above, the semiconductor device according to the present embodiment is just like the third embodiment.
According to this embodiment, the same effect as that of the third embodiment can be obtained.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable. For example, the present invention can be applied to a double emitter structure in which the emitter region 170 is provided on both sides of the high concentration base region 160. In the case of the double emitter structure, the first buried region 180 overlaps the edge of the emitter region 170 on the collector region 140 side and does not overlap the entire surface of the emitter region 170 every two emitter regions 170. Formed as follows.

Example 1
In the semiconductor device according to each of the second and third embodiments, it was simulated how the collector current of the bipolar transistor flows when the voltage between the emitter and the collector is increased. 18 to 20, (a) shows a bipolar transistor according to a comparative example. This bipolar transistor is obtained by removing the first buried region from the bipolar transistor according to the second embodiment. (B) and (c) show bipolar transistors according to the second and third embodiments, respectively.

  FIG. 18 shows the impurity concentration distribution of the bipolar transistor used in the simulation. Note that t = 1 μm shown in FIG.

FIG. 19 shows the collector current flow immediately after the bipolar transistor is turned on (collector current = 1 × 10 ⁻³ A). In this figure, the lighter the color, the higher the current density. As shown in FIG. 19A, in the bipolar transistor according to the comparative example, most of the collector current flows in the right direction in the figure. On the other hand, as shown in FIGS. 19B and 19C, in the bipolar transistors according to the second and third embodiments, the collector current is not only in the right direction but also in the downward direction (or the left direction). Is also flowing.

FIG. 20 shows the collector current flow when the collector current becomes sufficiently large (1 × 10 ⁻² A). In this figure, the lighter the color, the higher the current density. As shown in FIG. 20C, in the third embodiment, there are few portions where the collector current density is high. This indicates that the collector current is not concentrated at a specific location but is distributed.

(Example 2)
A bipolar transistor according to the third embodiment was manufactured, and a TLP (Transmission Line Pulse) test, that is, a test for examining an ESD tolerance by applying a high current pulse was performed (Example). In addition, a bipolar transistor excluding the first buried region 180 from the third embodiment was manufactured, and a TLP test was performed (comparative example). In each example, measurement was performed at two locations in the wafer.

  FIG. 21 is a graph showing the results of the TLP test according to the example (solid line) and the comparative example (dotted line). This figure shows the relationship between the applied voltage (Voltage) between the emitter region 170 and the collector region 140 and the collector current (current flowing from the emitter region 170 to the collector region 140) in the embodiment at the first measurement point. “■” and a solid line indicate the second measurement point with “♦” and a solid line. Further, this figure shows the relationship between the applied voltage and the collector current in the comparative example by “□” and a dotted line at the first measurement point, and “◇” and a dotted line at the second measurement point. In this figure, according to a general display method of TLP measurement results, simultaneously with the IV curve at the time of TLP application, the leak current measurement results performed after each TLP application are simultaneously displayed. As indicated by the dotted arrows in the graph, the bipolar transistor according to the example has an increased amount of current required for breakdown compared to the bipolar transistor according to the comparative example. This indicates that the ESD tolerance of the bipolar transistor according to the example is increased.

100 substrate 102 semiconductor substrate 104 epitaxial growth layer 110 well 120 second buried region 130 sink region 132 low concentration impurity layer 140 collector region 145 silicide layer 150 base region 152 low concentration base region 160 high concentration base region 165 silicide layer 170 emitter region 175 Silicide layer 180 First buried region 182 Hollow portion 190 Isolation well 200 Element isolation region 310 Well 320 Embedded region 330 Sink region 340 High concentration impurity layer 342 Silicide layer 350 Gate electrode 352 Gate insulating film 360 Source region 362 Source extension region 370 Drain region 372 Drain extension region 374 Silicide layer 380 Back gate electrode 382 Low-concentration impurity region 384 Silicide layer 390 Third buried region

Claims (10)

A first conductivity type well formed on the substrate;
A second conductivity type base region formed in the well;
A high-concentration base region of a second conductivity type formed in a part of a surface layer of the base region and having an impurity concentration higher than that of the base region;
An emitter region of a first conductivity type formed in the base region and shallower than the base region;
A first conductivity type collector region formed in the well and located outside the base region;
A first conductivity region of a second conductivity type, at least part of which is located in the base region and having a higher impurity concentration than the base region;
With
In plan view, the first embedded region is
At least a portion is located between the emitter region and the collector region;
A semiconductor device that overlaps at least one side of the edge of the emitter region and does not overlap the entire surface of the emitter region. The semiconductor device according to claim 1,
A semiconductor device comprising a second buried region of a first conductivity type formed on the entire lower surface of the well and connected to the collector region. The semiconductor device according to claim 1 or 2,
A semiconductor device in which a lower end of the first buried region is located below a lower end of the base region. In the semiconductor device as described in any one of Claims 1-3,
An element isolation region formed on the substrate;
A portion of the base region is located below the element isolation region;
In the planar view, the first buried region is a semiconductor device in which the distance from the collector region side edge to the emitter region is larger than the distance from the lower end of the base region to the lower end of the element isolation region. In the semiconductor device according to claim 1,
A semiconductor device comprising a second conductivity type second base layer located between the base region and the collector region in a plan view and having an impurity concentration lower than that of the base region. In the semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the first buried region is formed so as to surround the emitter region in plan view. In the semiconductor device according to claim 1,
A field effect transistor formed on the substrate;
The transistor is
A second conductivity type transistor well formed on the substrate surface;
A gate electrode formed on the transistor well;
A drain region of a first conductivity type provided in the transistor well;
A source region of a first conductivity type formed in the transistor well and positioned so as to sandwich the gate electrode with the drain region;
An element isolation region that separates the channel region located under the gate electrode and the source region;
Have
In the transistor well, a third conductivity type third buried region having an impurity concentration higher than that of the transistor well is at least from the end of the source region opposite to the gate electrode side in a plan view. A semiconductor device formed over the channel region side end of the element isolation region. Forming a first conductivity type well on a substrate;
Forming a second conductivity type base region located in the well on the substrate;
A second conductivity type high-concentration base region having a higher impurity concentration than the base region and located in a part of a surface layer of the base region on the substrate, and located in the base region from the base region Forming a shallow first conductivity type emitter region and a first conductivity type collector region located in the well and outside the base region, respectively.
With
After the step of forming the well, the method includes a step of forming a first conductive region of a second conductivity type at least partially located in the base region and having a higher impurity concentration than the base region,
In plan view, the first embedded region is
At least a portion is located between the emitter region and the collector region;
A method of manufacturing a semiconductor device that overlaps at least one side of the edge of the emitter region and does not overlap the entire surface of the emitter region. In the manufacturing method of the semiconductor device according to claim 8,
A step of forming an element isolation region between the step of forming the well and the step of forming the base region;
The step of forming the first buried region is a method of manufacturing a semiconductor device performed after the step of forming the element isolation region. In the manufacturing method of the semiconductor device according to claim 9,
The semiconductor device further includes a field effect transistor formed on a substrate,
The transistor is
A second conductivity type transistor well formed on the substrate surface;
A gate electrode formed on the transistor well;
A drain region of a first conductivity type provided in the transistor well;
A source region of a first conductivity type formed in the transistor well and positioned so as to sandwich the gate electrode with the drain region;
An element isolation region that separates the channel region located under the gate electrode and the source region;
Have
In the transistor well, a third conductivity type third buried region having an impurity concentration higher than that of the transistor well is at least from the end of the source region opposite to the gate electrode side in a plan view. Formed over the channel region side end of the element isolation region,
A method of manufacturing a semiconductor device, wherein, in the step of forming the first buried region, the third buried region is formed together with the first buried region.

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