JP2011030360A - Overcurrent detection circuit - Google Patents

Abstract

An overcurrent detection circuit capable of detecting an overcurrent with high accuracy while reducing the number of components is provided.
An overcurrent detection circuit is an overcurrent detection circuit that detects an overcurrent generated in a control transistor that controls a current flowing through a load, and includes a bias current generation circuit that generates a bias current and a transistor. A reference voltage circuit that outputs a reference voltage based on the bias current and the on-resistance of the transistor, and a detection voltage that is determined based on a voltage generated between an input electrode and an output electrode of the control transistor when the control transistor is turned on And a detection circuit that compares the reference voltage and detects whether a current flowing through the control transistor exceeds a predetermined current value, and the control transistor and the transistor are formed in the same integrated circuit Is done.
[Selection] Figure 1

Description

  The present invention relates to an overcurrent detection circuit.

  In general, a load driving circuit is provided with an overcurrent detection circuit that detects whether or not an overcurrent has occurred in a load or a transistor that controls the load current (see, for example, Patent Document 1). FIG. 6 shows an example of the switching power supply circuit 200 for generating a desired output voltage Vout from the input voltage Vin.

  When the comparison signal Vc from the comparator 304 is at a low level (hereinafter referred to as L level), the drive circuit 300 drives the PMOS transistor 301 such that the feedback voltage Vfb corresponding to the output voltage Vout matches the reference voltage Vref1. The drive circuit 300 stops driving the PMOS transistor 301 when the comparison signal Vc is at a high level (hereinafter, H level).

  The voltage detection circuit 302 detects a voltage Vr at a node to which the high-precision resistor 400 for detecting current and the PMOS transistor 301 are connected, and outputs the detected voltage Vr to the comparator 304. The voltage detection circuit 302 outputs the voltage Vin as the voltage Vr when the PMOS transistor 301 is off. On the other hand, when the PMOS transistor 301 is turned on, the voltage detection circuit 302 has a voltage Vr = Vin−R × determined based on the input voltage Vin, the resistance value R of the resistor 400, and the output current Iout flowing through the PMOS transistor 301. Iout is output.

  The reference voltage circuit 303 is, for example, a bad gap circuit, and generates an accurate reference voltage Vref2 that serves as a reference for detecting whether or not the output current Iout is an overcurrent. Here, for example, when the output current Iout is an overcurrent at the current IA, the reference voltage Vref2 is at a predetermined level, so that the resistance value R of the resistor 400 becomes R = (Vin−Vref2) / IA. Just choose.

  The comparator 304 compares the voltage Vr output from the voltage detection circuit 302 with the reference voltage Vref2, and detects whether or not an overcurrent has occurred in the control transistor 301. When the output current Iout is smaller than the limiter current of the current value IA, the voltage Vr becomes higher than the voltage Vref2. Therefore, the comparator 304 outputs an L-level comparison signal Vc indicating that no overcurrent has occurred to the drive circuit 300. On the other hand, when the output current Iout is larger than the limiter current, the voltage Vr becomes lower than the voltage Vref2. Therefore, the comparator 304 outputs an H level comparison signal Vc indicating that an overcurrent has occurred to the drive circuit 300. As a result, the driving of the PMOS transistor 301 is stopped. Therefore, an overcurrent does not continue to flow through the PMOS transistor 301.

JP 2002-84744 A

  Since the switching power supply circuit 200 described above uses the resistor 400 with high accuracy for current detection, it is possible to detect whether overcurrent is generated in the PMOS transistor 301 with high accuracy. However, the accurate resistor 400 cannot generally be realized by an integrated circuit. Therefore, for example, when the driving circuit 300, the PMOS transistor 301, the voltage detection circuit 302, and the like are realized by an integrated circuit, the resistor 400 must be provided as an external component. Therefore, for example, instead of the resistor 400, the on-resistance of the PMOS transistor 301 may be used as a current detection resistor. However, generally, the resistance value of the on-resistance of the PMOS transistor 301 varies greatly due to manufacturing variations and the like. For this reason, it is difficult to accurately detect whether the current flowing through the PMOS transistor 301 is an overcurrent using the on-resistance of the PMOS transistor 301.

  The present invention has been made in view of the above problems, and an object thereof is to provide an overcurrent detection circuit capable of detecting an overcurrent with high accuracy while reducing the number of components.

  In order to achieve the above object, an overcurrent detection circuit according to one aspect of the present invention is an overcurrent detection circuit that detects an overcurrent generated in a control transistor that controls a current flowing through a load, and generates a bias current. A reference voltage circuit including a bias current generation circuit and a transistor, and outputting a reference voltage based on the bias current and an on-resistance of the transistor; an input electrode and an output electrode of the control transistor when the control transistor is turned on; A detection circuit configured to compare a detection voltage determined based on a voltage generated between the reference voltage and the reference voltage to detect whether or not a current flowing through the control transistor exceeds a predetermined current value. And the transistor are formed in the same integrated circuit.

  It is possible to provide an overcurrent detection circuit capable of detecting an overcurrent with high accuracy while reducing the number of parts.

It is a figure which shows the structure of the switching power supply circuit 10 which is one Embodiment of this invention. 4 is a timing chart for explaining operations of a control circuit 32 and a drive circuit 33. 2 is a diagram showing the configuration of a reference current circuit 90 and a reference voltage circuit 91. FIG. It is a flowchart which shows an example of the trimming process of reference voltage Vref3. 3 is a timing chart for explaining the operation of the switching power supply circuit 10. 2 is a diagram illustrating a configuration of a switching power supply circuit 200. FIG.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

  FIG. 1 is a diagram showing a configuration of a switching power supply circuit 10 according to an embodiment of the present invention. The switching power supply circuit 10 is a circuit for generating a desired output voltage Vout from an input voltage Vin, for example, and includes a power supply IC 20, a diode 21, an inductor 22, capacitors 23 to 25, and resistors 26 to 29. Yes.

  The power supply IC 20 includes an NMOS transistor 30, a bootstrap power supply circuit 31, a control circuit 32, a drive circuit 33, a voltage detection circuit 34, and an overcurrent detection circuit 35. The power supply IC 20 is an integrated circuit including a terminal BC, a terminal IN, a terminal SW, a terminal RC, a terminal FB, and a terminal IB. Then, the power supply IC 20 controls the switching of the NMOS transistor 30 so that the voltage Vfb applied to the terminal FB becomes a predetermined level, and generates the output voltage Vout of the target level.

  The diode 21 has an anode grounded and a cathode connected to the terminal SW. The inductor 22 has one end connected to the terminal SW and the other end connected to one end of the capacitor 23. The other end of the capacitor 23 is grounded, and the voltage charged in the capacitor 23 is the output voltage Vout. For this reason, the diode 21, the inductor 22, and the capacitor 23 together with the NMOS transistor 30 constitute a so-called step-down chopper circuit. When the NMOS transistor 30 is turned on, the capacitor 23 is charged and the output voltage Vout increases. Thereafter, when the NMOS transistor 30 is turned off, the energy stored in the inductor 22 is released in a loop constituted by the diode 21, the inductor 22, and the capacitor 23. For this reason, the capacitor 23 is discharged and the output voltage Vout decreases.

  The capacitor 24 has one end connected to the terminal BC and the other end connected to the terminal SW. The capacitor 24 is charged when a voltage Vreg of a bootstrap power supply circuit 32 described later is applied to the terminal BC. A bootstrap voltage Vbt is generated at both ends of the capacitor 24. The bootstrap voltage Vbt is a voltage used to turn on the NMOS transistors 30 and 83. For example, it is assumed that the voltage Vsw of the terminal SW is 0V as an initial state. In this case, if a voltage higher than the threshold voltage Vth (for example, 2 V) is applied to the gate of the NMOS transistor 30, the NMOS transistor 30 is turned on. However, when the NMOS transistor 30 is turned on, the voltage Vsw at the terminal SW approaches the input voltage Vin (for example, 12 V). Therefore, in order to keep the NMOS transistor 30 on, a voltage higher than the input voltage Vin is applied to the gate of the NMOS transistor 30. Need to be applied. Therefore, the bootstrap voltage Vbt that is, for example, about 5 V higher than the voltage Vsw of the terminal SW is generated using the voltage Vreg. Then, the drive circuit 33 that controls the switching of the NMOS transistor 30 is operated with the bootstrap voltage Vbt. As a result, even when the voltage Vsw approaches the input voltage Vin, the NMOS transistor 30 can be turned on. The NMOS transistor 83 is the same as the NMOS transistor 30.

  The resistor 26 and the resistor 27 generate a feedback voltage Vfb obtained by dividing the output voltage Vout by the resistance ratio of the resistors 26 and 27.

  In the NMOS transistor 30 (control transistor), the input voltage Vin is applied to the drain (input electrode) via the terminal IN, the source (output electrode) is connected to the terminal SW, and the output signal Vdr1 of the drive circuit 33 is input to the gate. Has been. Therefore, when the difference between the voltage level of the output signal Vdr1 and the voltage Vsw of the terminal SW becomes larger than the threshold voltage Vth of the NMOS transistor 30, the NMOS transistor 30 is turned on. In the present embodiment, the actual on-resistance when the NMOS transistor 30 is turned on is Ron1.

  The bootstrap power supply generation circuit 31 includes an internal power supply circuit 40 and a diode 41. For example, the internal power supply circuit 40 generates a voltage Vreg of a predetermined level from the input voltage Vin. In the diode 41, the voltage Vreg is applied to the anode, and the cathode is connected to the terminal BC.

  Here, the voltage Vreg is 5 V, the voltage Vin is 12 V, the forward voltage Vf of the diodes 21 and 61 is 0.4 V, and the bootstrap voltage Vbt generated at both ends of the capacitor 24 is considered. When the NMOS transistor 30 is off and a current flows through a loop constituted by the diode 21, the inductor 22, and the capacitor 23, the voltage Vsw at the terminal SW is −0.4V. The voltage Vbc at the terminal BC is 4.6 V, which is lower than the voltage Vreg by 0.4 V, which is the forward voltage Vf of the diode 41. Therefore, the bootstrap voltage Vbt is 4.6-(− 0.4) = 5V. Thereafter, the NMOS transistor 30 is turned on, and the voltage level of the terminal SW rises. When the voltage Vsw rises to, for example, 11V, the voltage Vbc at the terminal BC becomes 16V obtained by adding the bootstrap voltage Vbt = 5V to 11V. For this reason, 16V is applied to the drive circuit 33 and the voltage detection circuit 34 as the voltage on the power supply side, and 11V is applied as the voltage on the ground side. Even if the voltage Vbc at the terminal BC is higher than the voltage Vreg, the current does not flow backward from the terminal BC toward the terminal REG because the diode 41 is provided.

  The control circuit 32 generates an output signal Vls for making the feedback voltage Vfb coincide with the reference voltage Vref1. Specifically, when the comparison signal Vc of the comparator 92 is at the L level, the control circuit 32 generates the output signal Vls corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref1. Further, when the input comparison signal Vc is at H level, the control circuit 32 outputs an L level output signal Vls. The control circuit 32 includes a reference voltage circuit 50, an error amplification circuit 51, an oscillation circuit 52, a comparator 53, a clock generation circuit 54, an inverter 55, an AND circuit 56, a D flip-flop 57, and a level shift (LS) circuit 58. Composed.

The reference voltage circuit 50 is a circuit that generates a reference voltage Vref1 having a predetermined level that does not depend on temperature, such as a band gap voltage.
The error amplification circuit 51 is a circuit that amplifies the difference between the reference voltage Vref1 and the feedback voltage Vfb1. A phase compensation capacitor 25 and a resistor 28 are connected between the output of the error amplifier circuit 51 and the ground GND via a terminal RC. Note that a voltage at a node where the output of the error amplifier circuit 51 and the terminal RC are connected is a voltage Ve.
The oscillation circuit 52 outputs a sawtooth oscillation signal Vosc having a predetermined period.

  The comparator 53 compares the voltage Ve and the oscillation signal Vosc and outputs a PWM signal Vpwm. Here, the voltage Ve is input to the non-inverting input terminal of the comparator 53, and the oscillation signal Vosc is input to the inverting input terminal of the comparator 33. Therefore, when the level of the oscillation signal Vosc becomes lower than the level of the voltage Ve, the PWM signal Vpwm becomes the H level, and when the level of the oscillation signal Vosc becomes higher than the level of the voltage Ve, the PWM signal Vpwm becomes the L level. In the present embodiment, the period occupied by the H level in one cycle of the PWM signal Vpwm is defined as the duty ratio of the PWM signal Vpwm.

  The clock generation circuit 54 outputs a clock signal Vck that becomes H level at a timing when the oscillation signal Vosc changes from falling to rising.

  Inverter 55 inverts the logic level of comparison signal Vc and outputs the result to AND circuit 56. For example, when the comparison signal Vc is L level, the output from the inverter 55 is H level. In this case, the output of the AND circuit 56 changes based on the PWM signal Vpwm. On the other hand, when comparison signal Vc is at H level, the output of inverter 55 is at L level. In this case, the output of the AND circuit 56 is also at the L level.

  The D flip-flop 57 outputs the PWM signal Vpwm from the Q output in synchronization with the clock signal Vck when the signal input to the reset is at the H level. Specifically, when the PWM signal Vpwm is at the H level at the rising edge of the clock signal Vck, the D flip-flop 57 sets the output signal Vq from the Q output to the H level. On the other hand, when the PWM signal Vpwm is at the L level at the rising edge of the clock signal Vck, the D flip-flop 57 sets the output signal Vq to the L level. The D flip-flop 57 is reset when the output from the AND circuit 56 is L level, and sets the output signal Vq to L level.

  The level shift circuit 58 is a circuit that converts the logic level of the output signal Vq into a logic level that can be determined by the drive circuit 33 and the voltage detection circuit 34. The level shift circuit 58 outputs an output signal Vls.

The drive circuit 33 is a circuit that drives the NMOS transistor 30 based on the output signal Vls, and includes inverters 70 and 71.
Inverters 70 and 71 operate as a buffer for driving NMOS transistor 30 based on output signal Vls. Further, a voltage Vbc (= Vbt + Vsw) is applied to the inverters 70 and 71 as a power supply side voltage, and a voltage Vsw is applied as a ground side voltage. Therefore, for example, when the output signal Vls becomes H level, the level of the drive signal Vdr1, which is the output of the inverter 71, becomes the voltage Vbc (H level). On the other hand, when the output signal Vbt becomes L level, the level of the drive signal Vdr1 becomes voltage Vsw (L level). In the present embodiment, the voltage Vreg for generating the bootstrap voltage Vbt is a voltage that is sufficiently larger than the threshold voltage Vth of the NMOS transistor 30. Therefore, the drive circuit 33 turns on the NMOS transistor 30 based on the H level output signal Vls, and turns off the NMOS transistor based on the L level output signal Vls.

  Here, an example of the operation of the control circuit 32 and the drive circuit 33 when the desired output voltage Vout is generated will be described with reference to FIG. Here, it is assumed that the level of the comparison signal Vc is L level.

  First, when the oscillation signal Vosc becomes lower than the voltage Ve at time T0, the PWM signal Vpwm becomes H level. When the clock signal Vck becomes H level at the time T1 when the oscillation signal Vosc rises, the output signal Vq becomes H level. The output signal Vq is level-shifted and then input to the drive circuit 33. For this reason, the drive signal Vdr1 also becomes H level, and the NMOS transistor 30 is turned on.

  Next, when the oscillation signal Vosc becomes higher than the voltage Ve at time T2, the PWM signal Vpwm becomes L level. As a result, the D flip-flop 57 is reset and the output signal Vq also becomes L level. Then, the drive circuit 33 turns off the NMOS transistor 30 based on the level-shifted L level output signal Vls. Further, when the oscillation signal Vosc becomes lower than the voltage Ve at the time T3, the PWM signal Vpwm becomes the H level similarly to the time T0. After time T3, the operations from time T0 to time T3 are repeated.

  Therefore, when the desired output voltage Vout is generated, the drive circuit 33 switches the NMOS transistor 30 with the drive signal Vdr1 having a predetermined duty ratio. Note that when the output voltage Vout rises due to, for example, load fluctuation or the like while the desired output voltage Vout is generated, the feedback voltage Vfb also rises. As a result, the voltage Ve decreases and the duty ratio of the drive signal Vdr1 also decreases. Accordingly, the increased output voltage Vout decreases to a desired level. On the other hand, when the output voltage Vout decreases, the feedback voltage Vfb also decreases. As a result, the voltage Ve rises and the duty ratio of the drive signal Vdr1 increases. Therefore, the lowered output voltage Vout rises to a desired level. Thus, when the comparison signal Vc is at the L level, the control circuit 32 and the drive circuit 33 control the switching of the NMOS transistor 30 so that the desired output voltage Vout is output. As described above, when the comparison signal Vc is at the H level, the output signal Vq is at the L level. Therefore, in this case, the switching of the NMOS transistor 30 is stopped regardless of the level of the feedback voltage Vfb or the like.

  The voltage detection circuit 34 is a circuit that detects the voltage Vsw when the NMOS transistor 30 is turned on, and includes a rise delay circuit 80, inverters 81 and 82, an NMOS transistor 83, and a resistor 84. When the voltage Vsw is used as the input voltage Vin, the actual on-resistance Ron1 of the NMOS transistor 30, and the output current Iout flowing through the NMOS transistor 30, Vsw = Vin−Ron1 × Iout.

  The rise delay circuit 80 delays the rise of the output signal Vls by a predetermined period and outputs it. Specifically, the rise of the output signal Vls is delayed so that the NMOS transistor 83 is turned on after the NMOS transistor 30 is turned on.

  Inverters 81 and 82 constitute a buffer for driving NMOS transistor 83. In addition, a voltage Vbc is applied to the inverters 81 and 82 as a power supply side voltage, and a voltage Vsw is applied as a ground side voltage. Therefore, the inverters 81 and 82 turn on the NMOS transistor 83 when an H level signal is output from the rising delay circuit 80, and turn off the NMOS transistor 83 when an L level signal is output. Note that the output of the inverter 82 is a drive signal Vdr2.

  The source of the NMOS transistor 83 is connected to the terminal SW, and the drain is connected to one end of the resistor 84. Since the other end of the resistor 84 is connected to the terminal IN, the NMOS transistor 83 and the resistor 84 form an inverter. In addition, the resistance value R1 of the resistor 84 and the actual on-resistance Ron2 of the NMOS transistor 83 are designed to be sufficiently larger than the on-resistance Ron1 (R1, Ron2 >> Ron1). For this reason, when both the NMOS transistor 30 and the NMOS transistor 83 are turned on, the impedance between the terminal IN and the terminal SW is substantially equal to the on-resistance Ron1. Therefore, when both the NMOS transistor 30 and the NMOS transistor 83 are turned on, the voltage generated between the terminal IN and the terminal SW is determined based on Ron1 × Iout. Further, in this embodiment, the resistance value R1 of the resistor 84 is designed to be sufficiently larger than the actual on-resistance Ron2 of the NMOS transistor 83 (R1 >> Ron2). Therefore, when the NMOS transistor 83 is turned on, the voltage Vsw is output as the voltage Vd.

  The overcurrent detection circuit 35 is a circuit that detects whether or not the output current Iout flowing through the NMOS transistor 30 is an overcurrent, and includes a reference current generation circuit 90, a reference voltage circuit 91, and a comparator 92. .

  The reference current generation circuit 90 is a circuit that generates a reference current Iref corresponding to the resistance value of the resistor 29 connected via the terminal IB. As shown in FIG. 3, the reference current generation circuit 90 includes a reference voltage circuit 100, an error amplification circuit 101, an NPN transistor 102, and PNP transistors 103 and 104.

The reference voltage circuit 100 is a circuit that generates a reference voltage Vref2 having a predetermined level independent of temperature, such as a band gap voltage.
The base and emitter of the NPN transistor 102 are connected to the output and inverting input of the error amplifier circuit 101, respectively. Therefore, the error amplifier circuit 101 controls the voltage applied to the base of the NPN transistor 102 so that the voltage of the inverting input matches the reference voltage Vref2 applied to the non-inverting input. As a result, the voltage applied to the resistor 25 having the resistance value R2 becomes equal to the reference voltage Vref2, and the current having the current value Vref2 / R2 flows through the resistor 25.
The PNP transistor 103 and the PNP transistor 104 constitute a current mirror circuit. The PNP transistors 103 and 104 are transistors of the same size. For this reason, the reference current Iref = Vref2 / R2 generated by the PNP transistor 104 is obtained. Note that the voltage Vreg is applied to the power supply side voltage of the PNP transistors 103 and 104 of the present embodiment.

  The reference voltage circuit 91 generates a reference voltage Vref3 according to the current value at the time of overcurrent and the actual on-resistance Ron1 of the NMOS transistor 30. The reference voltage circuit 91 includes NPN transistors 110 to 115, resistors 120 to 125, trimming elements 130 to 133, terminals 140 to 143, and an NMOS transistor 150.

  A reference current Iref is supplied to the diode-connected NPN transistor 110. For this reason, a voltage corresponding to the reference current Iref is generated between the base and emitter of the NPN transistor 110. The resistor 120 is an emitter resistance of the NPN transistor 110. In addition, resistors 121 to 125 described later also correspond to the emitter resistors of the NPN transistors 111 to 115, respectively.

  Since the base of the NPN transistor 111 is connected to the base of the NPN transistor 110, the NPN transistor 110 and the NPN transistor 111 constitute a current mirror circuit. Therefore, a current I1 corresponding to the reference current Iref flows through the NPN transistor 111.

  Since the base of the NPN transistor 112 is connected to the base of the NPN transistor 110, the NPN transistor 110 and the NPN transistor 112 constitute a current mirror circuit. A resistor 122 and a trimming element 130 are connected in series to the emitter of the NPN transistor 112. The trimming element 130 changes from an open state to a short circuit state when a predetermined voltage is applied between the electrodes. The trimming element 130 can be realized by, for example, a Zener diode. Therefore, when the trimming element 130 is in a short circuit state, the current I2 flowing through the NPN transistor 112 has a current value corresponding to the reference current Iref. On the other hand, when the trimming element 130 is open, the current I2 is zero. The terminals 140 to 143 are terminals used when trimming is adjusted.

  Each of the NPN transistor 113 to NPN transistor 115 forms a current mirror circuit with the NPN transistor 110 in the same manner as the NPN transistor 112. Resistors 123 to 125 and trimming elements 131 to 133 are connected in series to the emitters of the NPN transistor 113 to NPN transistor 115. Therefore, when the trimming element 131 is in a short circuit state, the current I3 flowing through the NPN transistor 113 has a current value corresponding to the reference current Iref, and when the trimming element 131 is in an open state, the current I3 is zero. When the trimming element 132 is in a short circuit state, the current I4 flowing through the NPN transistor 114 has a current value corresponding to the reference current Iref, and when the trimming element 132 is in an open state, the current I4 is zero. Furthermore, when the trimming element 133 is in a short circuit state, the current I5 flowing through the NPN transistor 115 has a current value corresponding to the reference current Iref, and when the trimming element 133 is in an open state, the current I5 is zero.

  Thus, each of the NPN transistors 112 to 115 can generate currents I2 to I5 corresponding to the reference current Iref. Each of the collectors of the NPN transistors 111 to 115 is connected to the NMOS transistor 150. Therefore, the bias current Ib flowing through the NMOS transistor 150 is the sum of the currents I1 to I5. For this reason, the current value of the bias current Ib is determined based on the state of the trimming elements 130 to 133. In the present embodiment, the current values of the currents I1 to I5 are, for example, NPN transistors 110 to 115 such that I1: I2: I3: I4: I5 = 16: 8: 4: 2: 1. It is assumed that the size of is determined. The NPN transistors 110 to 115 and the resistors 120 to 125 correspond to a bias current circuit, and the trimming elements 130 to 133 correspond to a current adjustment circuit. Each of the NPN transistor 112 and the resistor 122, the NPN transistor 113 and the resistor 123, the NPN transistor 114 and the resistor 124, and the NPN transistor 115 and the resistor 125 correspond to a constant current circuit.

  In the NMOS transistor 150, the voltage Vbc of the terminal BC is applied to the gate, the input voltage Vin is applied to the drain, and the source is connected to the collectors of the NPN transistors 111 to 115. As described above, the level of the voltage Vbc changes depending on whether the NMOS transistor 30 is turned on or off. For example, when the NMOS transistor 30 is turned off, the voltage Vbc becomes lower than the input voltage Vin. Therefore, the NMOS transistor 150 is also turned off. On the other hand, when the NMOS transistor 30 is turned on and the voltage Vbc becomes higher than the input voltage Vin, the NMOS transistor 150 is turned on. As a result, the bias current Ib flows through the NMOS transistor 150. In the present embodiment, the source voltage of the NMOS transistor 150 is set to the reference voltage Vref3. For this reason, when the NMOS transistor 150 is turned off, the reference voltage Vref3 becomes approximately 0V, and when the NMOS transistor 150 is turned on, the reference voltage Vref3 becomes Vref3 = Vin−Ron3 × Ib. Here, the actual on-resistance of the NMOS transistor 150 is Ron3. The source of the NMOS transistor 150 is provided with a terminal 144 used for adjusting the reference voltage Vref3. The NMOS transistor 150 and the NMOS transistor 30 are the same type of transistor. Here, the same type of transistors refers to transistors that are designed to have the same temperature characteristics and voltage characteristics, and are, for example, transistors manufactured by the same manufacturing process.

  The comparator 92 (detection circuit) compares the levels of the reference voltage Vref3 and the voltage Vd (detection voltage) to detect whether or not an overcurrent has occurred. Specifically, when the voltage Vd is higher than the reference voltage Vref3, the comparator 92 outputs an L level comparison signal Vp indicating that no overcurrent has occurred. On the other hand, when the voltage Vd is lower than the reference voltage Vref3, the comparator 92 outputs an H level comparison signal Vp indicating that an overcurrent has occurred.

== Setting of the reference voltage Vref3 ==
Here, trimming of the reference voltage circuit 91 will be described. The trimming of the reference voltage circuit 91 is executed by a semiconductor test device (not shown) or the like before the power supply IC 20 is shipped, for example. Here, the upper limit of the current value of the NMOS transistor 30 is defined as a current value IA, and the current of the current value IA is defined as a limiter current. For this reason, when the current of the NMOS transistor 30 exceeds the limiter current, an overcurrent is generated in the NMOS transistor 30.

  FIG. 4 is an example of a trimming process executed by the semiconductor test apparatus. First, the semiconductor test apparatus activates the power supply IC 20 and applies a predetermined voltage between the terminal IN and the terminal SW with the NMOS transistor 30 turned on. Then, the current flowing between the terminal IN and the terminal SW is measured, and the actual on-resistance Ron1 of the NMOS transistor 30 is calculated (S100). Further, the semiconductor test apparatus calculates a target value for the reference voltage Vref3 based on the current value IA and the actual on-resistance Ron1. Specifically, Vin−IA × Ron1, which is the level of the voltage Vsw when the current IA actually flows through the NMOS transistor 30, is calculated as a target value (S101). Then, the semiconductor test apparatus sets the trimming elements 130 to 133 so that the value of the reference voltage Vref3 becomes the target value calculated in the process 101 (S102). Specifically, the semiconductor test apparatus sequentially changes the state of each of the terminals 140 to 143 to the ground state or the open state, and changes the bias current Ib. The semiconductor test apparatus holds the state of the terminals 140 to 143 when the value of the reference voltage Vref3 is closest to the target value. Thereafter, the semiconductor test apparatus performs trimming so that the held terminals 140 to 143 are realized by the trimming elements 130 to 133.

  At this time, the semiconductor test apparatus applies the same voltage to the gate (terminal BC) and drain (terminal IN) of the NMOS transistor 150 as when the power supply IC 20 actually operates. For this reason, the NMOS transistor 150 has the same on-resistance as when the power supply IC 20 operates. Further, as described above, the reference voltage Vref3 is Vref3 = Vin−Ib × Ron3. Therefore, in practice, the value of the bias current Ib is adjusted so that the value of Ib × Ron3 is closest to the value of IA × Ron1.

  For example, when the current value is determined to be optimal so that the bias current Ib = I1 + I2 in the process 102, the semiconductor test apparatus changes only the trimming element 130 from the open state to the short-circuit state.

== Operation of Switching Power Supply Circuit 10 ==
Here, an example of the operation of the switching power supply circuit 10 trimmed by the reference voltage circuit 91 by the semiconductor test apparatus will be described with reference to FIG. Here, it is assumed that the reference voltage Vref3 is adjusted to a target value determined based on the actual on-resistance Ron1 and the limiter current of the current value IA. For example, it is assumed that the adjusted reference voltage Vref3 matches the target value. Further, in the following operation example, it is assumed that the load of the switching power supply circuit 10 changes from a normal state to a state in which, for example, a load short circuit occurs. Furthermore, the current value of the output current Iout when the load is normal is a current value Ix (Ix <IA), and the current value of the output current Iout when the load is short-circuited is a current value Iy (Iy> IA). The reference voltage Vref3 shown in FIG. 5 is a value when the NMOS transistor 83 is turned on.

  First, when the load is normal, the control circuit 32 outputs an output signal Vls having a predetermined duty ratio so that a desired level of the output voltage Vout is maintained. For example, when the output signal Vls becomes H level at time T10, the drive signal Vdr1 also becomes H level, so that the NMOS transistor 30 is turned on. When the NMOS transistor 30 is turned on, the voltage Vsw rises from the voltage lower than 0V by the forward voltage Vf of the diode 21 so as to approach the input voltage Vin. Then, the increase in the voltage Vsw stops when the voltage becomes Vin−Ron × Ix. At time T11, the drive signal Vdr2 obtained by delaying the rise of the output signal Vls becomes H level. As a result, the NMOS transistor 83 is turned on, and the voltage Vd changes from the input voltage Vin to the voltage Vin−Ron1 × Ix. As described above, since current value Ix <current value IA, voltage Vd at time T11 is higher than reference voltage Vref3 (= Vin−Ron1 × IA). Therefore, the comparator 92 continues to output the L level comparison signal Vc. Then, at time T12, which is one cycle after the output signal Vls from time T10, the operation at time T10 is repeated again. Thus, when the load is normal, the comparison signal Vc does not change, and the drive circuit 33 continues to switch the NMOS transistor 30 based on the output signal Vls having a predetermined duty ratio.

  Next, the operation of the switching power supply circuit 10 when a load short circuit occurs at time T13 will be described. When the output signal Vls becomes H level at time T14, the NMOS transistor 30 is turned on, so that the voltage Vsw rises. As described above, the output current Iout when the load is short-circuited is the current value Iy. For this reason, the voltage Vsw rises to the voltage Vin−Ron × Iy. When the drive signal Vdr2 becomes H level at time T15, the NMOS transistor 83 is turned on, and the voltage Vd becomes the voltage Vin−Ron1 × Iy. Here, since current value Iy> current value IA, voltage Vd at time T15 is lower than reference voltage Vref3 (= Vin−Ron1 × IA). Therefore, the comparison signal Vc of the comparator 92 changes from the L level to the H level. When the comparison signal Vc becomes H level, the D flip-flop 57 is reset, so that the output signal Vls becomes L level. As a result, at time T15, the NMOS transistor 30 is turned off. As described above, in this embodiment, it is possible to prevent an overcurrent from flowing through the NMOS transistor 30. Even after time T15, when a load short-circuit occurs, the operations at times T14 and T15 described above are repeated.

  The switching power supply circuit 10 according to the present embodiment has been described above. In general, the on-resistance Ron of a MOS transistor is determined by determining the mobility, gate capacitance, channel width, channel length, gate-source voltage, and threshold voltage of a MOS transistor by μ, Cox, W, L, Vgs, Vth, respectively. Then, Ron = 1 / (μ · Cox · (W / L) · (Vgs−Vth)). Accordingly, the on-resistance Ron is affected by the thickness of the oxide film. However, in this embodiment, the NMOS transistor 30 and the NMOS transistor 150 are formed in the same power supply IC 20, and the thickness of the oxide film in the power supply IC 20 is substantially constant. For this reason, for example, when the thickness of the oxide film changes and the on-resistance Ron1 of the NMOS transistor 30 increases, the on-resistance Ron3 of the NMOS transistor 150 similarly increases. That is, even when the thickness of the oxide film changes, the reference voltage Vref3 and the voltage Vd change similarly. Therefore, for example, as compared with the case where only the NMOS transistor 30 is formed in another chip, the switching power supply circuit 10 according to the present embodiment can detect the overcurrent with high accuracy while reducing the number of components. Furthermore, in this embodiment, since the on-resistance of the NMOS transistor 30 is a current detection resistor, it is not necessary to provide a separate current detection resistor.

  The NMOS transistor 150 and the NMOS transistor 30 are the same type of transistor. For this reason, the on-resistance Ron3 of the NMOS transistor 150 and the on-resistance Ron1 of the NMOS transistor 30 change similarly with respect to temperature, applied voltage, and the like. Further, the temperature change of the bias current Ib generated based on the reference voltage Vref2 such as a band gap is generally small. Therefore, the reference voltage Vref3 and the voltage Vd (voltage Vsw) change similarly with respect to the temperature. For this reason, for example, compared with the case where a PMOS transistor is used to generate the reference voltage Vref3, the present embodiment can detect an overcurrent with higher accuracy.

  The reference voltage circuit 91 can adjust the current value of the bias current Ib. Therefore, even when the ON resistance of the NMOS transistor 30 having a large variation is used as the current detection resistor, it is possible to detect the overcurrent with high accuracy.

  In addition, the adjustment of the bias current Ib is realized by, for example, the trimming element 130 that changes between the electrodes in a short circuit state or an open state.

  In the present embodiment, a plurality of trimming elements for adjusting the current value of the bias current Ib are provided. Therefore, for example, the level of the reference voltage Vref3 can be made closer to the target value as compared with the case where the value of the bias current Ib is adjusted using a single trimming element.

  Furthermore, since the trimming of the reference voltage Vref3 is performed before the power supply IC 20 is shipped, it is possible to save the user's trouble.

  Further, generally, the value of the on-resistance Ron1 of the NMOS transistor 30 varies by about several tens of percent due to manufacturing variations and the like. For this reason, for example, when the reference voltage Vref3 is determined based on the product of the design value of the on-resistance of the NMOS transistor 30 and the current value IA, the comparator 92 detects an overcurrent with a current value greatly different from the current value IA. Will be. In the present embodiment, the reference voltage Vref3 is determined based on the product of the actual resistance value of the on-resistance Ron1 and the limiter current of the current value IA. For this reason, even when the ON resistance of the NMOS transistor 30 having a large variation is used as the current detection resistor, it is possible to accurately detect the overcurrent.

  In addition, the said Example is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  In the present embodiment, the NMOS transistor 30 and the NMOS transistor 150 are, for example, transistors manufactured by the same manufacturing process. However, not all processes need to be completely the same. For example, when the power supply IC 20 is manufactured using a three-layer metal process, the NMOS transistor 150 may be formed in the first layer and the NMOS transistor 30 may be formed in the third layer. Further, vias, contacts, and the like that have little influence on the temperature characteristics and voltage characteristics of the transistors may be different.

  For example, in this embodiment, the NMOS transistor 30 is actually measured and the on-resistance Ron1 is calculated, but the present invention is not limited to this. For example, by using a value such as a threshold value measured on an actual wafer or the like in the above formula, a resistance value corresponding to the actual on-resistance can be calculated. As described above, the reference voltage Vref3 may be adjusted based on the resistance value corresponding to the actual on-resistance Ron1 and the current value IA. Even in such a case, the overcurrent can be detected with high accuracy as in the present embodiment.

20 Power IC
21, 41 Diode 22 Inductor 23, 24, 25 Capacitor 26, 27, 28, 29, 84, 120-125 Resistance 30, 83, 150 NMOS transistor 31 Power supply circuit for bootstrap 32 Control circuit 33 Drive circuit
34 Voltage detection circuit 35 Overcurrent detection circuit 40 Internal power supply circuit 50, 91, 100 Reference voltage circuit 51, 101 Error amplification circuit 52 Oscillation circuit 53, 92 Comparator 54 Clock generation circuit 55, 70, 71, 81, 82 Inverter 56 AND Circuit 57 D flip-flop 58 Level shift circuit 80 Rise delay circuit 90 Reference current generation circuit 102, 110-115 NPN transistor 103, 104 PNP transistor 130-133 Trimming element 140-144 Terminal

Claims (5)

An overcurrent detection circuit that detects an overcurrent generated in a control transistor that controls a current flowing through a load
A reference voltage circuit including a bias current generating circuit for generating a bias current and a transistor, and outputting a reference voltage based on the bias current and the on-resistance of the transistor;
A detection voltage determined based on a voltage generated between an input electrode and an output electrode of the control transistor when the control transistor is turned on is compared with the reference voltage, and a current flowing through the control transistor has a predetermined current value. A detection circuit for detecting whether or not
With
The control transistor and the transistor are formed in the same integrated circuit;
An overcurrent detection circuit characterized by. The overcurrent detection circuit according to claim 1,
The overcurrent detection circuit, wherein the transistor is the same type of transistor as the control transistor. The overcurrent detection circuit according to claim 1 or 2,
The reference voltage circuit further includes a bias current adjustment circuit for adjusting the bias current;
An overcurrent detection circuit characterized by. The overcurrent detection circuit according to claim 3,
The bias current adjustment circuit includes:
Including a trimming element that increases the bias current when the state between the electrodes is in one of a short circuit state or an open state, and decreases the bias current when the state between the electrodes is in the other state;
An overcurrent detection circuit characterized by. The overcurrent detection circuit according to claim 4,
The bias current circuit includes:
A plurality of constant current circuits for changing the current value of the bias current;
The bias current adjustment circuit includes:
Including a plurality of trimming elements connected in series to each of the plurality of constant current circuits;
An overcurrent detection circuit characterized by.

Images