JP2011029983A - A/d conversion circuit - Google Patents

Abstract

To realize an AD converter circuit that reduces the occurrence of erroneous determination while maintaining a low input capacitance.
A differential voltage between a voltage Vinp and Vinn of an input signal and a plurality of reference voltages VrpN and VrnN having different voltage values in order is amplified, and an order corresponding to the order of the voltage values of the plurality of reference voltages is obtained. A plurality of first-stage amplifiers, and one or more second-stage amplifiers 56 (N + 1) for amplifying a differential voltage between outputs of two first-stage amplifiers 54N and 54 (N + 2) adjacent to the plurality of first-stage amplifiers, And an encoder 53 for calculating values indicating levels of the voltage of the input signal with respect to the plurality of reference voltages from the outputs of the plurality of first stage amplifiers and the one or more second stage amplifiers.
[Selection] Figure 5

Description

  The present invention relates to an AD conversion circuit, and more particularly to a flash AD conversion circuit.

  In recent years, there has been a demand for transmitting signals at high speed. For example, signal transmission between multiple circuit blocks in a chip, signal transmission between LSI chips, signal transmission between boards or housings is performed, but this increases the operating speed and increases the amount of processing data Accordingly, it is desired to widen the signal transmission speed.

  FIG. 1 is a diagram showing a schematic configuration of a high-speed signal transmission system. As shown in FIG. 1, the signal transmission system includes a transmission circuit 1, a transmission line 2, and a reception circuit 3. In the transmission circuit 1, low-speed parallel data is converted into serial data by a multiplexer (MUX) 11, and serial data is output to the transmission line 2 by a driver (Driver) 12 having the same output impedance as the characteristic impedance of the transmission line 2. To do. Serial data is input to the receiving circuit 3 through the transmission line 2. The input reception waveform received by the reception circuit 3 is deteriorated due to the characteristics of the transmission line 2. Specifically, the high frequency component is lost and the waveform becomes dull.

  The data to be transmitted is binary data of “0” and “1”. When the deterioration in the transmission line 2 is small, the received data is determined by determining with a comparator having a predetermined threshold level. It can be played correctly. However, when the transmission line 2 is long or when the frequency of transmission data becomes very high, the deterioration in the transmission line 2 becomes large, and if it is determined by one comparator, the received data is reproduced correctly. It is not possible. Therefore, the signal level is detected according to the clock of the received data, and the data received from it is reproduced correctly.

  Therefore, as shown in FIG. 1, the receiving circuit 3 samples the received signal (analog waveform) and digitizes it by an analog / digital conversion circuit (ADC) 31 arranged in the input portion. The equalization circuit (EQ) 32 performs waveform shaping (equalization processing) on the output of the ADC 31 so as to compensate for waveform deterioration due to the transmission line. The shaped reception data is determined as 0/1, and the determination result is converted from serial data to parallel data by a latch (Decision Latch) and a demultiplexer (D / L DMUX) 33. A clock signal is required for sampling in the ADC 31 and processing in the equalization circuit 32. A clock recovery circuit (CRU) 34 recovers a data clock from the received data output from the equalization circuit 32.

  In each application such as SATA (Serial Advanced Technology Attachment) and PCIe (Peripheral Component Interconnect express), a data rate is defined, and until now, a receiver (circuit) optimized for each application has been developed. However, if a receiver is developed for each application, there is a problem that development costs increase. Therefore, it is conceivable to reduce a development cost by commonly using a receiver having a wide range of compatible data rates in many applications. For this reason, there is a demand for a receiver that can handle a wide range of data rates, that is, a broadband receiver.

  In addition, an application that requires a wide data rate such as several hundred Mbps to several Gbps, such as HDMI (High Definition Multimedia Interface), has been developed, and it is predicted that a wider signal transmission speed will be required in the future.

  As shown in FIG. 1, the ADC 31 is used in the wideband receiving circuit. Currently, the only ADC 31 that can satisfy the above requirements is a flash ADC.

  FIG. 2 is a diagram showing a configuration of a general flash type ADC. In the signal transmission system of FIG. 1, the signal is often transmitted as a differential signal. Therefore, in the following description, an ADC that converts the differential signal will be described as an example. However, the following description is applicable not only to ADCs that convert differential signals, but also to ADCs that process non-differential signals (unipolar signals).

As shown in FIG. 2, a general flash ADC includes a reference voltage generation circuit 41, a comparison circuit unit 42, and an encoder 43. The reference voltage generation circuit 41 divides the voltage difference VH−VL between the high reference voltage VH and the low reference voltage VL by a ladder resistor, and generates a plurality of reference voltages having different voltage values in order. For example, when the ADC output data is m bits, the voltage difference VH−VL is divided into 2 ^m (= M). It is desirable that the divided voltage differences are equally spaced. Hereinafter, a case where the voltage difference VH−VL is divided into 2 ^m (= M) pieces will be described as an example.

  The division generates (M−1) reference voltages from VL + (VH−VL) / M to VL + (VH−VL) (M−1) / M. For example, the Nth reference voltage VrN = VL + (VH−VL) N / M. As described above, since the ADC converts the differential signal here, a differential reference voltage that is symmetric with respect to the center reference voltage is generated with VL + (VH−VL) / 2 as the center reference voltage. For example, the minimum reference voltage VL + (VH−VL) / M is the first positive reference voltage Vrp1 and the (M−1) th negative reference voltage Vrn (M−1). Similarly, the maximum reference voltage VL + (VH−VL) (M−1) / M is the (M−1) th positive reference voltage Vrp (M−1) and the first negative reference voltage Vrn1. . In more general terms, the Nth positive reference voltage is VrpN = VL + (VH−VL) N / M, which is the (MN) th negative reference voltage Vrn (MN). Similarly, the Nth negative reference voltage is VrnN = VL + (VH−VL) (MN) / M, which is the (MN) th positive reference voltage Vrp (MN).

  The comparison circuit unit 42 includes (M−1) amplifier circuits (amplifiers) and (M−1) latches. As shown in FIG. 2, a positive input signal Vinp and a negative input signal Vinn are commonly input to (M−1) amplifier circuits (amplifiers). The Nth amplifier 44N amplifies the difference voltage between Vinp and Vinn and the Nth reference voltages VrpN and VrnN, and outputs positive and negative outputs OpN and OnN. When the amplifier output is set to be saturated, the amplifier operates as a comparator. Similarly, the (N + 1) th amplifier 44 (N + 1) amplifies the difference voltage between Vinp and Vinn and the (N + 1) th reference voltages Vrp (N + 1) and Vrn (N + 1), and outputs a positive / negative output Op (N + 1). And On (N + 1) are output. The (N + 2) th amplifier 44 (N + 2) amplifies the difference voltage between Vinp and Vinn and the (N + 2) th reference voltage Vrp (N + 2) and Vrn (N + 2), and outputs positive and negative outputs Op (N + 2) and On ( N + 2) is output. The positive and negative outputs of the amplifier reach a positive and negative saturation level when sufficient time has elapsed. The (M−1) amplifiers operate in synchronization with the clock signal CK. For example, the amplifier performs an amplification operation when the logic value of the clock signal CK is “high (H)”, and “low (L)”. Reset operation is performed at a certain time.

  The (M−1) latches are connected corresponding to the (M−1) amplifiers, and latch the positive and negative outputs of the corresponding amplifiers in synchronization with the change of the clock signal. For example, the Nth latch 45N latches the positive and negative outputs OpN and OnN of the Nth amplifier 44N when the clock signal CK changes from H to L. Similarly, the (N + 1) th latch 45 (N + 1) outputs the positive and negative outputs Op (N + 1) and On (N + 1) of the (N + 1) th amplifier 44 (N + 1) when the clock signal CK changes from H to L. Latch. The (N + 2) th latch 45 (N + 2) latches the positive and negative outputs Op (N + 2) and On (N + 2) of the (N + 2) th amplifier 44 (N + 2) when the clock signal CK changes from H to L. If the outputs of the (M−1) latches are normal, the outputs of the latches up to a certain position of the latches arranged in order are L, and the outputs of the latches thereafter are H. The voltage of the input signal is between the reference voltages input to the two amplifiers corresponding to the latch whose output changes.

  The encoder 43 obtains a position where the output of the latch changes based on the outputs of the (M−1) latches, converts a thermometer code indicating the position into a binary code, and outputs it. This is the AD conversion value.

  The AD conversion range is the range from VL to VH. When the input signal voltage is VL or less, an AD conversion value indicating the minimum value is output, and when the input signal voltage is VH or more. Outputs an AD conversion value indicating the maximum value. Normally, the input signal is limited to be in a range from VL to VH.

In the ADC of FIG. 2, when the resolution is m bits, 2 ^m −1 (= M−1) amplifiers are required, which causes a problem that the circuit scale and the input capacity are increased. Therefore, an ADC having a reduced circuit scale and input capacity by performing an interpolation process has been proposed.

  FIG. 3 is a diagram illustrating a configuration of an ADC that performs interpolation processing. The ADC of FIG. 3 deletes every other (M−1) amplifiers in the ADC of FIG. 2, and the latch corresponding to the deleted amplifier has a positive / negative sign of two amplifiers adjacent to the deleted amplifier. Enter the output. In FIG. 3, the (N + 1) th amplifier is deleted, and the negative output OnN of the Nth amplifier 44N and the positive output Op (N + 2) of the (N + 2) th amplifier 44 (N + 2) are replaced with the (N + 1) th latch 45. Input to (N + 1).

  FIG. 4 is a diagram for explaining signal changes in the ADC of FIG. In FIG. 4, curve X shows the positive output of an amplifier whose input signals Vinp and Vinn are sufficiently larger than the reference voltage or the negative output of an amplifier whose input signals Vinp and Vinn are sufficiently smaller than the reference voltage. Further, in FIG. 4, a curve Y indicates a negative output of an amplifier in which the input signals Vinp and Vinn are sufficiently larger than the reference voltage, or a positive output of an amplifier in which the input signals Vinp and Vinn are sufficiently smaller than the reference voltage. In FIG. 4, the arrows indicate the timing at which the clock signal CK changes from H to L and the latch latches the output of the amplifier.

  When input signals Vinp and Vinn that are sufficiently larger or smaller than the reference voltage are input to two amplifiers adjacent to the deleted amplifier, the latch corresponding to the deleted amplifier has positive and negative outputs indicated by curves X and Y. Latch. Therefore, such a latched result is not particularly problematic.

  On the other hand, when the input signals Vinp and Vinn close to the reference voltage are input to the two amplifiers adjacent to the deleted amplifier, one positive output and the other negative output of the two amplifiers and one The negative output of and the other positive output have the same polarity. Therefore, erroneous determination may occur when these are latched. In FIG. 4, curves A and B show one set of positive and negative outputs of two amplifiers when the voltages of the input signals Vinp and Vinn are between the reference voltages of two adjacent amplifiers. Show. Specifically, the voltage of the input signal Vinp is slightly higher than the intermediate voltage between the reference voltage VrpN input to the Nth amplifier 44N and the reference voltage Vrp (N + 2) input to the (N + 2) th amplifier 44 (N + 2). Suppose it's big. Therefore, the voltage of the input signal Vinn is slightly smaller than the intermediate voltage between the reference voltage VrnN input to the Nth amplifier 44N and the reference voltage Vrn (N + 2) input to the (N + 2) th amplifier 44 (N + 2). In this case, the positive output Op (N + 2) of the (N + 2) th amplifier 44 (N + 2) becomes the curve A, and the negative output OnN of the Nth amplifier 44N becomes the curve B. The (N + 1) th latch 45 (N + 1) latches the signal that changes on the curves A and B at the timing of the arrow. Similar to the RS flip-flop, the latch latches a value corresponding to the level of two inputs. In this case, since the curve B transitions before the curve A, the latch latches a normal value.

  However, as shown in FIG. 4, curves A and B eventually saturate to the same voltage. Therefore, when the gain of the amplifier is large and the curves A and B transition abruptly, the positive output and the negative output of the two amplifiers may saturate to the same voltage at the latch timing. In this case, the latch value becomes unstable, and erroneous determination may occur. Further, when the gain of the amplifier is small and the transition between the curves A and B is gentle, there may be a case where the difference voltage between the positive output and the negative output of the two amplifiers is small at the latch timing. Also in this case, the value of the latch becomes unstable and an erroneous determination may occur.

  As described above, the ADC in which every other amplifier in FIG. 3 is deleted has a problem that the voltage of the input signal may not be converted into correct digital data, resulting in a conversion error.

“Principles of Data Conversion System Design” Behzad Razavi, Willey-IEEE Press, December 1994.

  According to the embodiment, an AD conversion circuit (ADC) is described in which occurrence of erroneous determination is reduced while maintaining a low input capacitance.

  The AD converter circuit according to the first aspect of the embodiment amplifies a difference voltage between the voltage of the input signal and a plurality of reference voltages having different voltage values in order, and corresponds to the order of the voltage values of the plurality of reference voltages. A plurality of first-stage amplifiers, one or more second-stage amplifiers for amplifying the differential voltage of the outputs of two adjacent first-stage amplifiers, a plurality of first-stage amplifiers, and one or more two-stage amplifiers An encoder that calculates a value indicating the level of the voltage of the input signal with respect to a plurality of reference voltages from the output of the stage amplifier.

  According to the embodiment, the occurrence of erroneous determination is reduced in the AD converter circuit with reduced input capacitance.

FIG. 1 is a diagram showing a schematic configuration of a high-speed signal transmission system. FIG. 2 is a diagram showing a configuration of a general flash type ADC. FIG. 3 is a diagram illustrating a configuration of an ADC that performs interpolation processing. FIG. 4 is a diagram for explaining signal changes in the ADC of FIG. FIG. 5 is a diagram illustrating a configuration of the AD conversion circuit according to the first embodiment. FIG. 6 is a diagram illustrating a circuit configuration of the first-stage amplifier and the second-stage amplifier of the ADC according to the first embodiment. FIG. 7 is a diagram for explaining signal changes in the ADC of the first embodiment. FIG. 8 is a diagram for explaining a signal change due to the gain of the second-stage amplifier in the first embodiment. FIG. 9 is a diagram illustrating a configuration of the AD conversion circuit according to the second embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a second-stage amplifier of the ADC according to the second embodiment. FIG. 11 is a diagram illustrating a circuit configuration of a second-stage amplifier of the ADC according to the second embodiment. FIG. 12 is a diagram illustrating a circuit configuration of a second-stage amplifier of the ADC according to the second embodiment. FIG. 13 is a diagram illustrating a circuit configuration of a second-stage amplifier of the ADC according to the second embodiment. FIG. 14 is a diagram showing a configuration of a current mirror circuit in the second stage amplifier of FIG.

  FIG. 5 is a diagram illustrating a configuration of an AD conversion (Analog-to-Digital Conversion) circuit according to the first embodiment.

As illustrated in FIG. 5, the AD conversion circuit according to the first embodiment includes a reference voltage generation circuit 51, a comparison circuit unit 52, and an encoder 53. The reference voltage generation circuit 51 divides the voltage difference VH−VL between the high reference voltage VH and the low reference voltage VL by a ladder resistor, and generates a plurality of reference voltages having different voltage values in order. For example, when the ADC output data is m bits, the voltage difference VH−VL is divided into 2 ^m (= M). It is desirable that the divided voltage differences are equally spaced. Hereinafter, a case where the output data of the ADC is m bits will be described as an example.

  When the voltage range from VL to VH is divided into M, there are (M−1) reference voltages from VL + (VH−VL) / M to VL + (VH−VL) (M−1) / M. . For example, the Nth reference voltage VrN = VL + (VH−VL) N / M. As described above, since the ADC converts the differential signal here, there is a differential reference voltage that is symmetrical with respect to the center reference voltage with VL + (VH−VL) / 2 as the center reference voltage. For example, the minimum reference voltage VL + (VH−VL) / M is the first positive reference voltage Vrp1 and the (M−1) th negative reference voltage Vrn (M−1). Similarly, the maximum reference voltage VL + (VH−VL) (M−1) / M is the (M−1) th positive reference voltage Vrp (M−1) and the first negative reference voltage Vrn1. . In more general terms, the Nth positive reference voltage is VrpN = VL + (VH−VL) N / M, which is the (MN) th negative reference voltage Vrn (MN). Similarly, the Nth negative reference voltage is VrnN = VL + (VH−VL) (MN) / M, which is the (MN) th positive reference voltage Vrp (MN).

  In the first embodiment, the reference voltage generation circuit 51 generates a reference voltage every other one from VL + (VH−VL) / M to VL + (VH−VL) (M−1) / M. In other words, the reference voltage generation circuit 51 generates the reference voltage VL + (VH−VL) I / M (I is an odd number from 1 to (M−1)), but the voltage VL + (VH−VL) I / M. (I is an even number from 2 to (M-2)) does not occur. In order to generate such a reference voltage, for example, M resistors having the same resistance value are connected between VL and VH, and (M−2) resistors other than the resistors at both ends are connected to two adjacent resistors. Ladder resistance is created so that the total resistance becomes one resistance. Specifically, in the ladder resistor, the ladder resistor is made so that the resistance value of the two resistors at both ends is 1, and the resistance value of the (M−2) resistors is 2.

  The comparison circuit unit 52 includes M / 2 first stage amplifier circuits (amplifiers) 54N (N is an odd number from 1 to (M-1)) and (M-2) / 2 second stage amplifier circuits (amplifiers). ) 56 (N + 1) (N is an even number from 2 to (M−2)) and (M−1) latches 55N (N is an integer from 1 to (M−1)). In FIG. 5, two first stage amplifiers 54N, 54 (N + 2), one second stage amplifier 56 (N + 1), and three latches 55N, 55 (N + 1), 55 (N + 2) are shown. .

  As shown in FIG. 5, the positive input signal Vinp and the negative input signal Vinn are commonly input to the M / 2 first stage amplifiers. First-stage amplifier 54N amplifies the difference voltage between Vinp and Vinn and reference voltages VrpN and VrnN, and outputs positive and negative outputs OpN and OnN. Similarly, first-stage amplifier 54 (N + 2) amplifies the difference voltage between Vinp and Vinn and reference voltages Vrp (N + 2) and Vrn (N + 2), and outputs positive and negative outputs Op (N + 2) and On (N + 2). The M / 2 first-stage amplifiers operate in synchronization with the clock signal CK. For example, the amplification operation is performed when the logical value of the clock signal CK is “high (H)”, and is “low (L)”. Sometimes reset operation is performed.

  (M-2) / 2 The positive and negative outputs of the adjacent first stage amplifiers are input to the two second stage amplifiers. As shown in FIG. 5, the second stage amplifier 56 (N + 1) includes a difference voltage between the positive output Op (N + 2) of the first stage amplifier 54 (N + 2) and the negative output OnN of the first stage amplifier 54N, and the first stage amplifier 54 (N + 2). The differential voltage between the negative output On (N + 2) and the positive output OpN of the first-stage amplifier 54N is amplified to output amplified positive / negative outputs AOp (N + 1) and AOn (N + 1). The (M-2) / 2 second-stage amplifiers operate in synchronization with the clock signal CK as in the first-stage amplifier. For example, the second-stage amplifiers are amplified when the logic value of the clock signal CK is “high (H)”. The operation is performed, and when it is “low (L)”, the reset operation is performed.

  The (M−1) latches include an odd-numbered latch 55N (N is an odd number from 1 to (M−1)) and an even-numbered latch 55N (N is an even number from 2 to (M−2)). And divided. The odd-numbered latch 55N latches the positive / negative output of the corresponding first-stage amplifier in synchronization with the change of the clock signal CK. For example, the latch 55N latches the positive and negative outputs OpN and OnN of the amplifier 54N when the clock signal CK changes from H to L. Similarly, the latch 55 (N + 2) latches the positive and negative outputs Op (N + 2) and On (N + 2) of the amplifier 54 (N + 2) when the clock signal CK changes from H to L.

  The latch 55 (N + 1) latches the amplified positive and negative outputs AOp (N + 1) and AOn (N + 1) of the second-stage amplifier 54 (N + 1) when the clock signal CK changes from H to L.

  The encoder 53 obtains a position where the output of the latch changes based on the outputs of the (M−1) latches, and outputs a binary code indicating the position as an AD conversion value.

  In the first embodiment, the configuration and operation of the (M−1) latches and encoder 53 are the same as those in the ADC shown in FIGS. 2 and 3. The operation of the M / 2 first stage amplifiers is the same as the operation in the ADC shown in FIGS. 2 and 3 except that every other unit is deleted.

  FIG. 6 is a diagram illustrating a circuit configuration of the first-stage amplifier and the second-stage amplifier of the ADC according to the first embodiment. The amplifier of FIG. 6 includes P-channel transistors TP1 and TP2 and N-channel transistors TN1 and TN2 that form a differential amplifier, and N-channel transistors TN3 and TN4 and TN5 and TN6 that form a differential input unit. Further, this amplifier makes P-channel transistors TP0, TP3 and TP4 that operate the differential amplifier when the clock signal CK is H and reset the differential amplifier when the clock signal CK is L, and the clock signal CK is N-channel transistors TN7 and TN8 are provided for setting the differential input unit in an operating state when the clock signal CK is L and inactivating the differential input unit when the clock signal CK is low.

  When the amplifier of FIG. 6 is used as a first stage amplifier, input signals are input to the terminals Vinp and Vinn of FIG. 6, and a reference voltage is input to the terminals Vrp and Vrn. When the amplifier of FIG. 6 is used as a second stage amplifier, the positive output and negative output of the first-stage amplifier adjacent to the upper side are input to the terminals Vinp and Vinn of FIG. 6, respectively, and the lower side is adjacent to the terminals Vrp and Vrn. Input the positive output and negative output of the first stage amplifier. For example, in the case of the second stage amplifier 56 (N + 1) in FIG. 5, the positive output Op (N + 2) of the first stage amplifier 54 (N + 2) is output to the terminal Vinp, and the negative output On ( N + 2), the negative output OnN of the first-stage amplifier 54N is input to the terminal Vrp, and the positive output OpN of the first-stage amplifier 54N is input to the terminal rn.

  The configuration and operation of the amplifier in FIG. 6 are widely known and will not be described in detail. However, a current difference proportional to the sum of the difference voltage between Vinp and Vrp and the difference voltage between Vrn and Vinn is TN1 and TN2. Appears as a difference in current flowing through A voltage difference corresponding to the current difference appears as a difference voltage between the outputs Vop and Von.

  FIG. 7 is a diagram for explaining the operation of the second-stage amplifier in the first embodiment. In FIG. 7A, as described in FIG. 4, when the voltages of the input signals Vinp and Vinn are between the reference voltages of two adjacent first stage amplifiers, the positive outputs of the two first stage amplifiers and One set of negative outputs looks like curves A and B. Curve C shows the difference between curve A and curve B. The other set is a reverse polarity curve symmetric with respect to the center voltage.

  The second-stage amplifier amplifies the difference voltage between the positive output and the negative output of the two first-stage amplifiers, that is, the difference voltage shown by the curve C, and outputs the amplified output as shown by the curve D in FIG. Output. Accordingly, even when the curves A and B are approximate, that is, when the difference voltage is small, the difference voltage is amplified in a short time by the second-stage amplifier and input to the even-numbered latches. Therefore, the occurrence of erroneous determination is reduced compared to the example of FIG.

  Note that, as shown in FIG. 7A, the curves A and B are eventually saturated with the same polarity, so the curve C is zero (center voltage). Accordingly, as shown in FIG. 7B, the curve D is also zero (center voltage). Therefore, it is desirable that the curve D be close to the maximum value at the latch timing indicated by the arrow in FIG. However, since the cycle of the clock signal CK is determined in advance, the gain of the second-stage amplifier is appropriately set, and the curve D is set to be near the maximum value at the latch timing.

  FIG. 8 is a diagram for explaining a change in the amplified output due to the gain of the second-stage amplifier.

  FIG. 8A shows a change in amplification output when the gain of the second-stage amplifier is large. As shown in FIG. 8A, when the gain of the second-stage amplifier is too large, the difference voltage is amplified rapidly, but when the outputs of the two first-stage amplifiers increase, the output voltage becomes saturated. Conversely, the amplified output becomes smaller. As shown in FIG. 8C, when the gain of the second-stage amplifier is too small, the amplification speed of the differential voltage is insufficient, and the amplified output remains small even at the latch timing. On the other hand, as shown in FIG. 8B, when the gain of the second-stage amplifier is set appropriately, the difference voltage is amplified to an appropriate magnitude at the latch timing, and the correct value is latched. be able to.

  As described above, it is important to appropriately set the gain of the second-stage amplifier, and the gain of the second-stage amplifier is set at the manufacturing stage according to the conditions in which the ADC is used.

  However, in the ADC manufacturing stage, the conditions under which the ADC is used are not fixed, and the gain of the second stage amplifier may not be determined. The AD converter circuit (ADC) of the second embodiment described below is an ADC suitable for such a case.

  FIG. 9 is a diagram illustrating a configuration of an AD conversion circuit (ADC) according to the second embodiment. The ADC of the second embodiment is an amplifier in which the gain of the second stage amplifier can be adjusted. Unlike the ADC of the first embodiment, the gain of the second stage amplifier can be adjusted by inputting an adjustment code from the outside. The other parts are the same as in the first embodiment.

  As shown in FIG. 9, the gain of the second-stage amplifier 57 (N + 1) can be adjusted according to the adjustment code gain input from the outside. Similarly, the gains of the other second-stage amplifiers can be adjusted according to the adjustment code gain input from the outside. In a state where the ADC is used, the gain of the second-stage amplifier is adjusted so that the amplified output (difference voltage) of the second-stage amplifier has a characteristic as shown in FIG.

  10 to 14 are diagrams illustrating configuration examples of amplifiers capable of gain adjustment. In the amplifier, the gain changes in proportion to the amount of current flowing through the differential amplification unit and the difference input unit. The amount of current flowing through the differential amplification unit and the difference input unit changes in proportion to the size of the transistor that forms the amount of current flowing through the differential amplification unit and the difference input unit.

  In the example of FIG. 10, TN7 and TN8 that operate as constant current sources of the differential input unit of FIG. 6 are formed by four sets of transistors connected in parallel, and the size of the transistors is changed by changing the set of transistors to be operated. Change. Specifically, TN7 is formed by four sets of columns in which two transistors TN71 and TS71, TN72 and TS72, TN73 and TS73, and TN74 and TS74 are connected in series. Further, TN8 is formed by four sets of columns in which two transistors TN81 and TS81, TN82 and TS82, TN83 and TS83, and TN84 and TS84 are connected in series. TN71, TN72, TN73 and TN74 have the same size, and TS71, TS72, TS73 and TS74 have the same size. Similarly, TN81, TN82, TN83, and TN84 are the same size, and TS81, TS82, TS83, and TS84 are the same size.

  The decoder 60 decodes the 2-bit adjustment code and generates a selection signal to be applied to the gates of TS71, TS72, TS73, and TS74. This selection signal is also applied to the gates of TS81, TS82, TS83, and TS84. The selection signal sets the number of operating states among TS71, TS72, TS73, and TS74 between 1 to 4, and sets the number of operating states among TS81, TS82, TS83, and TS84 to 1 to 4 Set between. Thereby, the amount of current flowing through this portion (constant current source) can be changed to 1: 2: 3: 4, and other operations are the same as those in FIG.

  In the example of FIG. 11, the TN3, TN4, TN5, and TN6 of the difference input unit of FIG. 6 have the same configuration as described in FIG. In the example of FIG. 12, the amount of current can be changed in the TP1, TP2, TN1, and TN2 of the differential amplification unit of FIG. 6 with the same configuration as described in FIG. In the example of FIG. 13, TN9 and TN10 are connected in series to TN7 and TN8 that operate as constant current sources of the differential input unit of FIG. Then, the current flowing through TN9 and TN10 can be controlled by the current mirror circuit 70, and the amount of current generated in the current mirror circuit 70 is changed according to the adjustment code.

  FIG. 14 is a diagram illustrating a configuration example of the current mirror circuit 70. As shown in FIG. 14, the decoder 60 decodes the adjustment code and selects a transistor to be turned on from the transistors TS1 to TS4. In accordance with the number of transistors turned on, the current flowing through the current mirror formed by TC3 and TC4 to TC7 changes, and the output current changes. The output is applied to TN9 and TN10 in FIG.

  Various other amplifiers capable of gain adjustment can be realized. Further, although the adjustment code is 2 bits here, it may be 3 bits or more.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Hereinafter, the following additional notes will be disclosed with respect to the embodiment.
(Appendix 1)
A plurality of first stage amplifiers that amplify a difference voltage between a voltage of the input signal and a plurality of reference voltages having different voltage values in order, and having an order corresponding to the order of the voltage values of the plurality of reference voltages;
One or more second-stage amplifiers that amplify a difference voltage between outputs of two first-stage amplifiers adjacent to the plurality of first-stage amplifiers;
An AD converter comprising: an encoder that calculates a value indicating a level of the voltage of the input signal with respect to the plurality of reference voltages from outputs of the plurality of first-stage amplifiers and the one or more second-stage amplifiers. circuit.
(Appendix 2)
A plurality of latches for latching output values of the plurality of first stage amplifiers and the one or more second stage amplifiers, respectively, and outputting the latched values;
The AD converter circuit according to appendix 1, wherein the encoder calculates a value indicating a level of the voltage of the input signal with respect to the plurality of reference voltages from output values of the plurality of latches.
(Appendix 3)
The AD conversion circuit according to appendix 2, further comprising a reference voltage generation circuit that generates the plurality of reference voltages.
(Appendix 4)
The AD converter circuit according to appendix 2 or 3, wherein the one or more second-stage amplifiers are capable of gain adjustment.
(Appendix 5)
The plurality of first stage amplifiers, the one or more second stage amplifiers, and the plurality of latches operate in synchronization with a clock signal,
The plurality of first-stage amplifiers and the one or more second-stage amplifiers perform an amplification operation when the clock signal has one logic value,
The plurality of latches respectively latch the output values of the plurality of first stage amplifiers and the one or more second stage amplifiers when the clock signal changes from the one logical value to the other logical value. 5. The AD conversion circuit according to any one of 4 to 4.
(Appendix 6)
The AD converter circuit according to appendix 4, wherein gain adjustment of the one or more second stage amplifiers is performed by adjusting a size of a transistor forming the second stage amplifier.
(Appendix 7)
The AD converter circuit according to appendix 6, wherein the transistor whose size is adjusted includes a plurality of child transistors connected in parallel, and is adjusted by adjusting the number of child transistors that operate.
(Appendix 8)
The AD converter circuit according to appendix 4, wherein gain adjustment of the one or more second stage amplifiers is performed by adjusting a current amount of a current source of the second stage amplifier.

31 AD converter circuit (ADC)
51 Reference Voltage Generation Circuit 52 Comparison Circuit Unit 53 Encoder 54N, 54 (N + 2) First-stage Amplifier Circuit (Amplifier)
55N, 55 (N + 1), 55 (N + 2) Latch 56 (N + 1) Second stage amplifier 57 (N + 1) Gain adjustable second stage amplifier 60 Decoder 70 Current mirror circuit

Claims (5)

A plurality of first stage amplifiers that amplify a difference voltage between a voltage of the input signal and a plurality of reference voltages having different voltage values in order, and having an order corresponding to the order of the voltage values of the plurality of reference voltages;
One or more second-stage amplifiers that amplify a difference voltage between outputs of two first-stage amplifiers adjacent to the plurality of first-stage amplifiers;
An AD converter comprising: an encoder that calculates a value indicating a level of the voltage of the input signal with respect to the plurality of reference voltages from outputs of the plurality of first-stage amplifiers and the one or more second-stage amplifiers. circuit. A plurality of latches for latching output values of the plurality of first stage amplifiers and the one or more second stage amplifiers, respectively, and outputting the latched values;
The AD converter circuit according to claim 1, wherein the encoder calculates a value indicating a level of a voltage of the input signal with respect to the plurality of reference voltages from output values of the plurality of latches.   The AD conversion circuit according to claim 2, further comprising a reference voltage generation circuit that generates the plurality of reference voltages.   The AD converter circuit according to claim 2, wherein the one or more second-stage amplifiers are capable of gain adjustment. The plurality of first stage amplifiers, the one or more second stage amplifiers, and the plurality of latches operate in synchronization with a clock signal,
The plurality of first-stage amplifiers and the one or more second-stage amplifiers perform an amplification operation when the clock signal has one logic value,
The plurality of latches respectively latch values of outputs of the plurality of first stage amplifiers and the one or more second stage amplifiers when the clock signal changes from the one logic value to the other logic value. 5. The AD conversion circuit according to any one of 2 to 4.

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