JP2011029503A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a gate-all-around transistor by leveling currents respectively flowing to a plurality of channels of the gate-all-around transistor. <P>SOLUTION: A semiconductor device includes a semiconductor substrate, a source-drain region where a plurality of layered structures each having a second semiconductor layer formed on a first semiconductor layer over the semiconductor substrate at a constant interval are stacked, a plurality of channel regions formed in a wire shape so as to connect identical layers of second semiconductor layers, and a gate electrode 103 formed via a gate insulating film 110 so as to cover the plurality of channel regions, wherein the channel width of a channel region decreases with the distance from the semiconductor substrate and the film thickness of a channel region of a second semiconductor layer increases with the distance from the semiconductor substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a GAA structure, and more particularly to a semiconductor device in which a plurality of channel regions are formed on the same area.

  In recent years, the miniaturization of MOS transistors has progressed with the increase in functionality and integration of semiconductor integrated circuits. However, the conventional MOS transistor has a small on / off ratio. Therefore, in order to obtain a desired on-state current, it is necessary to set the width of the gate electrode to a predetermined value or more, or to form a plurality of gate electrodes on the same plane. In these methods, the area occupied by the field effect transistor increases, and there is a problem in improving the circuit density.

  Therefore, as a structure for obtaining a desired on-current, for example, a gate all around (hereinafter abbreviated as GAA) transistor is considered (for example, see Patent Document 1).

  The GAA transistor is formed so that the gate electrode wraps around the channel region. Therefore, when a voltage is applied to the gate electrode, the electric field tends to concentrate on the channel region, and the on / off ratio of the switching current can be set large. In addition, a large number of channel regions can be formed over the same area, and the on-state current can be increased.

  When a large number of channel regions are formed in the GAA transistor, a processing conversion difference occurs between the upper layer and the lower layer channel regions, so that the channel width of the channel region varies. Therefore, the resistance values of the channels when the GAA transistor is turned on are different. Therefore, the current does not flow uniformly in each channel, and the current concentrates on the channel having a low resistance value. As a result, there is a problem that it is impossible to obtain an on-current that is assumed when currents flow equally in all channels.

Japanese Patent Laying-Open No. 2005-229107

  An object of the present invention is to provide a semiconductor device capable of making currents flowing through a plurality of channels of a gate all-around transistor uniform and improving the reliability of the gate all-around transistor.

  A semiconductor device according to an example of the present invention includes a semiconductor substrate and a source in which a plurality of stacked structures in which a second semiconductor layer is formed on a first semiconductor layer formed at a predetermined interval on the semiconductor substrate are stacked. A drain region, a plurality of channel regions formed in a wire shape so as to connect the same layers of the second semiconductor layers, and a gate insulating film formed so as to enclose each of the plurality of channel regions; A gate electrode formed through the gate insulating film so as to enclose each of the plurality of channel regions, and the channel width of the channel region is formed so as to be farther from the semiconductor substrate, The film thickness of the semiconductor layer and the channel region is formed wider as the distance from the semiconductor substrate increases.

  A semiconductor device according to an example of the present invention has a stacked structure in which a semiconductor substrate and a second semiconductor layer made of silicon are formed on a first semiconductor layer formed on the semiconductor substrate at a predetermined interval. A plurality of stacked source / drain regions, a plurality of channel regions formed in a wire shape so as to connect the same layers of the second semiconductor layer, and a plurality of channel regions, respectively. A gate electrode formed through the gate insulating film so as to enclose each of the plurality of channel regions, and the film thickness of the second semiconductor layer increases as the distance from the semiconductor substrate increases. Each of the plurality of channel regions is formed to have a circular cross section in a direction perpendicular to the channel length direction.

  According to the present invention, the current flowing through each of the plurality of channels of the gate all-around transistor is made uniform, and the reliability of the gate all-around transistor is improved.

The top view which shows typically the GAA transistor concerning 1st Embodiment. Sectional drawing of the GAA transistor which followed the II-II line | wire of FIG. 1 concerning 1st Embodiment. Sectional drawing of the GAA transistor which followed the III-III line | wire of FIG. 1 concerning 1st Embodiment. The figure which showed typically the nanowire channel of the GAA transistor concerning 2nd Embodiment. The top view which showed the nanowire channel of the GAA transistor in 2nd Embodiment compared with the prior art example. Sectional drawing along the direction perpendicular | vertical to the channel length direction of the GAA transistor concerning 2nd Embodiment. The bird's-eye view which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. The bird's-eye view which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. The bird's-eye view which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. The bird's-eye view which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. The bird's-eye view which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. The bird's-eye view which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. The bird's-eye view which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. Sectional drawing along the AA of FIG. 13 which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. Sectional drawing along the AA of FIG. 13 which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment. Sectional drawing along the AA of FIG. 13 which shows the manufacturing process of the GAA transistor concerning 3rd Embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

1. Overview
In the example of the present invention, the thickness of the plurality of nanowire channels of the GAA transistor is formed in consideration of the difference in the length of the outer periphery of the upper nanowire channel and the lower nanowire channel. That is, the nanowire channel formed in the lower layer is formed thin, and the nanowire channel formed in the upper layer is formed thick.

  By forming the nanowire channel with different film thicknesses, the outer circumferences of the nanowire channels have the same length. Therefore, variation in the resistance value of the nanowire channel when the GAA transistor is turned on can be suppressed. Therefore, during the operation of the GAA transistor, a current flows uniformly through each nanowire channel. As a result, a predetermined on-current can be obtained. Furthermore, since the current flows uniformly through each nanowire channel, the channel region is uniformly deteriorated and the reliability of the GAA transistor is improved.

2. Embodiment
(1) First Embodiment FIG. 1 is a plan view schematically showing a GAA transistor.

  One GAA transistor 102 is formed in a region surrounded by the element isolation region 101. Two source / drain regions 104 of the GAA transistor 102 are formed at regular intervals. Further, a gate electrode 103 is formed between the source / drain regions 104. Further, in each of the source / drain regions 104, a contact portion 105 for making contact with the wiring layer is formed.

  The gate electrode 103 of the GAA transistor is formed so as to enclose the nanowire channel. Therefore, a nanowire channel whose periphery is covered with the gate electrode 103 is formed in the dotted line region da shown in FIG.

  FIG. 2 is a cross-sectional view of the GAA transistor taken along line II-II in FIG.

In FIG. 2, on a P ⁺ type semiconductor substrate 106, there is a laminated structure in which SiGe (silicon germanium) layers 107a, 107b and 107c and Si (silicon) layers 108a, 108b and 108c are alternately formed. Further, this stacked structure functions as the source / drain region 104 of the GAA transistor. Here, not only the stacked structure of the SiGe layer and the Si layer, but also a stacked structure in which any two of the Si layer, the SiGe layer, the SiC layer, and the SiGeC layer are combined.

  Two such laminated structures are formed at regular intervals. A wire-shaped nanowire channel 109a made of Si (silicon) is formed in a region sandwiched between two Si layers 108a in the stacked structure. Furthermore, wire-like nanowire channels 109b and 109c made of Si are also formed in the region sandwiched between the two Si layers 108b and the region sandwiched between the two Si layers 108c, respectively. The

  Thus, the GAA transistor has a structure having a plurality of channel regions on the same area.

  Further, the gate insulating film 110 is formed so as to cover the opposite side walls of the SiGe layer 107 and the Si layer 108 and enclose each of the nanowire channels 109.

  Further, the gate electrode 103 is formed through the gate insulating film 110 so as to enclose the nanowire channel 109.

  Further, a contact plug 111 is formed on the Si layer 108c.

  An insulating film 112 is formed on the uppermost gate electrode 103, and an insulating film 113 is formed on the side surface. Further, an insulating film 114 is formed so as to cover the insulating film 112 and the insulating film 113.

  FIG. 3 shows a cross-sectional view taken along line III-III in FIG.

  As shown in FIG. 3, for example, the nanowire channel 109c formed in the upper layer has a narrow channel width, and the nanowire channel 109a formed in the lower layer has a wide channel width. Further, the surface area of the upper surface of each nanowire channel 109 is smaller than the surface area of the lower surface.

  This forms a multi-layered Si layer on a silicon substrate and forms a nanowire channel 109 of a GAA transistor from this Si layer. At this time, an opening is formed in the Si layer by etching so as to leave a region to be a nanowire channel. However, this opening has a forward taper shape due to a difference in processing conversion between the upper layer and the lower layer.

  Therefore, when all the Si layers have the same film thickness as in the prior art, the channel width of the upper nanowire channel 109c of the nanowire channel 109 of the GAA transistor is narrower than that of the lower nanowire channel 109a. Therefore, the outer circumference of the upper nanowire channel 109c is shorter than the outer circumference of the lower nanowire channel 109a.

  Therefore, in the first embodiment, the film thickness is formed in consideration of the difference in the outer peripheral length of each nanowire channel 109. That is, the nanowire channel 109 formed in the lower layer is formed thin, and the nanowire channel 109 formed in the upper layer is formed thick.

  By forming in this way, it becomes possible to make the length of the outer periphery of all the nanowire channels 109 equal. Therefore, when a predetermined voltage is applied to the gate electrode 103 of the GAA transistor to turn it on, variations in the nanowire channel resistance value can be reduced. Therefore, during the operation of the GAA transistor, a uniform current flows through each nanowire channel 109, and a predetermined on-current can be obtained.

  Furthermore, since a uniform current flows through each nanowire channel 109, the degradation rate of the nanowire channel 109 becomes equal. Therefore, the reliability of the GAA transistor is improved.

(2) Second Embodiment FIG. 4 schematically shows a nanowire channel of a GAA transistor, and FIG. 5A is a plan view schematically showing only the nanowire channel of a conventional GAA transistor. It is.

  When forming the nanowire channel 109 of the GAA transistor, the Si layer is etched using the RIE method. However, the surface etched by this RIE method has irregularities as shown in FIG. Furthermore, as shown in FIGS. 4 and 5A, the nanowire channel 109 formed by the RIE method is wavy. Carriers in the nanowire channel 109 are scattered due to the unevenness and undulation, and when the GAA transistor is turned on, the value of the current flowing through the nanowire channel 109 decreases. As a result, when the GAA transistor is turned on, there is a problem that the resistance value of each nanowire channel 109 varies depending on the shape of the unevenness and the shape of the undulation.

  Furthermore, when the cross section in the direction perpendicular to the channel length direction of the nanowire channel 109 is a square, the electric field tends to concentrate on the corners. Therefore, a high voltage is applied to the insulating film in the vicinity of the corners, and the possibility of destroying the insulating film is increased. As a result, there is a problem that the reliability of the GAA transistor is lowered.

  FIG. 6 shows a cross-sectional view taken along line III-III in FIG. 1 in the second embodiment. FIG. 5B is a plan view schematically showing only the nanowire channel of the GAA transistor in the second embodiment.

  In the second embodiment, in order to solve the above problem, first, the lengths of the outer peripheries of all the nanowire channels 109 are formed to be equal to each other as in the first embodiment.

After that, for example, annealing is performed in an atmosphere containing H ₂ of about 800 degrees, and the surface of the nanowire channel 109 is migrated. By this process, the cross section of each nanowire channel 109 in the direction perpendicular to the channel length direction is deformed from a square to a circle.

  By re-forming the cross section of each nanowire channel 109 in the direction perpendicular to the channel length direction, irregularities formed by the RIE method can be eliminated. Furthermore, as shown in FIG. 5B, each nanowire channel 109 can be controlled to be formed in a straight line when formed in a circular shape. For this reason, when a predetermined voltage is applied to the gate electrode 103 of the GAA transistor to turn it on, variations in the nanowire channel resistance value can be reduced.

  Furthermore, in the second embodiment, the lengths of the outer peripheries of the nanowire channels 109 are formed to be equal to each other as in the first embodiment. For this reason, when the GAA transistor is turned on, variations in the nanowire channel resistance value can be further reduced. As a result, during the operation of the GAA transistor, a uniform current flows through each nanowire channel 109, and a predetermined on-current can be obtained.

  In addition, since current flows uniformly through each nanowire channel 109, the degradation rate of each nanowire channel 109 is also equal. Furthermore, as shown in FIG. 6, the cross section of each nanowire channel 109 in the direction perpendicular to the channel length direction is circular. For this reason, corner portions are not formed in the nanowire channel 109, and there is no place where the electric field concentrates, so that the breakdown of the gate insulating film is suppressed. As a result, the reliability of the GAA transistor is improved.

(3) Third Embodiment In the third embodiment, an example of a method for manufacturing a GAA transistor according to the second embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 7, P-type impurities are ion-implanted into the semiconductor substrate to form a P ⁺ -type semiconductor substrate 106. This is to prevent the formation of a parasitic channel in the semiconductor substrate. Next, a stacked structure of a SiGe (silicon germanium) layer 201a and a Si (silicon) layer 202a to be a nanowire channel and source / drain is formed by epitaxial growth. Further, the SiGe layer 201b, the Si layer 202b, the SiGe layer 201c, and the Si layer 202c are sequentially formed by epitaxial growth.

  Here, in the manufacturing method of the present embodiment, the case where the laminated structure composed of the SiGe layer and the Si layer is three layers has been described. However, even if a two-layer laminated structure is formed, a multilayered structure having more than three layers is formed. May be formed.

  Next, as shown in FIG. 8, a mask material 203 used as an etching mask for the nanowire channel is formed on the Si layer 202c formed on the top by a plasma CVD method. The mask material 203 is, for example, a laminated film of a silicon oxide film 203b and a silicon nitride film 203a.

  Next, although not shown, patterning is performed so that the silicon oxide film 203b and the silicon nitride film 203a remain in the region where the GAA transistor is to be formed, and an STI (Shallow Trench Isolation) groove is formed by RIE. Thereafter, an element isolation insulating film is embedded in the STI trench by plasma CVD. This element isolation insulating film is, for example, a silicon oxide film. Further, the element isolation insulating film embedded in the STI trench is planarized by CMP to form an element isolation insulating film having an STI structure.

  Thereafter, the silicon nitride film 203a is formed into a desired nanowire pattern by a lithography process and an RIE method.

  Next, as shown in FIG. 9, a mask material 204 used for etching the damascene gate groove is deposited by plasma CVD. The mask material 204 is, for example, a laminated film of a silicon oxide film 204b and a silicon nitride film 204a.

  Next, as shown in FIG. 10, after the silicon nitride film 204a is selectively etched by a lithography process and RIE, a gate electrode is formed by selectively etching the silicon oxide film 203b and the silicon oxide film 204b. Forming a gate damascene trench.

  At this time, the silicon oxide film 203b and the silicon nitride film 203a formed over the region where the nanowire channel is to be formed are selectively left.

  Next, as shown in FIG. 11, in order to form a nanowire channel, the SiGe layers 201b and 201c and the Si layers 202a, 202b, and 202c are formed in a wire shape using the silicon oxide film 203b and the silicon oxide film 204b as a mask. Etching is performed sequentially.

  At this time, when the Si layer 202a is etched, over-etching is performed to selectively remove the silicon nitride film 203a and the silicon oxide film 203b on the Si layer 202 where the nanowire channel is to be formed. 204b is removed.

  When the Si layers 202a, 202b, and 202c are sequentially etched, an etching process conversion difference occurs between the upper Si layer 202c and the lower Si layer 202a. For this reason, the groove formed by this etching has a forward tapered shape. Therefore, the cross section along the direction perpendicular to the channel length direction of the Si layer 202 in which the nanowire channel is formed becomes a trapezoid.

Also, as shown in FIG. 12, the SiGe layers 201a, 201b, 201c formed under the Si layers 202a, 202b, 202c for forming the nanowire channel are isotropically etched. Here, when dry etching is performed as isotropic etching, for example, a gas containing chlorine trifluoride (ClF ₃ ) may be used. When wet etching is performed, for example, hydrofluoric acid may be used as an etchant. At this time, etching is performed so that the entire surfaces of the Si layers 207a, 207b, and 207c where the nanowire channel is formed are exposed.

  At this time, each of the Si layers 207a, 207b, and 207c in which the nanowire channel is formed has a square cross section in a direction perpendicular to the channel length direction of the Si layer 202.

Next, as shown in FIG. 13, in order to make the cross section in the direction perpendicular to the channel length direction of each of the Si layers 207a, 207b, and 207c in which the shape nanowire channel is formed, Annealing is performed under _two atmospheres.

  Further, after the cross section in the direction perpendicular to the channel length direction of the Si layers 207a, 207b, and 207c in which the nanowire channel is formed is formed in a circular shape, a P-type impurity is ion-implanted obliquely into the region where the nanowire channel is formed In addition, an annealing process for crystal recovery may be added.

  FIG. 14 to FIG. 17 thereafter show sectional views along the line AA in FIG.

Next, as shown in FIG. 14, for example, in a mixed gas atmosphere of nitrogen, oxygen, and hydrogen chloride (N ₂ , O ₂ , HCl), heat treatment is performed at 900 degrees to form silicon that functions as a gate insulating film, for example. An oxide film 208 is formed.

  Next, as shown in FIG. 15, a metal compound 209 is embedded in the gate damascene trench by a metal CVD method. The metal compound 209 is made of, for example, a compound of titanium nitride and tungsten. Thereafter, the metal compound 209 is planarized by a CMP method. Subsequently, a recess is formed on the metal compound 209 by the RIE method. Further, the silicon nitride film 210 and the α-silicon layer 211 are formed in the recess by the CVD method. Thereafter, the α-silicon layer 211 is planarized by CMP.

  Next, as shown in FIG. 16, the mask material 203 and the silicon oxide film 204b are selectively removed using the α-silicon layer 211 as a mask. Thereafter, the α-silicon layer 211 is selectively removed.

  Next, an insulating film is formed on the sidewall of the metal compound by a normal process. Further, an insulating film is formed on the Si layer 202c and the silicon nitride film 210 by a normal process. Further, a contact hole is formed in the insulating film formed on the upper part of the Si layer 202c by a normal process to form a contact plug, thereby completing the GAA transistor shown in FIG.

4). Conclusion
According to the present invention, the current flowing through each of the plurality of channels of the gate all-around transistor is made uniform, and the reliability of the gate all-around transistor is improved.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

101: element isolation insulating film, 102: GAA transistor, 103: gate electrode, 104: source / drain region, 105: contact portion, 106: P ⁺ type semiconductor substrate, 107: SiGe layer, 108: Si layer, 109: nano Wire channel, 110: gate insulating film, 111: contact plug, 112: insulating film, 113: insulating film: 114: insulating film, 201: SiGe layer, 202: Si layer, 203: mask material, 203a: silicon nitride film, 203b: Silicon oxide film, 204: Mask material, 204a: Silicon nitride film, 204b: Silicon oxide film, 207: Si layer, 208: Silicon oxide film, 209: Metal compound, 210: Silicon nitride film, 211: α-silicon layer.

Claims (5)

A semiconductor substrate;
A source / drain region in which a plurality of stacked structures in which a second semiconductor layer is formed on a first semiconductor layer formed at a predetermined interval on the semiconductor substrate are stacked;
A plurality of channel regions formed in a wire shape so as to connect between the same layers of the second semiconductor layer;
A gate insulating film formed to enclose each of the plurality of channel regions;
A gate electrode formed through the gate insulating film so as to enclose each of the plurality of channel regions,
The channel width of the channel region is formed narrower as the distance from the semiconductor substrate increases.
2. The semiconductor device according to claim 1, wherein the second semiconductor layer and the channel region are formed wider as they are separated from the semiconductor substrate.   2. The semiconductor device according to claim 1, wherein each of the plurality of channel regions has a surface area on a lower surface larger than a surface area on an upper surface.   4. The semiconductor device according to claim 1, wherein each of the first and second semiconductor layers is made of any one of Si, SiGe, SiC, and SiGeC. 5. A semiconductor substrate;
A source / drain region in which a plurality of stacked structures in which a second semiconductor layer is formed on a first semiconductor layer formed at regular intervals on the semiconductor substrate are stacked;
A plurality of channel regions formed in a wire shape so as to connect each of the same layers of the second semiconductor layers;
A gate insulating film formed to enclose each of the plurality of channel regions;
A gate electrode formed through the gate insulating film so as to enclose each of the plurality of channel regions,
The film thickness of the second semiconductor layer is formed so as to increase away from the semiconductor substrate,
Each of the plurality of channel regions has a circular cross section in a direction perpendicular to the channel length direction.   The semiconductor device according to claim 4, wherein each of the first and second semiconductor layers is made of any one of Si, SiGe, SiC, and SiGeC.

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