JP2011019189A - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit in which a data signal is configured as a differential signal without increasing the number of data signal lines is provided.
A semiconductor integrated circuit includes two data input / output terminals, a data input circuit for inputting data via the two data input / output terminals, and a data output for outputting data via the two data input / output terminals. One of the data input circuit and the data output circuit transmits two single-phase signals using the two data input / output terminals as independent terminals, and the data input circuit and the data output circuit The other circuit transmits a pair of differential signals using two data input / output terminals as a pair of terminals.
[Selection] Figure 1

Description

  The present disclosure relates generally to semiconductor integrated circuits, and more particularly to memory circuits.

  In a memory device such as a clock synchronous memory, a data strobe signal is transmitted and received together with a data signal, and the data capture timing of the data signal is controlled by the data strobe signal, thereby performing high-speed and reliable data transmission. Recently, with the increase in data transfer speed, considering the ease of timing design and the influence of noise, the data strobe signal is composed of a differential signal and the data signal is composed of a single-phase signal. . The noise includes switching noise generated when the input / output circuit is switched in the logic LSI (Large Scale Integration) circuit and the memory circuit, and crosstalk noise generated between adjacent signal wirings. Variations in the propagation delay of the data signal occur due to the influence of the noise thus generated. In the case of a differential signal, for example, switching noise generated inside the LSI can be regarded as substantially equal to a pair of two signal lines, and since these two signal lines are adjacent signal lines, crosstalk also occurs mutually. It can be regarded as equivalent. Therefore, by using the differential signal, the influence of relative noise is canceled out, and a circuit configuration strong against the influence of noise can be obtained.

  The data strobe signal is a signal for determining timing, and a pair of data strobe signal lines may be provided for the entire data signal. On the other hand, for data signals, there are as many signal lines as there are data bits. Therefore, although the data strobe signal can be configured as a differential signal, if the data signal is configured as a differential signal, the number of signal lines becomes enormous, which is not realistic. For this reason, the data signal is usually composed of a single-phase signal.

  In the case of a differential signal, the reference point for signal determination is a cross point between two differential signals, and in the case of a single-phase signal, the reference point for signal determination is a cross point between a single-phase signal and a reference potential. In this way, the differential signal and the single-phase signal have different signal determination reference points and have different timing characteristics due to the influence of noise or the like. For this reason, when considering the delay of signal propagation, it becomes difficult to match the timing characteristics of the data signal that is a single-phase signal and the data strobe signal that is a differential signal, and timing design becomes difficult.

  Accordingly, a memory circuit and system that match the timing characteristics of the data signal and the data strobe signal that is a differential signal are desired. For this purpose, it is desirable that the data signal can be configured as a differential signal without increasing the number of data signal lines. There are also memory configurations that do not use a data strobe signal. In such a configuration, it is preferable from the viewpoint of noise reduction if the data signal can be configured as a differential signal without increasing the number of data signal lines.

JP 2005-32417 A JP-A-6-224889 JP 2005-535035 A

  In view of the above, a semiconductor integrated circuit in which a data signal is configured as a differential signal without increasing the number of data signal lines is desired.

  The semiconductor integrated circuit includes two data input / output terminals, a data input circuit that inputs data via the two data input / output terminals, and a data output circuit that outputs data via the two data input / output terminals. One of the data input circuit and the data output circuit transmits two single-phase signals using the two data input / output terminals as independent terminals, and the data input circuit and the data The other circuit of the output circuit transmits a pair of differential signals using the two data input / output terminals as a pair of terminals.

  According to at least one embodiment of the present disclosure, a memory system in which a data signal is configured as a differential signal can be configured without increasing the number of data signal lines.

It is a figure which shows an example of a structure of a memory system. It is a figure which shows an example of the specific structure of the logic circuit of a memory system, and a memory circuit. It is a figure which shows an example of a structure of the input / output part of the data signal of a logic circuit. It is a figure which shows an example of a structure of the input / output part of the data signal of a memory circuit. It is a figure which shows an example of a structure of the input circuit of a single phase signal. It is a figure which shows an example of a structure of the output circuit of a single phase signal. It is a figure which shows an example of a structure of the input circuit of a differential signal. It is a figure which shows an example of a structure of the output circuit of a differential signal. It is a figure which shows the structure of a signal termination | terminus. FIG. 10 is a timing diagram illustrating a read operation of the memory circuit. FIG. 10 is a timing diagram illustrating a write operation of the memory circuit. FIG. 10 is a timing diagram illustrating a write operation and a subsequent read operation of the memory circuit. FIG. 10 is a timing diagram illustrating a read operation and a subsequent write operation of the memory circuit. FIG. 10 is a timing chart showing an operation when a write operation is continuously executed. FIG. 6 is a timing chart showing an operation when three write operations are executed in succession.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a memory system. The memory system shown in FIG. 1 includes a logic circuit 10 and a memory circuit 11. The memory circuit 11 is connected to the logic circuit 10 via a plurality of signal lines that are wiring on a printed circuit board. The logic circuit 10 includes a clock generation circuit 12, a clock output buffer 13, and a plurality of signal input / output terminals 14-1 to 14-12. The memory circuit 11 also includes an internal clock generation circuit 15, a clock input buffer 16, and a plurality of signal input / output terminals 17-1 to 17-12.

  The clock generation circuit 12 generates a clock signal. Based on the clock signal generated by the clock generation circuit 12, the clock output buffer 13 generates a pair of differential clock signals CLK and / CLK and sends them out from the signal input / output terminals 14-1 and 14-2. The differential clock signals CLK and / CLK are input to the clock input buffer 16 via the signal input / output terminals 17-1 and 17-2, and the reception clock signal is supplied to the internal clock generation circuit 15. The internal clock generation circuit 15 of the memory circuit 11 generates a clock signal used inside the memory circuit 11 based on the received clock signal.

  Signal input / output terminals 14-11 and 14-12 of the logic circuit 10 are terminals for inputting / outputting data strobe signals DQS0 and / DQS0 which are differential signals to the logic circuit 10. Signal input / output terminals 17-11 and 17-12 of the memory circuit 11 are terminals for inputting / outputting data strobe signals DQS0 and / DQS0, which are differential signals, to / from the memory circuit 11. In the case of writing data to the memory circuit 11, data strobe signals DQS 0 and / DQS 0 are transmitted from the logic circuit 10 to the memory circuit 11. In the case of reading data from the memory circuit 11, data strobe signals DQS 0 and / DQS 0 are transmitted from the memory circuit 11 to the logic circuit 10.

  The signal input / output terminals 14-3 to 14-10 are data input / output terminals of the logic circuit 10. Signal input / output terminals 17-3 to 17-10 are data input / output terminals of the memory circuit 11. Data transmitted through these data input / output terminals has a predetermined timing relationship with the data strobe signals DQS0 and / DQS0.

  Here, for example, paying attention to the signal input / output terminals 14-3 and 14-4 and the signal input / output terminals 17-3 and 17-4, these two data input / output terminals on the logic circuit 10 side and these on the memory circuit 11 side. Consider two data signal lines connecting between two data input / output terminals. At the time of data reading, these two data signal lines are used as independent signal lines, and two single-phase signals are transmitted from the memory circuit 11 to the logic circuit 10 as read data DQ0 and DQ1. At the time of data writing, a pair of differential signals DQ0 and / DQ0 are written using these two data signal lines as a pair of signal lines, and transmitted from the logic circuit 10 to the memory circuit 11. Furthermore, the pair of differential signals DQ1 and / DQ1 are transmitted from the logic circuit 10 to the memory circuit 11 as write data at a timing different from DQ0 and / DQ0. In this way, the 2-bit write data DQ0 and DQ1 are transmitted as a differential signal twice and transmitted in a time division manner. Thus, in the case of a data read operation, two single-phase signals are transmitted using two data input / output terminals as independent terminals, and in the case of a data write operation, two data input / output terminals are transmitted. A pair of differential signals are transmitted using the terminals as a pair of terminals.

  The data transmission is performed in the same manner for each of the data signals DQ0 to DQ7. That is, in a plurality of data signal lines connecting between the signal input / output terminals 14-3 to 14-10 and the signal input / output terminals 17-3 to 17-10, the number of bits equal to the number of the plurality of data signal lines. Read data DQ0 to DQ7 are transmitted as a single-phase signal at a time. Also, write data DQ0 to DQ7 having the same number of bits as the number of the plurality of data signal lines are divided into two times as differential signals and transmitted by time division. In the first transmission, for example, DQ0 and / DQ0, DQ2 and / DQ2, DQ4 and / DQ4, DQ6 and / DQ6 are transmitted, and in the second transmission, for example, DQ1, and / DQ1, DQ3 and / DQ3, DQ5 and / DQ5, DQ7 and / DQ7 may be transmitted.

  With the configuration shown in FIG. 1, the number of signal lines between the logic circuit 10 and the memory circuit 11 and the number of pins of the logic circuit 10 and the memory circuit 11 are equal to the conventional configuration. That is, noise resistance can be improved by transmitting a data signal as a differential signal without increasing the number of signal lines or the number of pins. In addition, by making the data signal have a differential signal configuration similar to that of the data strobe signal, the timing characteristics of the data signal and the data strobe signal can be matched, and the timing design is facilitated. Further, as will be described later, by using the latency at the time of writing, write data can be transmitted using a cycle that has not been conventionally used for data transmission.

  FIG. 2 is a diagram illustrating an example of a specific configuration of the logic circuit 10 and the memory circuit 11 of the memory system. The logic circuit 10 includes a PLL & logic circuit 20, a clock output circuit 21, a counter 22, an output register 23, an input register 24, a data input / output circuit 25, a data strobe input / output circuit 26, a logic circuit core 27, an address output circuit 28, and A command output circuit 29 is included. The memory circuit 11 includes a clock generation circuit 30, a clock input circuit 31, a counter 32, an output register 33, an input register 34, a data input / output circuit 35, a data strobe input / output circuit 36, an address input circuit 37, an address decoder 38, a command An input circuit 39, a command decoder 40, a data amplifier 41, and a memory core 42 are included.

  The logic circuit core 27 of the logic circuit 10 controls data read and write operations in the memory system shown in FIG. 2 by controlling the operation of each part of the logic circuit 10. The address generated by the logic circuit core 27 is supplied to the memory circuit 11 via the address output circuit 28. A command generated by the logic circuit core 27 is supplied to the memory circuit 11 via the command output circuit 29. Further, data generated by the logic circuit core 27 is supplied to the memory circuit 11 via the output register 23 and the data input / output circuit 25.

  The command input circuit 39 of the memory circuit 11 receives the command supplied from the logic circuit 10 and supplies the received command to the command decoder 40. The command decoder 40 decodes the command and generates various control signals and timing signals such as a write signal, a read signal, and a precharge signal according to the decoding result. These control signals and timing signals are supplied to each circuit portion of the memory circuit 11. The operation of each circuit portion of the memory circuit 11 is executed according to the control signal and the timing signal.

  The address input circuit 37 receives an address from the logic circuit 10 and supplies the received address to the address decoder 38. The address decoder 38 decodes the address and supplies an address decode signal to the memory core 42.

  In the memory core 42, a plurality of memory cells are arranged in a matrix in the row direction and the column direction to form a cell array, and data is stored in each memory cell. In the memory core 42, a plurality of word lines are arranged corresponding to a plurality of row addresses, and a plurality of memory cells are connected to each word line. A plurality of bit lines are arranged in the direction in which column addresses are arranged, and each bit line is connected to a memory cell.

  In the memory core 42, the word line and the column selection line specified by the address decode signal supplied from the address decoder 38 are activated. Data of the memory cell connected to the activated word line is read out to the bit line and amplified by the sense amplifier. In the read operation, the data amplified by the sense amplifier is selected by the activated column selection line, and is output to the outside of the memory circuit 11 through the data amplifier 41, the output register 33, and the data input / output circuit 35. . In the case of a write operation, write data supplied from outside the memory circuit 11 via the data input / output circuit 35, the input register 34, and the data amplifier 41 is a column address sense amplifier selected by an activated column selection line. Is written to. This write data and data to be read from the memory cell and rewritten are written into the memory cell connected to the activated word line.

  The PLL & logic circuit 20 of the logic circuit 10 corresponds to the clock generation circuit 12 of FIG. 1, includes a PLL circuit and other logic circuits, and generates a clock signal CLK and a data strobe signal DQS. The clock signal CLK and the data strobe signal DQS are generated so as to have a predetermined phase relationship with each other. The clock signal CLK generated by the PLL & logic circuit 20 is transmitted to the memory circuit 11 via the clock output circuit 21. The clock signal CLK may be further supplied to the counter 22. The data strobe signal DQS generated by the PLL & logic circuit 20 is supplied to the memory circuit 11 via the data strobe input / output circuit 26. The clock input circuit 31 of the memory circuit 11 receives the clock signal CLK supplied from the logic circuit 10 and supplies the received clock signal CLK to the clock generation circuit 30. The clock generation circuit 30 generates an internal clock signal and a data strobe signal DQS based on the reception clock signal CLK. Each internal circuit of the memory circuit 11 operates based on an internal clock signal generated by the clock generation circuit 30. The data strobe signal DQS generated by the clock generation circuit 30 is sent to the logic circuit 10 via the data strobe input / output circuit 36 during the data read operation. The data strobe signal DQS generated by the clock generation circuit 30 is supplied to the counter 32 for data reading operation.

  The counter 22 of the logic circuit 10 operates based on the clock signal CLK or the data strobe signal DQS generated by the PLL & logic circuit 20, and generates a timing signal. In response to the timing signal output from the counter 22, the output register 23 outputs the retained data during the data write operation. The data output from the output register 23 is supplied to the memory circuit 11 through the data input / output circuit 25 as write data DQ. The data input / output circuit 35 of the memory circuit 11 receives the write data DQ supplied from the logic circuit 10 and supplies the received data to the input register 34. The counter 32 of the memory circuit 11 operates based on the data strobe signal DQS received from the logic circuit 10 via the data strobe input / output circuit 36, and generates a timing signal for latching received data. The input register 34 latches the received data from the data input / output circuit 35 according to the timing signal generated by the counter 32. The data latched by the input register 34 is supplied to the data amplifier 41 at a predetermined timing.

  During the data read operation, data read from the memory core 42 is supplied to the output register 33 via the data amplifier 41 and latched. The counter 32 of the memory circuit 11 operates based on the data strobe signal DQS generated by the clock generation circuit 30 and generates a timing signal for outputting read data. The output register 33 outputs retained data according to the timing signal generated by the counter 32. The data output from the output register 33 is supplied to the logic circuit 10 as read data DQ via the data input / output circuit 35. The data input / output circuit 25 of the logic circuit 10 receives the read data DQ supplied from the memory circuit 11 and supplies the received data to the input register 24. The counter 22 of the logic circuit 10 operates based on the data strobe signal DQS received from the memory circuit 11 via the data strobe input / output circuit 26, and generates a timing signal for latching received data. The input register 24 latches the received data from the data input / output circuit 25 according to the timing signal generated by the counter 22. The data latched by the input register 24 is supplied to the logic circuit core 27 at a predetermined timing.

  Transmission of the data strobe signal DQS between the data strobe input / output circuit 26 and the data strobe input / output circuit 36 is performed as transmission using a differential signal. Further, the transmission of the data signal DQ between the data input / output circuit 25 and the data input / output circuit 35 is performed as a differential signal transmission in the write operation, and a single-phase signal in the read operation. Done as a transmission. That is, in the read operation, two single-phase signals are transmitted using the two data input / output terminals as independent terminals, and in the write operation, the two data input / output terminals are paired with a pair of terminals. Used to transmit a pair of differential signals.

  The logic circuit 10 and the memory circuit 11 each include an output register 23 and an input register 34 that store at least 2-bit data. During the write operation, the 2-bit data stored in the output register 23 is transmitted from the data input / output circuit 25 in a time-sharing manner as two transmissions using a pair of differential signals. The 2-bit data received by the data input / output circuit 35 in a time division manner as two transmissions using a pair of differential signals is stored in parallel in the input register 34. Data stored in parallel in the input register 34 is collectively supplied to the memory core 42 via the data amplifier 41. The above 2-bit operation is similarly performed for each pair of data signals DQ. That is, if the data signal DQ is 8 bits, the 8-bit data stored in the output register 23 is transmitted from the data input / output circuit 25 in a time division manner as two transmissions using four pairs of differential signals. The 8-bit data received by the data input / output circuit 35 in a time division manner as two transmissions using four pairs of differential signals is stored in the input register 34 in parallel. In the case of burst transmission, the above transmission is repeatedly performed as will be described later.

  FIG. 3 is a diagram illustrating an example of the configuration of the input / output portion of the data signal DQ of the logic circuit 10. In FIG. 3, the same components as those of FIG. 2 are referred to by the same numerals. FIG. 3 shows the input / output portions of the data signals DQn and DQn + 1 for the two data input / output terminals 50 and 51. For example, if the data signal DQ is 8 bits wide, a configuration similar to that shown in FIG. 3 may be provided for each pair of data signals DQ1 and DQ2, DQ3 and DQ4, DQ5 and DQ6, DQ7 and DQ8. The counter circuit 22-1 and the inverters 22-2 to 22-4 correspond to the counter 22 in FIG. The register groups 24-1 and 24-2 and the switch circuits 24-3 to 24-10 correspond to the input register 24 in FIG. The register group 23-1 and the switch circuits 23-2 to 23-11 correspond to the output register 23 in FIG. The input circuits 25-1 and 25-2 and the differential signal output circuit 25-3 correspond to the data input / output circuit 25 in FIG. The output control signal shown in FIG. 3 is an output enable signal that indicates an output state. The input control signal is an input enable signal that indicates an input state.

  Each switch circuit shown in FIG. 3 becomes conductive when the timing signal from the counter circuit 22-1 is asserted, and becomes non-conductive when the timing signal from the counter circuit 22-1 is negated. At the time of reading data from the memory circuit 11, the counter circuit 22-1 generates a timing signal in accordance with the data strobe signal DQS received from the memory circuit 11, and sequentially turns on the switch circuits 24-3 to 24-6. . Thus, the four single-phase signals input from the data input / output terminal 50 via the input circuit 25-1 are sequentially stored as data DO01 to DO04 in the register group 24-1. In this example, a burst length of 4 is assumed, and data having a number of bits equal to the burst length is stored in the register group 24-1. Similarly, four single-phase signals input from the data input / output terminal 51 via the input circuit 25-2 are sequentially stored as data DO11 to DO14 in the register group 24-2.

  At the time of data writing to the memory circuit 11, the counter circuit 22-1 generates a timing signal in accordance with the clock signal CLK or the data strobe signal generated internally by the logic circuit 10, and the switch circuits 23-3 to 23-7 are connected. Sequentially turn on. At this time, the switch circuits 23-2 and 23-3 are set to a conductive state and a non-conductive state, respectively. As a result, the data DI01 to DI04 stored in the register group 23-1 are sequentially sent out as differential signals from the data input / output terminals 50 and 51 via the differential signal output circuit 25-3. In this example, a burst length of 4 is assumed, and data having a number of bits equal to the burst length is transmitted from the differential signal output circuit 25-3. Next, the switch circuits 23-2 and 23-3 are set to a non-conductive state and a conductive state, respectively, and the switch circuits 23-8 to 23-11 are sequentially turned on. As a result, the data DI11 to DI14 stored in the register group 23-1 are sequentially sent out as differential signals from the data input / output terminals 50 and 51 via the differential signal output circuit 25-3.

  FIG. 4 is a diagram illustrating an example of the configuration of the input / output portion of the data signal DQ of the memory circuit 11. 4, the same components as those in FIG. 2 are referred to by the same numerals. FIG. 4 shows the input / output portions of the data signals DQn and DQn + 1 for the two data input / output terminals 52 and 53. For example, if the data signal DQ is 8 bits wide, a configuration similar to that shown in FIG. 4 may be provided for each pair of data signals DQ0 and DQ1, DQ2 and DQ3, DQ4 and DQ5, DQ6 and DQ7. The counter circuit 32-1 and the inverters 32-2 to 32-4 correspond to the counter 32 in FIG. The register group 34-1, the data write switch 34-2, and the switch circuits 34-3 to 34-10 correspond to the input register 34 in FIG. The register group 33-1 and the switch circuits 33-2 to 33-9 correspond to the output register 33 in FIG. The input circuit 35-1 and the output circuits 35-2 and 35-3 correspond to the data input / output circuit 35 of FIG. The output control signal shown in FIG. 4 is an output enable signal that indicates an output state. The input control signal is an input enable signal that indicates an input state.

  Each switch circuit shown in FIG. 4 becomes conductive when the timing signal from the counter circuit 32-1 is asserted, and becomes non-conductive when the timing signal from the counter circuit 32-1 is negated. When reading data from the memory circuit 11, the counter circuit 32-1 generates a timing signal according to the data strobe signal DQS generated inside the memory circuit 11. As a result, the switch circuits 33-2 to 33-5 are sequentially turned on, and at the same time, the switch circuits 33-6 to 33-9 are sequentially turned on. The 4-bit data DO01 to DO04 supplied from the data amplifier 41 is sent out of the memory circuit 11 from the register group 33-1 via the output circuit 35-2 and the data input / output terminal 52. At the same time, the 4-bit data DO11 to DO14 supplied from the data amplifier 41 is sent out of the memory circuit 11 from the register group 33-1 via the output circuit 35-3 and the data input / output terminal 53. In this example, a burst length of 4 is assumed, and data having a number of bits equal to the burst length is transmitted from the data input / output terminals 52 and 53.

  At the time of writing data to the memory circuit 11, the counter circuit 32-1 generates a timing signal according to the data strobe signal DQS received from the logic circuit 10, and sequentially turns on the switch circuits 34-3 to 34-6. . As a result, data received as differential signals via the data input / output terminals 52 and 53 and converted into single-phase signals by the input circuit 35-1 are stored as data DI01 through DI04 in the register group 34-1. In this example, a burst length of 4 is assumed, and data having a number of bits equal to the burst length is stored in the register group 34-1. Next, the switch circuits 34-7 to 34-10 are sequentially turned on in accordance with the timing signal generated by the counter circuit 32-1. As a result, the data received as a differential signal via the data input / output terminals 52 and 53 and converted into a single-phase signal by the input circuit 35-1 is stored as data DI11 to DI14 in the register group 34-1.

  FIG. 5 is a diagram illustrating an example of the configuration of a single-phase signal input circuit. The circuit shown in FIG. 5 is used as the input circuits 25-1 and 25-2 in FIG. 3, for example. The input circuit shown in FIG. 5 includes PMOS transistors 51 and 52, NMOS transistors 53 to 55, and an inverter 56. The PMOS transistors 51 and 52 and the NMOS transistors 53 to 55 constitute a differential amplifier. The differential amplifier operates when an input enable signal applied to the gate of the NMOS transistor 55 is asserted. A single-phase input data signal is applied to the gate of the NMOS transistor 53 which is one end of the differential input. A reference voltage VREF is applied to the gate of the NMOS transistor 54 which is the other end of the differential input. A signal corresponding to the magnitude relationship between the signal voltage of the input data signal and the reference voltage VREF is output from the inverter 56 by the differential amplifier of FIG.

  FIG. 6 is a diagram illustrating an example of the configuration of a single-phase signal output circuit. The circuit shown in FIG. 6 is used as, for example, the output circuits 35-2 and 35-3 in FIG. The output circuit shown in FIG. 6 includes a PMOS transistor 61, an NMOS transistor 62, inverters 63 and 64, and NAND circuits 65 and 66. When the output enable signal is asserted, the circuit of FIG. 6 outputs a HIGH or LOW single-phase signal corresponding to the data signal Data from an output terminal that is a connection point between the PMOS transistor 61 and the NMOS transistor 62.

  FIG. 7 is a diagram illustrating an example of a configuration of a differential signal input circuit. The circuit shown in FIG. 7 is used as, for example, the input circuit 35-1 shown in FIG. The input circuit shown in FIG. 7 includes PMOS transistors 71 and 72, NMOS transistors 73 to 75, and an inverter 76. The PMOS transistors 71 and 72 and the NMOS transistors 73 to 75 constitute a differential amplifier. The differential amplifier operates when an input enable signal applied to the gate of the NMOS transistor 75 is asserted. The positive phase signal Diff_P of the differential data signal is applied to the gate of the NMOS transistor 73 which is one end of the differential input. The negative phase signal Diff_N of the differential data signal is applied to the gate of the NMOS transistor 74 which is the other end of the differential input. With the differential amplifier of FIG. 7, a signal corresponding to the magnitude relationship between the two differential input signals is output from the inverter 76.

  FIG. 8 is a diagram illustrating an example of a configuration of a differential signal output circuit. The circuit shown in FIG. 8 is used as, for example, the differential signal output circuit 25-3 in FIG. The output circuit shown in FIG. 8 includes a PMOS transistor 81, an NMOS transistor 82, inverters 83 and 84, NAND circuits 85 and 86, an inverter 87, a PMOS transistor 91, an NMOS transistor 92, inverters 93 and 94, and NAND circuits 95 and 96. Including. When the output enable signal is asserted, the circuit of FIG. 8 outputs a HIGH or LOW positive phase signal Diff_P corresponding to the data signal Data from an output terminal that is a connection point between the PMOS transistor 81 and the NMOS transistor 82. . A LOW or HIGH negative phase signal Diff_N corresponding to the data signal Data is output from an output terminal which is a connection point between the PMOS transistor 91 and the NMOS transistor 92.

  FIG. 9 is a diagram showing the configuration of the signal termination. In the ODT (On Die Termination) function, the signal termination can be controlled for each memory circuit 11 by a control signal (ODTCNTL shown in FIG. 2). That is, on and off of the resistance termination of the memory circuit 11 can be controlled by the control signal. In the configuration shown in FIG. 9, a bridge resistor is formed via the switch 105 on the memory circuit 11 side. On the logic circuit 10 side, a signal is terminated via a resistor on the power supply voltage high potential side and the ground potential side, and on and off of the termination can be controlled by the switches 101 to 104.

  FIG. 9A shows a case where a signal is transmitted from the logic circuit 10 to the memory circuit 11 (that is, in the case of writing). In this case, the termination is turned on in the memory circuit 11 (the switch 105 becomes conductive), and the two data input / output terminals are connected to each other via a resistor. In the logic circuit 10, the termination is turned off (the switches 101 to 104 are turned off), and the two data input / output terminals are separated from the power supply voltage and the ground voltage. As a result, the transmission line is terminated for the transmission of the differential signal.

  FIG. 9B shows a case where a signal is transmitted from the memory circuit 11 to the logic circuit 10 (that is, in the case of reading). In this case, the termination is turned off in the memory circuit 11 (the switch 105 is non-conductive), and the two data input / output terminals are separated from each other. In the logic circuit 10, the terminal is turned on (the switches 101 to 104 are turned on), and each of the two data input / output terminals is connected to the power supply voltage via a resistor and to the ground voltage via a resistor. Thus, the transmission line is terminated for the transmission of each single-phase signal on each signal line.

  FIG. 10 is a timing chart showing a read operation of the memory circuit 11 described above. (A) to (f) show a read operation of a conventional memory circuit in which a data signal is always a single-phase signal for comparison. (G) to (l) show the read operation of the memory circuit 11 in which the data signal at the time of writing is a differential signal.

  (A) shows a clock signal CLK, (b) shows a command signal, and (c) shows differential data strobe signals DQS and / DQS. (D) shows the output timing of the data signal DQn from the output register, (e) shows the output timing of the data signal DQn + 1 from the output register, and (f) shows the read timing of data from the memory cell. (G) shows a clock signal CLK, (h) shows a command signal, and (i) shows differential data strobe signals DQS and / DQS. (J) shows the output timing of the data signal DQn from the output register, (k) shows the output timing of the data signal DQn + 1 from the output register, and (l) shows the data read timing from the memory cell. As shown in FIG. 10, in the case of the read operation, the conventional memory circuit and the memory circuit 11 have the same operation.

  FIG. 11 is a timing chart showing the write operation of the memory circuit 11. (A) to (f) show a write operation of a conventional memory circuit in which the data signal is always a single-phase signal. (G) to (k) show the write operation of the memory circuit 11 in which the data signal at the time of writing is a differential signal.

  (A) shows a clock signal CLK, (b) shows a command signal, and (c) shows differential data strobe signals DQS and / DQS. (D) shows the timing of storing the data signal DQn in the input register, (e) shows the timing of storing the data signal DQn + 1 in the input register, and (f) shows the timing of writing data to the memory cell. Write data DI01 to DI04 and DI11 to DI14 to be applied after a predetermined write latency WL from the write command WRITE are first stored in the input register. When the 4-bit burst writing to the input register is completed, the data in the input register is written into the memory cell.

  (G) shows a clock signal CLK, (h) shows a command signal, and (i) shows differential data strobe signals DQS and / DQS. (J) shows the timing for storing the differential data signals DQn and DQn + 1 in the input register, and (k) shows the timing for writing data to the memory cell. Simultaneously with the write command WRITE, application of the write data DI01 to DI14 to the memory circuit 11 is started, and the write data DI01 to DI14 are first stored in the input register. When the 4-bit burst write to the input register is completed twice, that is, when the 4-bit burst write to DQ and the 4-bit burst write to DQ + 1 are completed, the data of the input register is written to the memory cell. As described above, the memory circuit 11 performs data transmission of a write differential signal in a cycle in which a conventional data transmission period is a blank period without data transmission.

  FIG. 12 is a timing diagram showing a write operation and a subsequent read operation of the memory circuit 11. (A) to (f) show the operation of the conventional memory circuit. (G) to (k) show the operation of the memory circuit 11. A write operation is executed in the same manner as the write operation shown in FIG. 11, and then a read operation is executed in the same manner as the read operation shown in FIG. The timing at which the write operation to the memory cell in the write operation ends is the same in the conventional memory circuit and the memory circuit 11. Therefore, the timing of the read operation subsequent to the write operation is the same between the conventional memory circuit and the memory circuit 11.

  FIG. 13 is a timing chart showing a read operation and a subsequent write operation of the memory circuit 11. (A) to (f) show the operation of the conventional memory circuit. (G) to (k) show the operation of the memory circuit 11. In the case of the conventional memory circuit, during the write latency following the write command WRITE, read data corresponding to the preceding read command READ is output from the memory circuit 11 and transmitted on the signal line. In the case of the memory circuit 11, write data is transmitted during the write latency period, so that the memory circuit 11 is operated at a timing different from that of the conventional memory circuit. That is, the read data is output from the memory circuit 11 after the same read latency RL as the conventional one from the read command READ, but the write data DI01 to DI14 are applied to the memory circuit 11 during the read latency RL. In order to realize this, a write command WRITE is applied immediately after application of the read command READ, and application of write data is started simultaneously with the write command WRITE. After the read operation from the memory cell is completed, the write data stored in the input register may be written into the memory cell.

  FIG. 14 is a timing chart showing the operation when the write operation is continuously executed. (A) to (f) show the operation of the conventional memory circuit. (G) to (k) show the operation of the memory circuit 11. FIG. 14 shows a case where the write latency is different from FIG. As can be seen from FIG. 14, the end timing of the write operation for the second write command WRITE is the same for the conventional memory circuit and the memory circuit 11.

  FIG. 15 is a timing chart showing an operation when three write operations are executed in succession. (A) to (f) show the operation of the conventional memory circuit. (G) to (k) show the operation of the memory circuit 11. FIG. 15 shows the case of the same write latency as FIG. As can be seen from FIG. 15, the end timing of the write operation corresponding to the third write command is slightly later in the memory circuit 11 than in the conventional memory circuit.

  The above embodiment shows the case of the configuration using the data strobe signal. However, even in the case of the configuration not using the data strobe signal, the above transmission method is applied in which the data signal is single-phase when reading and differential when writing. Obviously we can do it. The timing chart of the above read operation and write operation assumes a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory). It can be applied to a memory circuit.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present invention includes the following contents.
(Appendix 1)
Two data input / output terminals,
A data input circuit for inputting data via the two data input / output terminals;
A data output circuit for outputting data via the two data input / output terminals, wherein one of the data input circuit and the data output circuit has the two data input / output terminals as independent terminals. And the other circuit of the data input circuit and the data output circuit transmits a pair of differential signals by using the two data input / output terminals as a pair of terminals. A semiconductor integrated circuit.
(Appendix 2)
The register including at least 2-bit data is stored, and the other circuit transmits the 2-bit data stored in the register in a time division manner as two transmissions by a pair of differential signals. 2. The semiconductor integrated circuit according to 1.
(Appendix 3)
The semiconductor integrated circuit according to claim 1, further comprising a terminal for inputting / outputting a data strobe signal having a predetermined timing relationship with data transmitted through the data input / output terminal as a differential signal.
(Appendix 4)
The semiconductor integrated circuit according to any one of appendices 1 to 3, wherein the semiconductor integrated circuit is a memory circuit, the one circuit is the data output circuit, and the other circuit is the data input circuit. Integrated circuit.
(Appendix 5)
5. The semiconductor according to claim 4, further comprising a signal termination circuit that connects the two data input / output terminals via a resistor when the termination is on and separates the two data input / output terminals from each other when the termination is off. Integrated circuit.
(Appendix 6)
6. The semiconductor integrated circuit according to appendix 4 or 5, wherein input of data to the data input circuit is started via the two data input / output terminals simultaneously with reception of a write command.
(Appendix 7)
The logic circuit is a circuit for reading / writing data from / to a memory device, the one circuit is the data input circuit, and the other circuit is the data output circuit. The semiconductor integrated circuit according to any one of claims.
(Appendix 8)
When the termination is on, each of the two data input / output terminals is connected to a power supply voltage via a resistor and to the ground voltage via a resistor. When the termination is off, the two data input / output terminals are connected to the power supply voltage and the ground. The semiconductor integrated circuit according to appendix 6, further comprising a signal termination circuit for separating from a voltage.
(Appendix 9)
9. The semiconductor integrated circuit according to appendix 7 or 8, wherein writing of write data to the memory device is started simultaneously with transmission of a write command.
(Appendix 10)
Logic circuit;
A plurality of data signal lines including two data signal lines;
A memory connected to the logic circuit via the plurality of data signal lines,
The two data signal lines are used as independent signal lines, two single-phase signals are transmitted as read data from the memory to the logic circuit, and the two data signal lines are used as a pair of signal lines. The differential signal is written data and transmitted from the logic circuit to the memory.
(Appendix 11)
The plurality of data signal lines transmit read data having a number of bits equal to the number of the plurality of data signal lines at a time as a single-phase signal, and write data having a number of bits equal to the number of the plurality of data signal lines. 11. The memory system according to appendix 10, wherein the memory system is divided into two times and transmitted in a time division manner.

DESCRIPTION OF SYMBOLS 10 Logic circuit 11 Memory circuit 12 Clock generation circuit 13 Clock output buffer 14-1 to 14-12 Signal input / output terminal 15 Internal clock generation circuit 16 Clock input buffer 17-1 to 17-12 Signal input / output terminal

Claims (5)

Two data input / output terminals,
A data input circuit for inputting data via the two data input / output terminals;
A data output circuit for outputting data via the two data input / output terminals, wherein one of the data input circuit and the data output circuit has the two data input / output terminals as independent terminals. And the other circuit of the data input circuit and the data output circuit transmits a pair of differential signals by using the two data input / output terminals as a pair of terminals. A semiconductor integrated circuit.   A register for storing at least 2-bit data is included, and the other circuit transmits the 2-bit data stored in the register in a time division manner as two transmissions by a pair of differential signals. Item 14. A semiconductor integrated circuit according to Item 1.   2. The semiconductor integrated circuit according to claim 1, further comprising a terminal for inputting / outputting a data strobe signal having a predetermined timing relationship with data transmitted through the data input / output terminal as a differential signal.   4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a memory circuit, the one circuit is the data output circuit, and the other circuit is the data input circuit. Semiconductor integrated circuit.   5. The signal termination circuit according to claim 4, further comprising a signal termination circuit that connects the two data input / output terminals via a resistor when the termination is on and separates the two data input / output terminals from each other when the termination is off. Semiconductor integrated circuit.

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