JP2011018835A - Method of manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device for preventing an insulating film at an upper end portion of a dummy gate electrode from disappearing and preventing an insulating film at an upper end portion of a cell gate electrode from being excessively removed when an interlayer insulating film is planarized by a CMP method. A manufacturing method is provided.
In a method for manufacturing a semiconductor device, the height of a dummy gate electrode 6 having an SW nitride film 15 formed on the upper surface thereof from the surface of a semiconductor substrate 3 is made higher than that of a cell gate electrode 5 and a peripheral gate electrode 7. In this state, the BPSG film 21 is planarized by the CMP method to expose the mask nitride films 13 of the cell gate electrode 5, the dummy gate electrode 6, and the peripheral gate electrode 7, respectively.
[Selection] Figure 9

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of planarizing an interlayer insulating film using a CMP method.

  For example, in a semiconductor device such as a DRAM (Dynamic Random Access Memory), a memory cell region and a peripheral circuit region are formed on a semiconductor substrate. In the memory cell region, a plurality of cell gate electrodes are arranged at fine intervals to form a dense gate pattern. In the peripheral circuit region, a plurality of peripheral gate electrodes are arranged at relatively large intervals, and a sparse gate pattern is configured.

  Patent Document 1 discloses a configuration in which a dummy gate electrode is provided in a portion where a gate pattern is sparse, that is, a position where a gate electrode is not formed. By providing the dummy gate electrode in this manner, the thickness of the insulating film formed on the gate electrode can be made uniform in the manufacturing process of the semiconductor device.

  Patent Document 2 discloses a configuration in which dummy gate electrodes are provided at sparse locations between peripheral gate electrodes in the peripheral circuit region. By providing the dummy gate electrode in this way, the density of the gate pattern in the peripheral circuit region can be brought close to the density of the gate pattern in the memory cell region. Accordingly, in the polishing process of the interlayer insulating film, it is possible to equalize the density at which irregularities occur in the memory cell region and the peripheral circuit region, and to flatten the polished interlayer insulating film.

JP 2004-14954 A JP 2003-243619 A

  In the manufacturing process of the DRAM, as shown in FIGS. 1 to 3, the cell gate electrode 5 in the memory cell region A1, the dummy gate electrode 6 and the peripheral gate electrode 7 in the peripheral circuit region A2 arranged on the surface of the semiconductor substrate 3. A step of forming sidewall spacers (sidewall insulating films) 17 and 20 is performed on each of these.

  First, as shown in FIG. 1, the peripheral gate electrode 7 in the peripheral circuit region A2 is covered with the first resist film 16, and the silicon nitride film 15 covering the cell gate electrode 5 in the memory cell region A1 is etched, whereby the cell gate electrode 5 Side wall spacers 17 made of the silicon nitride film 15 are formed on the side surfaces of the silicon nitride film. Subsequently, after removing the first resist film 16, each of the cell gate electrode 5, the dummy gate electrode 6, and the peripheral gate electrode 7 is covered with a silicon oxide film 18.

  Next, as shown in FIG. 2, the cell gate electrode 5 and the dummy gate electrode 6 are covered with the second resist film 19, and the silicon nitride film 15 and the silicon oxide film 18 covering the peripheral gate electrode 7 are etched, thereby forming the peripheral gate. Sidewall spacers 20 are formed on the side surfaces of the electrodes 7. Thereafter, as shown in FIG. 3, the second resist film is removed, and the cell gate electrode 5, the dummy gate electrode 6, and the peripheral gate electrode 7 are covered with an interlayer insulating film made of a BPSG (Boron Phosphor Silicate Glass) film 21.

  By the way, in the DRAM, with miniaturization, reduction of the capacity between adjacent cell contacts (Landing Contact) and reduction of the aspect ratio of the cell contacts are required. Therefore, in the DRAM manufacturing process, a CMP process using a silica-based slurry is performed when forming an interlayer insulating film of the cell gate electrode 5 or a cell contact (a cell contact connecting the N + diffusion layer to the cylinder type capacitor). It has been broken.

  In this CMP process, as shown in FIG. 3, the upper end portion of the cell gate electrode 5 in the memory cell region A1, the upper end portion of the dummy gate electrode 6, and the upper end portion of the peripheral gate electrode 7 in the peripheral circuit region A2 are formed. Polishing is performed to planarize the interlayer insulating film using the silicon nitride film 13 as a stopper.

  However, when polishing is performed in the above-described CMP process, an interlayer is formed in the CMP process in the boundary area between the memory cell area A1 where the gate patterns are densely packed and the peripheral circuit area A2 configured with a relatively sparse gate pattern. After planarizing the insulating film, as shown in FIG. 4, a so-called dishing D in which the depth gradually increases from the periphery toward the center occurs between the memory cell region A1 and the peripheral circuit region A2. There's a problem.

  Due to the occurrence of this dishing D, the silicon nitride film 13 formed on the upper end portion of the cell gate electrode 5 in the memory cell region A1 is excessively removed, or directly below the silicon nitride film 13 on the upper end portion of the dummy gate electrode 6. There was a problem that the arranged tungsten film 12 was exposed.

  As a result, in the CMP process, there is a problem that the tungsten film 12 of the dummy gate electrode 6 may be lost, or the semiconductor chip is contaminated by the scattering of the tungsten film 12 of the dummy gate electrode 6.

  The present invention is intended to solve the above-described problems.

According to one aspect of the method for manufacturing a semiconductor device of the present invention, a memory cell region having a cell gate electrode and a peripheral circuit region having a peripheral gate electrode are provided, and the memory cell region is between the cell gate electrode and the peripheral gate electrode. A semiconductor substrate having a first gate insulating film formed on each of the upper ends of the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode, the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode; Forming a second insulating film covering the gate electrode and the surface of the semiconductor substrate;
Removing the second insulating film covering the upper surface of the first insulating film of the cell gate electrode and forming a sidewall insulating film on the cell gate electrode with the remaining second insulating film;
Forming a third insulating film covering the cell gate electrode, the dummy gate electrode, the peripheral gate electrode, and the surface of the semiconductor substrate;
Removing the second insulating film and the third insulating film covering the upper surface of the first insulating film of the peripheral gate electrode, and forming a sidewall insulating film on the peripheral gate electrode with the remaining second insulating film and third insulating film;
Forming a cell gate electrode, a dummy gate electrode, a peripheral gate electrode, and a fourth insulating film covering the surface of the semiconductor substrate;
In a state where the height from the surface of the semiconductor substrate of the dummy gate electrode having the second insulating film formed on the upper surface is higher than that of the cell gate electrode and the peripheral gate electrode, the fourth insulating film is planarized by CMP. Exposing the first insulating films of the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode.

  According to the semiconductor device manufacturing method of the present invention described above, after the sidewall insulating films are formed on the cell gate electrode and the peripheral gate electrode, the second insulating film formed on the upper surface of the dummy gate electrode is left without being removed. be able to. For this reason, when the fourth insulating film is planarized by the CMP method, the height of the dummy gate electrode having the second insulating film formed on the upper surface from the surface of the semiconductor substrate is higher than that of the cell gate electrode and the peripheral gate electrode. In the raised state, the space between the memory cell region and the peripheral circuit region is polished. As a result, even when dishing by the CMP method occurs between the memory cell region and the peripheral circuit region, the second insulating film on the upper surface of the dummy gate electrode functions as a stopper, and the first of the dummy gate electrode It is prevented that the insulating film disappears and the first insulating films of the cell gate electrode and the peripheral gate electrode are not removed excessively. Therefore, a sufficient thickness of the first insulating film of the cell gate electrode is ensured.

  In the present invention, the memory cell area refers to an area including a nonvolatile memory. In the present invention, the peripheral circuit region indicates a region including the peripheral circuit of the nonvolatile memory.

  According to the present invention, when the interlayer insulating film is planarized by the CMP method, the insulating film at the upper end portion of the dummy gate electrode is prevented from disappearing and the thickness of the insulating film formed at the upper end portion of the cell gate electrode is reduced. It can prevent thinning. Therefore, the present invention can secure a sufficient thickness of the insulating film at the upper end of the cell gate electrode.

FIG. 6 is a cross-sectional view showing a state in which a peripheral gate electrode is covered with a first resist film in a manufacturing process of a semiconductor device related to the present invention. In the manufacturing process of the semiconductor device relevant to this invention, it is sectional drawing which shows the state in which the cell gate electrode and the dummy gate electrode were covered with the 2nd resist. FIG. 6 is a cross-sectional view showing a state in which sidewall spacers are formed on a cell gate electrode, a dummy gate electrode, and a peripheral gate electrode in a manufacturing process of a semiconductor device related to the present invention. FIG. 10 is a cross-sectional view showing a state in which dishing occurs across a dummy gate electrode and a peripheral gate electrode in a manufacturing process of a semiconductor device related to the present invention. FIG. 6 is a cross-sectional view showing a state where a peripheral gate electrode is covered with a first resist film in the manufacturing process of the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a state in which a sidewall spacer is formed on a cell gate electrode in the manufacturing process of the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a state where a cell gate electrode and a dummy gate electrode are covered with a second resist in the manufacturing process of the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing a state where sidewall spacers are formed on a peripheral gate electrode in the manufacturing process of the semiconductor device of the first embodiment. 5 is a cross-sectional view showing a state in which a cell gate electrode, a dummy gate electrode, and a peripheral gate electrode are covered with a BPSG film in the manufacturing process of the semiconductor device of the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a state in which a BPSG film is planarized in the manufacturing process of the semiconductor device of the first embodiment. In the manufacturing process of the semiconductor device of 2nd Embodiment, it is sectional drawing which shows the state by which the phosphorus dope silicon film was embedded inside the contact hole. In the manufacturing process of the semiconductor device of 2nd Embodiment, it is sectional drawing which shows the state by which the BPSG film | membrane was planarized.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

  As shown in FIG. 5, the semiconductor device manufacturing method of the present embodiment includes a memory cell region (A1) in which a plurality of cell gate electrodes (5) are arranged, and a peripheral circuit region having a plurality of peripheral gate electrodes (7). (A2), and the memory cell region (A1) is a dummy gate electrode disposed between the cell gate electrode (5) disposed at the end of the memory cell region (A1) and the peripheral gate electrode (7). (6), and a first insulating film (mask nitride film 13) is formed on each cell gate electrode (5), dummy gate electrode (6), and each upper end of each peripheral gate electrode (7). A step of preparing a substrate (3).

  In addition, the method for manufacturing the semiconductor device includes a second insulating film (SW nitride film) covering the surface of each cell gate electrode (5), dummy gate electrode (6), each peripheral gate electrode (7), and the semiconductor substrate (1). 15), a step of forming a first resist film (16) covering the second insulating film (SW nitride film 15) across each peripheral gate electrode (7) and dummy gate electrode (6), Etching is performed using the first resist film (16) as a mask to remove the second insulating film (SW nitride film 15) covering the upper surface of the first insulating film (mask nitride film 13) of each cell gate electrode (5). Then, a step of forming a sidewall insulating film (sidewall spacer 17) on each cell gate electrode (5) with the remaining second insulating film (SW nitride film 15), and a first resist film (16) from the semiconductor substrate (3). And a step of removing There.

  In addition, the method for manufacturing the semiconductor device includes a third insulating film (SW oxide film) covering the surface of each cell gate electrode (5), dummy gate electrode (6), each peripheral gate electrode (7), and the semiconductor substrate (3). 18), a step of forming a second resist film (19) covering the third insulating film (SW oxide film 18) across each cell gate electrode (5) and dummy gate electrode (6), Etching is performed using the second resist film (19) as a mask, and a second insulating film (SW nitride film 15) covering the upper surface of the first insulating film (mask nitride film 13) of each peripheral gate electrode (7) and the first The third insulating film (SW oxide film 18) is removed, and the peripheral insulating film (sidewall) is formed on each peripheral gate electrode (7) by the remaining second insulating film (SW nitride film 15) and third insulating film (SW oxide film 18). Forming a spacer 20), and half From the body substrate (3) has a step of removing the second resist layer (19), the.

  In addition, the semiconductor device manufacturing method includes the fourth insulating film (BPSG film 21) covering the surface of each cell gate electrode (5), dummy gate electrode (6), each peripheral gate electrode (7), and the semiconductor substrate (3). ), And the second insulating film (SW nitride film 15) formed on the upper surface of the dummy gate electrode (6) as a stopper, and the fourth insulating film (BPSG film 21) is planarized by CMP. And exposing each first insulating film (mask nitride film 13) of each cell gate electrode (5), dummy gate electrode (6), and each peripheral gate electrode (7).

(First embodiment)
5 to 10 are cross-sectional views for explaining the first embodiment. As shown in FIG. 5, on the surface of the semiconductor substrate 3, a memory cell region A <b> 1 and a peripheral circuit region A <b> 2 are partitioned and formed by an element isolation region 4.

  In the memory cell region A1, a plurality of cell gate electrodes 5 constituting a memory cell transistor are arranged to form a memory cell array. In the memory cell transistor, a memory cell array is configured by repetitively arranging cell gate electrodes 5 having relatively small gate lengths at a fine pitch. In the memory cell region A1, dummy gate electrodes 6 are formed at end portions of the plurality of cell gate electrodes 5 arranged in the memory cell array.

  In the peripheral circuit region A2 located on the opposite side of the memory cell region A1 where the plurality of cell gate electrodes 5 are arranged with the dummy gate electrode 6 interposed therebetween, a plurality of peripheral gate electrodes 7 constituting the peripheral transistor are provided. Is formed. For convenience, only one peripheral gate electrode 7 is shown in FIG. Therefore, the dummy gate electrode 6 is disposed between the cell gate electrode in the memory cell region and the peripheral gate electrode 7 in the peripheral circuit region A2.

  On the semiconductor substrate 3, a gate insulating film having a thickness of 5 nm, a polycrystalline silicon film 11 having a thickness of 70 nm, a barrier metal film having a thickness of 10 nm, a tungsten film 12 having a thickness of 60 nm, and A mask nitride film 13 as a first silicon nitride film (first insulating film) having a thickness of 70 nm is laminated and formed in this order. In FIG. 5, the gate insulating film and the barrier metal film are relatively thin, and are not shown for convenience.

  By patterning the polycrystalline silicon film 11, the barrier metal film, the tungsten film 12, and the mask nitride film 13, the gate electrodes 5, 6, and 7 having the mask nitride film 13 provided at the upper end are formed.

  Phosphorous implantation for forming an LDD (Lightly Doped Drain) diffusion layer is performed in the diffusion layer region of the memory cell transistor. At this time, the energy is 10 KeV, and phosphorus is implanted under the condition that the dose is 1.5 × 10 13 atoms / cm 2.

  Subsequently, phosphorus for forming the LDD diffusion layer is implanted into the diffusion layer region of the peripheral transistor. At this time, energy is 10 KeV, and phosphorus is implanted under the condition of a dose amount of 2 × 10 13 atoms / cm 2.

  On the entire surface of the semiconductor substrate 3 including the patterned gate electrodes 5, 6, and 7, a sidewall nitride film 15 (hereinafter referred to as SW nitride film 15) as a second silicon nitride film is formed in a thickness range of 10 nm to 50 nm. Is formed by a CVD (Chemical Vapor Deposition) method. In the present embodiment, the thickness of the SW nitride film 15 is set to 30 nm.

  Then, a resist is applied to the entire surface of the semiconductor substrate 3, and the surface of the cell gate electrode 5 in the memory cell region A1 is exposed and the surface of the dummy gate electrode 6 and peripheral circuits are exposed by photolithography as shown in FIG. A first resist film 16 is formed to cover the surface of the peripheral gate electrode 7 in the region A2.

  Next, as shown in FIG. 6, the SW nitride film 15 is etched back by anisotropic etching using plasma containing fluorine gas using the first resist film 16 as a mask. As a result, a sidewall spacer 17 made of the remaining SW nitride film 15 is formed on the side wall of the cell gate electrode 5, and an opening is opened on the surface of the semiconductor substrate 3. As a result, the SW nitride film 15 formed on the surface of the dummy gate electrode 6 and the surface of the peripheral gate electrode 7 remains without being removed. Subsequently, the first resist film 16 used as a mask is removed from the semiconductor substrate 3 by oxygen ashing.

  As shown in FIG. 7, a sidewall oxide film 18 (hereinafter referred to as SW oxide film 18) as a third silicon oxide film (third insulating film) is formed on the entire surface of the semiconductor substrate 3 by the CVD method. Is formed to be about 10 nm to 40 nm.

  Then, a resist is applied to the entire surface of the semiconductor substrate 3, and the surface of the peripheral gate electrode 7 in the peripheral circuit region A2 is exposed and the surface of the memory cell region A1, that is, the memory, by photolithography, as shown in FIG. A second resist film 19 is formed to cover the surface of the cell gate electrode 5 of the transistor and the surface of the dummy gate electrode 6.

  As shown in FIG. 8, using the second resist film 19 as a mask, the SW oxide film 18 of the peripheral gate electrode 7 is etched back by anisotropic etching using plasma containing fluorine gas. Subsequently, the SW nitride film 15 is planarized by etch back. As a result, sidewall spacers 20 composed of the remaining SW nitride film 15 and SW oxide film 18 are formed on the sidewalls of the peripheral gate electrode 7 in the peripheral circuit region A2.

  The peripheral transistor 7 in the peripheral circuit region A2 is subjected to ion implantation for forming a source / drain region using the sidewall spacer 20 formed of the SW nitride film 15 and the SW oxide film 18 as a mask. At this time, arsenic is used as an ion species, and implantation is performed under the conditions of an energy of 20 KeV and a dose of 2 × 10 15 atoms / cm 2.

  Through this series of steps, the SW nitride film 15 at the upper end of the cell gate electrode 5 and the upper end of the peripheral gate electrode 7 is removed, and the SW nitride film remains only at the upper end of the dummy gate electrode 6. it can. Therefore, with respect to the height from the surface of the semiconductor substrate 3, the cell gate electrode 5 and the peripheral gate electrode 7 are substantially the same height, and the height of the dummy gate electrode 6 is higher than the height of the cell gate electrode 5 and the peripheral gate electrode 7. Also, it is formed to be higher by the film thickness of the SW nitride film 15.

  As shown in FIG. 9, the second resist film 19 used as a mask is removed from the semiconductor substrate 3. In FIG. 9 and subsequent figures, the SW oxide film 18 formed so as to cover the entire surface of the memory cell region A1 remains, but the SW oxide film 18 and the BPSG film 21 are insulating films of the same quality. The illustration of the oxide film 18 is omitted. Subsequently, a BPSG film 21 constituting an interlayer insulating film as a fourth insulating film is formed on the entire surface of the semiconductor substrate 3.

  As shown in FIG. 10, the BPSG film 21 is planarized by polishing in the CMP process, and the mask nitride films at the upper ends of the cell gate electrode 5, the dummy gate electrode 6, and the peripheral gate electrode 7 are planarized. In the polishing, the BPSG film is polished using a condition that allows a selectivity to the mask nitride film 13. Then, the upper surfaces of the mask nitride films 13 formed at the upper ends of the cell gate electrode 5, the dummy gate electrode 6, and the peripheral gate electrode 7 are exposed, and polishing is stopped at the position where the mask nitride film 13 is exposed. By flattening the BPSG film 21 in this manner, variation in height generated in the interlayer insulating film in the semiconductor chip as the semiconductor device is suppressed, and the heights of the gate electrodes 5, 6 and 7 are made uniform. be able to.

  As a result, etching detachability at the time of cell contact formation performed in the subsequent process (contact hole detachability by anisotropic etching is improved, and contact hole penetration failure can be prevented from occurring) There is an advantage that variation in excavation (etching progress state) of the substrate 3 can be reduced.

  For polishing in the CMP process, for example, a silica-based slurry is used. In this polishing step, the upper surface of the SW nitride film 15 formed at the upper end portion of the dummy gate electrode 6 having the highest height from the surface of the semiconductor substrate 3 is exposed first. Thereafter, as the SW nitride film 15 formed on the upper end portion of the dummy gate electrode 6 is removed, the upper surface of the mask nitride film 13 formed on the upper end portion of the peripheral gate electrode 7 is exposed.

  A dummy gate electrode 6 is disposed at the end in the direction in which the cell gate electrodes 5 of the memory cell array in which the polishing is relatively easy to proceed, and the SW nitride film 15 formed on the upper end of the dummy gate electrode 6 is arranged. The dummy gate electrode 6 is formed higher by the thickness. Thus, since the SW nitride film functions as a stopper during polishing in the CMP process, the mask nitride film 13 of the memory cell transistor in the memory cell transistor array is prevented from being excessively shaved by polishing.

  That is, in the semiconductor device manufacturing method of the present embodiment, the CMP process is performed in a state where the height of the dummy gate electrode 6 having the SW nitride film 15 formed on the upper surface is higher than that of the cell gate electrode 5 and the peripheral gate electrode 7. To flatten the BPSG film 21 and expose the mask nitride films 13 of the cell gate electrode 5, the dummy gate electrode 6 and the peripheral gate electrode 7, respectively.

  Therefore, according to the present embodiment, the mask nitride film 13 at the upper end portion of the dummy gate electrode is prevented from disappearing in the CMP process, and the thickness of the mask nitride film 13 formed at the upper end portion of the cell gate electrode is reduced. Can be prevented. Therefore, a sufficient thickness of the mask nitride film 13 at the upper end portion of the cell gate electrode can be ensured.

  In addition, the tungsten film 12 formed immediately below the mask nitride film 13 of the dummy gate electrode 6 can be prevented from being exposed, and the disappearance of the tungsten film 12 of the dummy gate electrode 6 and the tungsten film in the CMP process can be prevented. It is possible to prevent contamination due to the scattering of 12 or the like.

(Second Embodiment)
Next, a second embodiment will be described with reference to the drawings. The second embodiment is different from the manufacturing method of the first embodiment described above only in that a step of forming a cell contact is added, so only the steps after the step shown in FIG. 9 will be described. To do. Note that in the second embodiment, the same members as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. 11 and 12 are cross-sectional views for explaining the second embodiment.

  In the second embodiment, after the step shown in FIG. 9, a contact hole 23 reaching the surface of the semiconductor substrate 3 is formed between adjacent cell gate electrodes 5 in the memory cell transistor, as shown in FIG. . Inside the contact hole 23, the BPSG film is etched using a condition that allows a selection ratio with respect to the mask nitride film 13 to open a diffusion layer between the cell gate electrodes 5.

  As shown in FIG. 11, the phosphorous doped silicon film 24 is embedded in the contact hole, and the phosphorous doped silicon film 24 is formed over the BPSG film 21.

  Next, the surface of the BPSG film 21 is exposed by polishing the phosphorus-doped silicon film 24 and removing the phosphorus-doped silicon film 24 covering the BPSG film 21 in a CMP process. Subsequently, the BPSG film 21 and the phosphorus-doped silicon film 24 inside the contact hole 24 are polished. By polishing the BPSG film 21 in the CMP process, the upper interlayer film of each gate electrode 5, 6, 7 is planarized. In the polishing in the CMP process, the polishing is performed using conditions that allow the mask nitride film 13 to have a selectivity.

  Then, similarly to the first embodiment described above, the upper surfaces of the mask nitride films 13 formed on the upper ends of the cell gate electrode 5, the dummy gate electrode 6 and the peripheral gate electrode 7 are exposed, as shown in FIG. Thus, the polishing of the BPSG film 21 is stopped at the position where each mask nitride film 13 is exposed. By flattening the BPSG film 21 in this way, variations in the height of the interlayer insulating film in the semiconductor chip are suppressed, and the heights of the gate electrodes 5, 6, and 7 are formed uniformly. Can do.

  Also in this CMP process, the gate gate electrode of the dummy transistor having the highest height from the surface of the semiconductor substrate 1 among the cell gate electrode 5, the dummy gate electrode 6, and the peripheral gate electrode 7, as in the first embodiment. 6 is exposed most first. Thereafter, the upper surface of the mask nitride film 13 on the peripheral gate electrode 7 of the peripheral transistor is exposed.

  A dummy gate electrode 6 of a dummy transistor is disposed at an end of a portion where a plurality of cell gate electrodes 5 constituting a memory cell array in which polishing is relatively easy to proceed. Then, by leaving the SW nitride film 15 formed on the upper end portion of the dummy gate electrode 6, the height of the dummy gate electrode 6 is higher than the height of the cell gate electrode 5 and the peripheral gate electrode 7. It is formed higher by the thickness of. As a result, the SW nitride film 15 at the upper end of the dummy gate electrode 6 functions as a polishing stopper in the CMP process. Therefore, the mask nitride film 13 formed on each cell gate electrode 5 arranged in the memory cell transistor array is prevented from being excessively shaved by polishing.

  In the polishing process in the CMP process, for example, silica-based slurry is used.

  According to the present embodiment, it is possible to form a contact plug between the fine cell gate electrodes 5 and planarize the interlayer insulating film made of the BPSG film 21. That is, in this embodiment, the CMP process for polishing the phosphorus-doped silicon film 24 to form a contact plug for the memory cell contact is performed between the layers located above the cell gate electrode 5, the dummy gate electrode 6, and the peripheral gate electrode 7. A CMP process for planarizing the BPSG film 21 which is an insulating film can also be performed, and the manufacturing cost can be reduced.

A1 Memory cell region A2 Peripheral circuit region 3 Semiconductor substrate 5 Cell gate electrode 6 Peripheral gate electrode 7 Dummy gate electrode 13 Mask nitride film (first insulating film, first silicon nitride film)
15 SW nitride film (second insulating film, second silicon nitride film)
16 First resist film 17, 20 Side wall spacer (side wall insulating film)
18 SW oxide film (third insulating film)
19 Second resist film 21 BPSG film (fourth insulating film)

Claims (7)

A memory cell region having a cell gate electrode and a peripheral circuit region having a peripheral gate electrode, wherein the memory cell region has a dummy gate electrode disposed between the cell gate electrode and the peripheral gate electrode, The cell gate electrode, the dummy gate electrode, the peripheral gate electrode, and the semiconductor substrate, wherein the first insulating film is formed on each upper end of the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode. Forming a second insulating film covering the surface of
Removing the second insulating film covering the upper surface of the first insulating film of the cell gate electrode, and forming a sidewall insulating film on the cell gate electrode with the remaining second insulating film;
Forming a third insulating film covering the cell gate electrode, the dummy gate electrode, the peripheral gate electrode and the surface of the semiconductor substrate;
The second insulating film and the third insulating film that cover the upper surface of the first insulating film of the peripheral gate electrode are removed, and a sidewall insulating film is formed on the peripheral gate electrode by the remaining second insulating film and the third insulating film. Forming a step;
Forming a fourth insulating film covering the cell gate electrode, the dummy gate electrode, the peripheral gate electrode and the surface of the semiconductor substrate;
The dummy gate electrode, on which the second insulating film is formed on the upper surface, is higher than the cell gate electrode and the peripheral gate electrode by a height from the surface of the semiconductor substrate. Planarizing an insulating film and exposing the first insulating films of the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode, respectively;
A method for manufacturing a semiconductor device comprising: A memory cell region in which a plurality of cell gate electrodes are arranged; and a peripheral circuit region having a plurality of peripheral gate electrodes, wherein the memory cell region is arranged at an end of the memory cell region and the peripheral A semiconductor substrate having a dummy gate electrode disposed between the gate electrode and a first insulating film formed on each cell gate electrode, the dummy gate electrode, and each peripheral gate electrode is prepared. And a process of
Forming a second insulating film covering each cell gate electrode, the dummy gate electrode, each peripheral gate electrode, and the surface of the semiconductor substrate;
Forming a first resist film covering the second insulating film over the peripheral gate electrodes and the dummy gate electrodes;
Etching is performed using the first resist film as a mask, the second insulating film covering the upper surface of the first insulating film of each cell gate electrode is removed, and a sidewall is formed on each cell gate electrode by the remaining second insulating film. Forming an insulating film;
Removing the first resist film from the semiconductor substrate;
Forming a third insulating film covering the cell gate electrodes, the dummy gate electrodes, the peripheral gate electrodes, and the surface of the semiconductor substrate;
Forming a second resist film covering the third insulating film across each cell gate electrode and the dummy gate electrode;
Etching is performed using the second resist film as a mask, the second insulating film and the third insulating film covering the upper surface of the first insulating film of each peripheral gate electrode are removed, and the remaining second insulating film And forming a sidewall insulating film on each peripheral gate electrode by the third insulating film;
Removing the second resist film from the semiconductor substrate;
Forming a fourth insulating film covering the cell gate electrodes, the dummy gate electrodes, the peripheral gate electrodes and the surface of the semiconductor substrate;
The fourth insulating film is planarized by CMP using the second insulating film formed on the upper surface of the dummy gate electrode as a stopper, and the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode Exposing each of the first insulating films, and
A method for manufacturing a semiconductor device comprising: Between the step of forming the fourth insulating film and the step of exposing each of the first insulating films,
Forming a contact hole that penetrates the fourth insulating film and reaches the surface of the semiconductor substrate between the adjacent cell gate electrodes;
Forming a fifth insulating film so as to fill the inside of the contact hole and cover the fourth insulating film;
The method for manufacturing a semiconductor device according to claim 2, comprising: A memory cell region in which a plurality of cell gate electrodes are arranged; and a peripheral circuit region having a plurality of peripheral gate electrodes, wherein the memory cell region is arranged at an end of the memory cell region and the peripheral A semiconductor substrate having a dummy gate electrode disposed between the gate electrode and each cell gate electrode, the dummy gate electrode, and each peripheral gate electrode having a first silicon nitride film formed on each upper end thereof; A process to prepare;
Forming a second silicon nitride film covering the cell gate electrodes, the dummy gate electrodes, the peripheral gate electrodes, and the surface of the semiconductor substrate;
Forming a first resist film covering the second silicon nitride film over each peripheral gate electrode and the dummy gate electrode;
Anisotropic etching is performed using the first resist film as a mask, the second silicon nitride film covering the upper surface of the first silicon nitride film of each cell gate electrode is removed, and the remaining second silicon nitride film Forming a sidewall insulating film on each cell gate electrode;
Removing the first resist film from the semiconductor substrate;
Forming a silicon oxide film covering the cell gate electrodes, the dummy gate electrodes, the peripheral gate electrodes, and the surface of the semiconductor substrate;
Forming a second resist film covering the silicon oxide film across each cell gate electrode and the dummy gate electrode;
Anisotropic etching is performed using the second resist film as a mask to remove the second silicon nitride film and the silicon oxide film covering the upper surface of the first silicon nitride film of each peripheral gate electrode, and the remaining Forming a sidewall insulating film on each of the peripheral gate electrodes with a second silicon nitride film and the silicon oxide film;
Removing the second resist film from the semiconductor substrate;
Forming a BPSG film covering each cell gate electrode, the dummy gate electrode, each peripheral gate electrode, and the surface of the semiconductor substrate;
The BPSG film is planarized by CMP using the second silicon nitride film formed on the upper surface of the dummy gate electrode as a stopper, and the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode Exposing each of the first silicon nitride films;
A method for manufacturing a semiconductor device comprising: Between the step of forming the BPSG film and the step of exposing each of the first silicon nitride films,
Forming a contact hole that penetrates the BPSG film and reaches the surface of the semiconductor substrate between the adjacent cell gate electrodes;
Forming a polycrystalline silicon film so as to fill the contact hole and cover the BPSG film;
The manufacturing method of the semiconductor device of Claim 4 which has these.   The method of manufacturing a semiconductor device according to claim 5, wherein the polycrystalline silicon film is a phosphorus-doped silicon film. A memory cell region in which a plurality of cell gate electrodes are arranged; and a peripheral circuit region having a peripheral gate electrode, wherein the memory cell region is disposed at an end of the memory cell region and the peripheral gate electrode A semiconductor substrate having a dummy gate electrode disposed between,
A first insulating film formed on each upper end of the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode;
Of the cell gate electrode, the dummy gate electrode, and the peripheral gate electrode, provided on the upper surface of only the dummy gate electrode, and a second insulating film covering the first insulating film,
The dummy gate electrode is a semiconductor device, wherein a height from the surface of the semiconductor substrate is higher than that of the cell gate electrode and the peripheral gate electrode.

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