JP2011018782A - Component built-in wiring board and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a component built-in wiring board facilitating inspection during production.SOLUTION: The component built-in wiring board includes a first insulating layer 11, a second insulating layer 13 having a lamination of at least two insulating layers and laminated on the first insulating layer, an electric/electronic component 41 having terminals embedded in the second insulating layer, a first wiring pattern 22 including a connection land for the electric/electronic component and sandwiched between the first and second insulating layers, a connecting member 42 electrically connecting the terminals to the connection land, a second wiring pattern 21 provided on the opposite surface of the first insulating layer to the surface thereof where the first wiring pattern is located, a first interlayer-connecting part 31 penetrating through the first insulating layer to electrically connect the first and second wiring patterns, a third wiring pattern 23 sandwiched between the at least two insulating layers, and a second interlayer connecting part 32 penetrating through a lamination-directional part of the second insulating layer and sandwiched between surfaces of the first and third wiring patterns. Each first wiring pattern 22 continual to the connection land is not in contact with the first interlayer connecting part 31.

Description

  The present invention relates to a component built-in wiring board in which components are embedded and mounted in an insulating plate and a method for manufacturing the same, and more particularly to a component built-in wiring board having a configuration in view of ease of inspection during manufacturing and a method for manufacturing the same.

  A conventional example of a component built-in wiring board is disclosed in Japanese Patent Application Laid-Open No. 2003-197849. This wiring board has a surface-mounted passive element component and a flip-connected semiconductor chip as built-in components.

  In general, in a component built-in wiring board, there is a problem in how to inspect the mounted connection state of the built-in component, the characteristics and function of the component, and guarantee the product. That is, during the manufacturing process, when the electronic component is mounted on the inner wiring pattern, the wiring for the electronic component is not completed and the wiring state is halfway. difficult. After this, the circuit is completed only after a multi-layer lamination process, an outer wiring layer patterning process, an individualization process, and the like, and electrical inspection becomes easy. However, in the inspection at this stage, even if the built-in component itself or the mounting connection state is defective, it cannot be repaired and a manufacturing loss occurs.

JP 2003-197849 A

  The present invention has been made in consideration of the above-described circumstances, and in a component-embedded wiring board in which components are embedded and mounted in an insulating plate and a manufacturing method thereof, components that can be easily inspected during manufacturing An object is to provide a built-in wiring board and a method for manufacturing the same.

  In order to solve the above-described problems, a component-embedded wiring board according to one embodiment of the present invention includes a first insulating layer and at least two insulating layers positioned in a stacked manner with respect to the first insulating layer. And sandwiched between the first insulating layer and the second insulating layer embedded in the second insulating layer, the electric / electronic component having a terminal embedded in the second insulating layer, and the second insulating layer A first wiring pattern including a connection land for the electrical / electronic component, and a connection member for electrically connecting the terminal of the electrical / electronic component and the connection land of the first wiring pattern; A second wiring pattern provided on a surface of the first insulating layer opposite to the surface on which the first wiring pattern is provided, and penetrating through the first insulating layer. A first interlayer electrically connecting the first wiring pattern and the second wiring pattern; A continuum, a third wiring pattern provided between the at least two insulating layers of the second insulating layer, and a part of the second insulating layer in the stacking direction. Each of the first wiring patterns connected to the connection land includes a second interlayer connection body sandwiched between the surface of the first wiring pattern and the surface of the third wiring pattern. It is not in contact with the first interlayer connection body.

  The component built-in wiring board having this configuration includes, for example, a first insulating layer having a first wiring pattern including a connection land, on which an electrical / electronic component is mounted, and an electrical / electronic component as partial materials in the course of manufacture. A second insulating layer to be embedded is prepared. Here, on the first insulating layer side, each of the first wiring patterns connected to the connection land of the electric / electronic component is not in contact with the first interlayer connection body penetrating the first insulating layer. .

  That is, in the state on the first insulating layer side, each of the first wiring patterns connected to the connection land is an electrically independent pattern. Therefore, by using this electrically independent pattern as an electrical inspection pad, it is possible to easily determine the quality of the component itself and the mounted connection state. Thereby, only what passed the inspection can be input to the subsequent processes.

  Moreover, the manufacturing method of the component built-in wiring board which is another aspect of this invention is the 1st insulating board which has a 1st surface and a 2nd surface, and the 1st laminated | stacked on the said 1st surface. The metal foil, the second metal foil laminated on the second surface, and the first metal foil and the second metal foil electrically passing through the first insulating plate A step of forming a laminated body having an interlayer connection to be conducted; patterning the second metal foil of the laminated body; and connecting a first wiring pattern including a connection land for a component to the connection land. A step of forming each of the first wiring patterns so as not to form a contact portion to the interlayer connection body, and using the connection land, an electrical / electrical current is formed on the second surface of the first stacked body. Electrically connecting the electronic component and electrically detecting the first wiring pattern connected to the connection land. Inspecting the electrical / electronic components using the pad for the purpose, selecting the non-defective product, and patterning the third metal foil laminated on the second insulating plate different from the first insulating plate, A step of forming a second wiring pattern, and a third insulating plate different from the first and second insulating plates is laminated on the surface of the second insulating plate on the side where the second wiring pattern is present And the fourth insulating layer is stacked on the non-defective first insulating plate so that the electric / electronic component is embedded in a fourth insulating plate different from the first to third insulating plates. And a step of integrating the third and second insulating plates in the order of the stacking positions.

  That is, in this manufacturing method, at the stage where the electrical / electronic component is electrically connected to the connection land by the first wiring pattern, all the first wiring patterns connected to the connection land pass through the first insulating plate. It is not in contact with the body and is electrically independent. Therefore, it is possible to inspect electric / electronic parts using the first wiring pattern connected to the connection land as an electric inspection pad, and to select non-defective products. As a result, only non-defective products in the course of manufacturing can be input to the subsequent processes.

  ADVANTAGE OF THE INVENTION According to this invention, in the component built-in wiring board by which components were embed | buried and mounted in the insulating board, and its manufacturing method, it becomes possible to inspect in the middle of manufacture easily.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 3 is a continuation diagram of FIG. 2, and is a process diagram (process diagram of electrical inspection) showing a part of a manufacturing process of the component built-in wiring board shown in FIG. 1 in a schematic cross section. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention.

  As an embodiment of the present invention, each of the first wiring patterns connected to the connection land may be in contact with the second interlayer connection body. In the component built-in wiring board that is a finished product, each of the first wiring patterns connected to the connection land passes through the second interlayer connection body to secure a circuit path as the wiring board. In addition to this, in order to secure the circuit path of the first wiring pattern connected to the connection land, there may be an aspect connected to the connection land (depending on the first wiring pattern) for other built-in components.

  As an embodiment, the second interlayer connector can be a conductive composition as a material thereof. Such an interlayer connection body of a conductive composition can be provided in a small region, and is suitable for increasing the density of a pattern as a wiring board.

  Here, the second interlayer connection body may have a shape having an axis coinciding with the stacking direction and a diameter changing in the direction of the axis. This interlayer connection body is a conductor derived from a conductive bump made of a conductive composition, and screen printing can be used for the formation thereof, which contributes to improvement in productivity.

  Further, as an embodiment, the electric / electronic component can be a surface-mounted passive element component. In the case where the electrical / electronic component is a surface-mounted passive element component, there is a great effect that it is possible to easily detect a defective state of a connection member (for example, solder) that cannot be visually recognized during manufacturing.

  As an embodiment, the electrical / electronic component is a semiconductor element having a semiconductor chip provided with a terminal pad, and the terminal of the electrical / electronic component is electrically connected to the terminal pad of the semiconductor chip. The surface mounting terminals can be arranged in a grid pattern. In such a case, it is possible to easily detect a connection failure state of a connection member (for example, solder) that cannot be seen in appearance, and a function including a wiring pattern and a semiconductor element mounted on the connection land, Each of the performances can be electrically inspected in the course of manufacturing a wiring board.

  Further, as an embodiment, the electrical / electronic component is a semiconductor chip provided with a terminal pad, the terminal of the electrical / electronic component is the terminal pad of the semiconductor chip, and the connection member is the semiconductor It can be defined as a conductive bump that is sandwiched between the terminal pad of the chip and the connection land of the first wiring pattern and electrically connects the terminal pad and the connection land. . In such a case, it is easy to electrically detect a connection failure state of the conductive bump that cannot be seen in appearance, and the wiring pattern and the semiconductor chip mounted on the connection land via the conductive bump are included. Each of the functions and performance can be electrically inspected during the manufacturing process of the wiring board.

  As an embodiment, the first wiring pattern may have a roughened surface on the second insulating layer side. According to the experiment, the electrical connection between the wiring pattern with the roughened surface and other conductive members is significantly lower resistance and the connection reliability is improved than the wiring pattern without the roughening. Is realized. Adhesion between the wiring pattern with the roughened surface and the insulating layer is also convenient.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layer 21 (second wiring pattern), 22 (first wiring pattern), 23 (third wiring pattern), 24, 25, 26 (= 6 layers in total), interlayer connection Body 31 (first interlayer connection body), 32 (second interlayer connection body), 34, 35, through-hole conductor 33, semiconductor chip 41 (electrical / electronic component), conductive bump 42 (connection) Member), underfill resin 51, and solder resists 61 and 62.

  The semiconductor chip 41 is electrically and mechanically connected to the inner wiring layer 22 via conductive bumps 42 by flip connection. For this connection, conductive bumps 42 are formed in advance on terminal pads (not shown) of the semiconductor chip 41, and connection lands are patterned on the wiring layer 22 so as to be aligned with the conductive bumps 42. Yes. The conductive bump 42 is made of, for example, gold (Au) as a material, and is previously formed in a stud shape on the terminal pad. An underfill resin 51 is filled between the semiconductor element 41 and the wiring layer 22 and the insulating layer 11 for mechanical and chemical protection of the flip connection portion.

  The surface of the wiring layer 22 that is in contact with the insulating layer 12 is a roughened surface 22a that has been treated so that the surface roughness is appropriately increased. This is a configuration for improving the low-resistance connection between the conductive bump 42 and the wiring layer 22 and its reliability, and also a configuration for improving the adhesion between the wiring layer 22 and the insulating layer 12. The roughened surface 22a further contributes to improving the reliability of the electrical connection between the wiring layer 22 and the interlayer connector 32.

  To describe still another structure, the wiring layers 21 and 26 are wiring layers on both main surfaces as a wiring board, and various components (not shown) can be mounted thereon. Solder resist 61 is provided on both main surfaces except for the land portions of the wiring layers 21 and 26 on which solder (not shown) is to be mounted in mounting, so that the solder melted at the time of solder connection is held on the land portions and thereafter functions as a protective layer. , 62 (thickness is about 20 μm, for example). An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is insulated between the wiring layer 21 and the wiring layer 22, and the wiring layer 22 and the wiring layer 23 are insulated in this order. The insulating layer 13 is provided between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is provided between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is provided between the wiring layer 25 and the wiring layer 26. However, the wiring layers 21 to 26 are separated from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, for example, having a thickness of 100 μm, and the insulating layer 13 only having a thickness of, for example, 300 μm. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in semiconductor chip 41, and provides a space for housing the semiconductor chip 41. The insulating layers 12 and 14 are deformed so as to fill the opening of the insulating layer 13 for the built-in semiconductor chip 41 and the space inside the through-hole conductor 33 of the insulating layer 13 and become voids inside. There is no space.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

  The interlayer connection body 31 penetrating the insulating layer 11 does not conduct or contact the wiring pattern 22 connected to the connection land for the electric / electronic component (in this embodiment, the semiconductor chip 41) that requires electrical inspection during the manufacturing process. It is provided in such a position. This is configured so that the wiring pattern 22 connected to the connection land for the semiconductor chip 41 and the interlayer connection body 31 are not brought into contact with each other, and all of these wiring patterns are electrically independent during the manufacturing process. This is because the quality of the component itself and the mounted connection state is determined by using the pad. The aspect of the electrical inspection will be described later (FIG. 3).

  In order to secure the circuit path of the wiring pattern 22 connected to the connection land for the semiconductor chip 41, an interlayer connection 32 penetrating the insulating layer 12 can be used as shown in the figure. Alternatively, there may be an aspect that is connected to a connection land (by the wiring pattern 22) for other built-in components.

  The component built-in wiring board having this configuration includes, as a partial material in the course of manufacturing, an insulating layer 11 having a wiring pattern 22 including a connection land on which a semiconductor chip 41 is mounted, and insulating layers 12 to 15 in which the semiconductor chip 41 is to be embedded. And can be prepared. During the manufacturing process, as described above, on the insulating layer 11 side, each of the wiring patterns 22 connected to the connection land of the semiconductor chip 41 is not in contact with the interlayer connector 31 penetrating the insulating layer 11.

  In other words, in the state on the insulating layer 11 side at this time, each of the wiring patterns 22 connected to the connection land is an electrically independent pattern. Therefore, by using this electrically independent pattern as an electrical inspection pad, it is possible to easily determine the quality of the component itself and the mounted connection state. Thereby, only what passed the inspection can be input to the subsequent processes.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 2 to 5 are process diagrams each schematically showing a part of a manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 2 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 2 (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm).

  By forming the conductive bumps of the conductive composition by screen printing, the conductive bumps that fit in a very small region can be efficiently formed with high productivity. Conductive bumps that fit in such a small area are suitable for increasing the density of patterns as wiring boards. The conductive composition here is obtained by dispersing fine metal particles such as silver, gold, and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 2B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31, so that the head is exposed. To do. At the time of exposure or afterwards, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 is a shape having an axis coinciding with the stacking direction and the diameter changing in the axial direction). Subsequently, as shown in FIG. 2 (c), a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 2D, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into a wiring layer 22 including connection lands. In this processing, each of the wiring patterns 22 connected to the connection land is performed so that there is no conduction or contact with the interlayer connection body 31. In other words, the formation position of the interlayer connector 31 is set in advance in the process shown in FIG.

  Further, as shown in FIG. 2E, the surface of the patterned wiring layer 22 is roughened to obtain a roughened surface 22a. Specifically, for example, a blackening reduction process or a microetching process can be employed. Examples of the micro-etching process include CZ processing (MEC product name) and bond film processing (Atotech product name).

  Since the process of roughening the surface of the copper foil is generally performed in order to improve the adhesion with the insulating resin laminated on the copper foil, the above roughening process is performed simultaneously with this process. It can be carried out. According to this, it is not necessary to perform the roughening process as a new process, which is efficient. However, the degree of roughening is preferably directed to an appropriate level in consideration of the low resistance in flip connection and its reliability.

  Next, an underfill resin before curing is applied to the position on the insulating layer 11 where the semiconductor chip 41 is to be mounted using, for example, a dispenser. Subsequently, the semiconductor chip 41 with the conductive bumps 42 is positioned and pressed against the connection land of the wiring layer 22 using, for example, a flip chip bonder. After the pressure welding, a heating process is performed to improve the connection strength and to cure the underfill resin 51. As described above, the wiring board material 1 in a state where the semiconductor chip 41 is mounted on the connection land of the wiring layer 22 is obtained as shown in FIG.

  Next, a description will be given with reference to FIG. FIG. 3 is a continuation diagram of FIG. 2 and is a process diagram (process diagram of electrical inspection) showing a part of the manufacturing process of the component built-in wiring board shown in FIG.

  In the wiring board material 1, each of the wiring patterns 22 on which the semiconductor chip 41 is mounted via the connection lands is an electrically independent pattern. This is as described above. Therefore, as shown in FIG. 3, the wiring board material 1 in this state is inspected. Specifically, as shown in the drawing, the wiring pattern 22 connected to the connection land is used as an electrical inspection pad, the inspection needle 101 is abutted against the inspection pad, and further connected to the inspection needle 101 to generate an inspection signal. / An inspection apparatus 100 that performs detection is prepared and inspection is performed.

  More preferably, the position on the wiring pattern 22 against which the inspection needle 101 is abutted can be a portion (= via land) where the interlayer connector 32 is to abut in the subsequent manufacturing process. Such a via land has a shape that expands in all directions and is easy to abut the inspection needle 101. In addition, the use of via land is convenient because the pattern 22 need not be modified because the inspection needle 101 is easily brought into contact with the via land.

  In this inspection, it is easy to electrically detect the connection failure state of the conductive bump 42 that cannot be seen in the appearance because of the flip connection, and the conductive bump is connected to the connection land by the wiring pattern 22 and the wiring pattern 22. It is possible to electrically inspect the function and performance including the mounted semiconductor chip 41 via the inspection device 100, respectively. Therefore, only non-defective products in the manufacturing process at this stage can be input to the subsequent processes. Moreover, repair may be performed depending on circumstances, and it can be used for the subsequent processes after repairing to a non-defective product.

  If a part of the wiring pattern 22 on which the semiconductor chip 41 is mounted via the connection land is electrically connected to or in contact with the interlayer connection body 31, the part of the wiring patterns 22 are in this stage. Since conduction is made through the metal foil 21A, even if the inspection apparatus 100 is used, a completely free electrical inspection is not possible. In terms of functional inspection, the quality of the product can generally be determined by conducting an electrical inspection on the final product, but in that case, the defective product is used until the end of the process, and repair is performed even if it is determined to be no. It is not considered possible, and the production loss due to disposal becomes very large. In the wiring board raw material 1 demonstrated in FIG. 2, such a problem is eliminated.

  Next, a description will be given with reference to FIG. FIG. 4 shows a manufacturing process of a part centering on the insulating layer 13 and the same 12 in each configuration shown in FIG. First, as shown in FIG. 4A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 72 for forming a through-hole conductor is formed at a predetermined position, and an opening 71 is formed in a portion corresponding to the built-in semiconductor chip 41.

  Next, electroless plating and electrolytic plating are performed, and the through-hole conductor 33 is formed on the inner wall of the through hole 72 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 71. Further, as shown in FIG. 4C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner wall of the opening 71 is also removed.

  Next, as shown in FIG. 4 (d), conductive bumps (bottom diameter: 200 μm, height: 160 μm, for example) that will become the interlayer connector 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 4E, an FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. The prepreg 12 </ b> A is provided with an opening in advance corresponding to the built-in semiconductor chip 41, similar to the insulating layer 13.

  In this lamination process, the head of the interlayer connector 32 is passed through the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 4E indicates that there are both cases where the head part is plastically deformed and crushed at this stage, and when it is not plastically deformed. By this step, the wiring layer 23 is located by sinking to the prepreg 12A side. The wiring board material obtained as described above is referred to as a wiring board material 2.

  Note that the steps shown in FIG. 4 may be performed as follows. In the stage of FIG. 4A, only the through hole 72 is formed and the subsequent steps from FIG. 4B to FIG. 4D are performed without forming the opening 71 for the built-in component. Next, as a process corresponding to FIG. 4E, prepreg 12A (without opening) is stacked. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 5 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked.

  In FIG. 5, the upper wiring board material 3 shown in FIG. 5 applies the same process as the lower wiring board material 1, and then the interlayer connector 34 and the prepreg 14 </ b> A are connected to the interlayer connector in the intermediate wiring board material 2 shown in FIG. 5. 32 and the prepreg 12A. However, there is no component (semiconductor chip 41) and no part (connection land) for connecting it, and the prepreg 14A is not provided with an opening for the semiconductor chip 41. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 14 </ b> A obtained by heating, the prepregs 12 </ b> A and 14 </ b> A are deformed into the space around the semiconductor chip 41 and the space inside the through-hole conductor 33, and no gap is generated. The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively. In this laminating step, the roughened surface 22a is provided on the surface of the wiring layer 22, thereby improving the adhesion and adhesion between the insulating layer 12 and the wiring layer 22, and the interlayer connector 32 and the wiring layer 22 The reliability of electrical connection is improved.

  After the laminating step shown in FIG. 5, the upper and lower metal foils 26A and 21A are patterned in a predetermined manner using well-known photolithography, and further, layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained. 5, the insulating layer 11 is a first insulating plate, the prepreg 12A and the insulating layer 13 are a fourth insulating plate, the prepreg 14A is a third insulating plate, and the insulating layer 15 is a second insulating plate. It corresponds to an insulating plate, respectively.

  As a modified example, the through-hole conductor 33 provided in the intermediate insulating layer 13 may naturally have a configuration similar to the interlayer connector 31 or 32. Further, the outer wiring layer 26 may be formed at the stage of the wiring board material 3 (for example, at a stage corresponding to FIG. 2D) other than being obtained by patterning after the last lamination step. .

  Next, another embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to another embodiment. In FIG. 6, the same reference numerals are given to the same or equivalent components as those appearing in the already described drawings. The explanation is omitted unless there is a matter to be explained.

  The wiring board of this embodiment has a semiconductor element 41A as a package product as a built-in (and requires electrical inspection during manufacturing) electric / electronic component. The semiconductor element 41A is an element based on a wafer level / chip scale package, and includes at least a semiconductor chip and a grid-shaped array of surface mounting terminals 41a formed on the semiconductor chip. The surface mounting terminal 41a is a terminal provided by rearranging the position of the surface mounting terminal 41a while being electrically conducted through the rewiring layer from the terminal pad originally possessed by the semiconductor chip. By such rearrangement, the arrangement density as a terminal is coarser than that of the terminal pad on the semiconductor chip, and the semiconductor element 41A is mounted on the connection land by the wiring layer 22 via the solder 45 by the surface mounting technique. can do.

  This embodiment is the same in that the electrical inspection can be performed in the manner shown in FIG. 3 during the manufacturing process. That is, it is possible to easily detect a connection failure state of the solder 45 that cannot be seen in the external appearance due to the mounting on the lower surface of the semiconductor element 41A, and the solder 45 to the connection land by the wiring pattern 22 and the wiring pattern 22 It is possible to electrically inspect the functions and performance including the mounted semiconductor element 41A via the inspection apparatus 100 (see FIG. 3). Therefore, only non-defective products in the manufacturing process at this stage can be input to the subsequent processes. Moreover, repair may be performed depending on circumstances, and it can be used for the subsequent processes after repairing to a non-defective product.

  In this embodiment, the roughened surface 22a is formed after the semiconductor element 41A is mounted on the wiring pattern 22. This is because the semiconductor element 41A is mounted on the wiring pattern 22 (connection land thereof) using the solder 45 and does not use the conductive bumps 42 as shown in FIG. In the connection using the solder 45, the connection reliability with the wiring pattern 22 is not a problem as much as the connection using the conductive bump 42. However, the roughened surface 22a may be formed before the semiconductor element 41A is mounted on the wiring pattern 22. When the roughened surface 22 a is formed after the semiconductor element 41 </ b> A is mounted on the wiring pattern 22, it can be used for the entire stacking process immediately after the roughening treatment of the wiring layer 22. Therefore, it is preferable in terms of maintaining the roughened state in the entire lamination process.

  Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to still another embodiment. In FIG. 7, the same reference numerals are given to the same or equivalent components as those appearing in the already described drawings. The explanation is omitted unless there is a matter to be explained.

  The wiring board of this embodiment has a surface-mount type passive element component 41B as a built-in (and requires an electrical inspection during manufacturing) electric / electronic component. The surface-mount type passive element component 41B has a planar size of, for example, 0.6 mm × 0.3 mm, has terminals at both ends, and has a lower side facing a connection land formed by the wiring layer 22. The terminals of the surface mount type passive element component 41 </ b> B and the connection lands are electrically and mechanically connected by solder 46.

  This embodiment is the same in that the electrical inspection can be performed in the manner shown in FIG. 3 during the manufacturing process. That is, it is possible to electrically detect a poor connection state of the solder 46 that is difficult to determine in appearance using the inspection apparatus 100 (see FIG. 3). Therefore, only non-defective products in the manufacturing process at this stage can be input to the subsequent processes. Moreover, repair may be performed depending on circumstances, and it can be used for the subsequent processes after repairing to a non-defective product.

  In this embodiment as well, the roughened surface 22a is formed after the component 41B is mounted on the wiring pattern 22. This is because the component 41B is mounted on the wiring pattern 22 (connection land thereof) using the solder 46 and is connected without using the conductive bumps 42 as shown in FIG. In the connection using the solder 46, the connection reliability with the wiring pattern 22 is not a problem as much as the connection using the conductive bump 42. However, the roughened surface 22a may be formed before the component 41B is mounted on the wiring pattern 22.

  DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material, 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 14 ... Insulating layer, 14A ... Prepreg, DESCRIPTION OF SYMBOLS 15 ... Insulating layer, 21 ... Wiring layer (2nd wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (1st wiring pattern), 22a ... Roughened surface, 22b ... Plating layer, 22A ... Metal foil (copper foil), 23 ... Wiring layer (third wiring pattern), 23A ... Metal foil (copper foil), 24 ... Wiring layer (wiring pattern), 24A ... Metal foil (copper foil), 25 ... Wiring Layer (another second wiring pattern), 26 ... wiring layer (wiring pattern), 26A ... metal foil (copper foil), 31 ... interlayer connector (conductive bump by conductive composition printing; first interlayer connection) Body), 32 ... interlayer connection body (conductive vane by conductive composition printing) Second interlayer connection), 34, 35 ... interlayer connection (conductive bumps formed by printing a conductive composition), 33 ... through-hole conductor, 41 ... semiconductor chip, 41A ... semiconductor element (chip scale package), 41a ... surface mount terminals, 41B ... surface mount passive element components, 42 ... conductive bumps (Au stud bumps; connection members), 45, 46 ... solder (connection members), 51 ... underfill resin, 61, 62 ... Solder resist, 71... Opening for parts, 72... Through hole, 100.

Claims (10)

A first insulating layer;
A second insulating layer, which is positioned in a stacked manner with respect to the first insulating layer, in which at least two insulating layers are stacked;
An electrical / electronic component having a terminal embedded in the second insulating layer;
A first wiring pattern including a connection land for the electric / electronic component sandwiched between the first insulating layer and the second insulating layer;
A connection member that electrically conducts between the terminal of the electrical / electronic component and the connection land of the first wiring pattern;
A second wiring pattern provided on the surface of the first insulating layer opposite to the surface on which the first wiring pattern is provided;
A first interlayer connector that penetrates the first insulating layer and electrically connects the first wiring pattern and the second wiring pattern;
A third wiring pattern provided between the at least two insulating layers of the second insulating layer; and
A second inter-layer connection body provided between the surface of the first wiring pattern and the surface of the third wiring pattern through a part of the second insulating layer in the stacking direction; ,
The component built-in wiring board, wherein each of the first wiring patterns connected to the connection land is not in contact with the first interlayer connection body.   2. The component built-in wiring board according to claim 1, wherein each of the first wiring patterns connected to the connection land is in contact with the second interlayer connection body.   The component built-in wiring board according to claim 1, wherein the second interlayer connection body is made of a conductive composition.   4. The component built-in wiring board according to claim 3, wherein the second interlayer connection body has a shape having an axis coinciding with the stacking direction and a diameter changing in the direction of the axis.   The component built-in wiring board according to claim 1, wherein the electric / electronic component is a surface-mounted passive element component. The electrical / electronic component is a semiconductor element having a semiconductor chip with terminal pads,
2. The component built-in wiring board according to claim 1, wherein the terminals of the electrical / electronic component are surface-mounting terminals arranged in a grid pattern and electrically connected to the terminal pads of the semiconductor chip. The electrical / electronic component is a semiconductor chip having terminal pads;
The terminal of the electrical / electronic component is the terminal pad of the semiconductor chip;
The connection member is a conductive bump that is sandwiched between the terminal pad of the semiconductor chip and the connection land of the first wiring pattern and electrically connects the terminal pad and the connection land. The component built-in wiring board according to claim 1, wherein:   The component built-in wiring board according to claim 1, wherein the first wiring pattern has a roughened surface on a side of the second insulating layer. A first insulating plate having a first surface and a second surface, a first metal foil laminated on the first surface, and a second metal laminated on the second surface Forming a laminated body having a foil and an interlayer connection body that penetrates the first insulating plate and electrically connects the first metal foil and the second metal foil;
The second metal foil of the laminate is patterned to form a first wiring pattern including connection lands for parts, and each of the first wiring patterns connected to the connection lands is in contact with the interlayer connection body. A step of forming so as not to cause
Electrically connecting an electrical / electronic component on the second surface of the first laminate using the connection land;
Using the first wiring pattern connected to the connection land as an electrical inspection pad, inspecting the electrical / electronic component, and selecting a good product;
Patterning a third metal foil laminated on a second insulating plate different from the first insulating plate to form a second wiring pattern;
Laminating a third insulating plate different from the first and second insulating plates on a surface of the second insulating plate on the side having the second wiring pattern;
In order to embed the electric / electronic component in a fourth insulating plate different from the first to third insulating plates, the fourth, third, And a step of integrating the second insulating plates in the order of the stacking positions.   After the step of patterning the second metal foil of the laminate and forming a first wiring pattern including connection lands for parts, the first insulating plate that is a non-defective product is laminated on the first insulating plate. The method further comprises a step of roughening the surface of the first wiring pattern before the step of integrating the fourth, third and second insulating plates in the order of the stacking positions. The manufacturing method of the component built-in wiring board of Claim 9.

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