JP2011018672A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

In a semiconductor device in which semiconductor chips are electrically connected to each other or between a semiconductor chip and a wiring board by means of bump electrodes, in particular, a technology capable of reducing the occurrence of connection failure even when the density of connection parts is increased and the pitch is reduced. I will provide a.
When a bump electrode BMP1 is pressed against a connection portion CNT, a beam BM constituting the connection portion CNT is bent (bent). Further, when the bump electrode BMP1 is pressed against the connection part CNT, the tip of the bump electrode BMP1 reaches the bottom surface of the cavity CA. At this time, a restoring force acts on the pushed and bent beam BM, and the bump electrode BMP1 inserted to the bottom surface of the cavity CA is sandwiched from the left and right. For this reason, the bump electrode BMP1 inserted into the cavity CA is fixed from the left and right by the restoring force of the beam BM.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device that electrically connects between semiconductor chips or between a semiconductor chip and a wiring board by means of bump electrodes, and a technique that is effective when applied to the manufacture thereof.

  In Japanese Patent Laid-Open No. 10-163267 (Patent Document 1), a heating process is not required, and a bump of a work with a bump can be easily fixed on a pad of a substrate. In addition, a technique for mounting a workpiece with bumps and a technique for providing a mounting substrate that can cope with the above is described. Specifically, a conductive portion composed of a first plating layer and a second plating layer is formed on a pad of the base material. The enormous part of the bump of the work with the bump is forcibly fitted into the hole of the conductive part, and the protruding part of the conductive part is locked to the edge of the enormous part. As a result, the bumps are prevented from coming out of the holes and can be brought into firm contact with the conductive parts.

  Japanese Patent Application Laid-Open No. 2004-12357 (Patent Document 2) describes a technique that can be applied to semiconductor devices and ultra-small pair chips that have a narrow pitch. Specifically, a spiral contact that is electrically connected to the connection terminal of the semiconductor device and has a spiral shape in plan view is provided on the insulating substrate. The spiral contactor can be deformed in accordance with the shape of the spherical connection terminal when contacting the spherical connection terminal on the insulating substrate so as to be electrically connected to the semiconductor device. It is configured. At this time, the spiral part and the width of the spiral contact are constant, and the thickness increases as it approaches the root from the tip.

  Japanese Patent Application Laid-Open No. 2004-354179 (Patent Document 3) describes a technique for reducing the cost and improving the reliability of a test socket for mounting an electronic component to perform a test. . Specifically, a through hole is formed at a position where a via for forming an interlayer connection is formed and a solder ball of the semiconductor device is connected in a test socket for mounting the semiconductor device and testing the semiconductor device. A substrate portion formed by laminating a plurality of base material layers formed with an electrode portion disposed on the substrate portion and electrically connected to the via and electrically connected to the semiconductor device is formed. The contact portion is provided. A slit is formed in the contact portion. Thereby, at the time of connection of a solder ball, a contact part is displaced with this connection. For this reason, the contact area between the solder ball and the contact portion can be increased, and the contact portion and the solder ball can be reliably electrically connected.

Japanese Patent Laid-Open No. 10-163267 JP 2004-12357 A JP 2004-354179 A

  In mobile devices such as cellular phones and digital cameras, so-called SIP (System In Package) in which a plurality of semiconductor chips are stacked and mounted inside one semiconductor package is widely used. This is because the mounting area can be reduced by stacking and arranging the semiconductor chips in comparison with the case where the semiconductor chips are arranged side by side on the plane (laying flat), and a large number of semiconductors with the same mounting area. This is because a chip can be mounted. That is, the mobile device is required to be downsized from the viewpoint of carrying convenience, and in order to realize this downsizing, SIP that can reduce the mounting area is used.

  In SIP, semiconductor chips are stacked, and the electrical connection between the stacked semiconductor chips is formed on, for example, terminals formed on a semiconductor chip disposed in a lower layer and semiconductor chips disposed on an upper layer. The bump electrodes are electrically connected with solder.

  In recent years, in order to reduce the size of semiconductor devices, it has been required to reduce the density and pitch of the connecting parts connecting the semiconductor chips. The terminals and bump electrodes arranged at a high density and a narrow pitch are soldered together. Need to connect. However, the connection using solder requires a step of heating and melting (reflowing) the solder. At this time, as the density of the connection portion composed of the terminals and bump electrodes increases and the pitch decreases, the solder flows when the solder is heated and melted. Therefore, it is formed on the terminals arranged at adjacent positions. There is a problem in that short-circuit defects occur due to bonding of the solders that are present.

  In the above, the case of using solder for connection between stacked semiconductor chips has been described by taking SIP as an example. However, the present invention is not limited to SIP in which semiconductor chips are stacked. For example, a semiconductor chip and a wiring board are flip-chip connected. Similar problems occur when connecting. In other words, even when bump electrodes formed on a semiconductor chip are connected to terminals formed on a wiring board by using solder, solder is applied as the bump electrodes and terminals increase in density and pitch. There is a problem of short circuit between the terminals.

  An object of the present invention is to provide a semiconductor device that electrically connects semiconductor chips or between a semiconductor chip and a wiring board by means of bump electrodes. It is to provide a technology that can be reduced.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a representative embodiment includes: (a) a first substrate; (b) a first conductor film formed on the first substrate and patterned; and (c) the first conductor film. (D) a second conductor film formed on the first conductor film and patterned so as to partially protrude into the cavity, and (e) the second conductor film. The opening part formed in this. The opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film that protrudes into the cavity functions as a beam. To do. At this time, the outline shape of the opening has a shape that borders the shape from the base of the beam protruding to the cavity to the tip, and the area on the plane of the opening is the plane of the beam It is larger than the upper area.

  A semiconductor device according to a representative embodiment includes (a) a first semiconductor substrate, (b) a hole reaching the element formation surface opposite to the back surface from the back surface of the first semiconductor substrate, and (c) And a patterned first conductor film formed on the back surface of the first semiconductor substrate including the inside of the hole. And (d) a cavity formed in the first conductor film formed on the back surface of the first semiconductor substrate, and (e) formed on the first conductor film, and a part of the cavity is formed. A second conductor film patterned to protrude into the cavity, and (f) an opening formed in the second conductor film. At this time, the opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film that protrudes into the cavity is a beam. Function. The contour shape of the opening has a shape that borders the shape of the beam protruding from the root of the beam to the tip, and the area on the plane of the opening is on the plane of the beam. It is characterized by being larger than the area.

  Further, the method of manufacturing a semiconductor device according to the representative embodiment includes (a) a step of forming a first conductor film on the first surface of the first substrate, and (b) a second step on the first conductor film. A step of forming a conductor film, (c) a step of forming an opening penetrating the second conductor film, and (d) wet etching the first conductor film using the opening as an etching hole. Forming a cavity in the first conductor film. The opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film that protrudes into the cavity becomes a beam. . Here, the outline shape of the opening has a shape that borders the shape of the beam protruding from the root of the beam to the tip, and the area on the plane of the opening is the plane of the beam It is larger than the upper area.

  Further, a method of manufacturing a semiconductor device according to a typical embodiment includes: (a) forming a hole reaching an electrode formed on an element formation surface opposite to the back surface from the back surface of the first semiconductor substrate; (B) forming a first conductor film on the back surface of the first semiconductor substrate including the inside of the hole; and (c) forming a second conductor film on the first conductor film. And (d) patterning the second conductor film to form an opening in the second conductor film formed on the back surface of the first semiconductor substrate; and (e) forming the opening. Forming a cavity in the first conductor film by wet-etching the first conductor film as an etching hole. Here, the opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film that protrudes into the cavity is a beam. Become. At this time, the outline shape of the opening has a shape that borders the shape from the base of the beam protruding to the cavity to the tip, and the area on the plane of the opening is the plane of the beam It is larger than the upper area.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the semiconductor device in which the semiconductor chips are electrically connected between the semiconductor chips or between the semiconductor chips and the wiring board by the bump electrodes, it is possible to reduce the occurrence of connection failure.

It is sectional drawing which shows the structure of the connection part currently formed in the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which made the semiconductor chip in which the connection part was formed, and the semiconductor chip in which the bump electrode was made to oppose. It is sectional drawing which shows an example of the connection state of a connection part and a bump electrode. It is sectional drawing which made the semiconductor chip in which the connection part was formed, and the semiconductor chip in which the bump electrode was made to oppose. It is sectional drawing which shows another example of the connection state of a connection part and a bump electrode. It is sectional drawing which made the semiconductor chip in which the connection part was formed, and the semiconductor chip in which the bump electrode was made to oppose. It is sectional drawing which shows another example of the connection state of a connection part and a bump electrode. It is sectional drawing which shows the example arrange | positioned so that the position of a connection part and the position of a terminal may overlap in a plane. It is a figure which shows the dimension of the main components which comprise a connection part, and the dimension of the front-end | tip part of a bump electrode. It is a figure which shows the planar structure of a connection part. It is a figure which shows the structure of the connection part of a comparative example. It is a figure which shows a mode that a lower layer semiconductor chip and an upper layer semiconductor chip are laminated | stacked. It is sectional drawing which shows a mode that a lower layer semiconductor chip and an upper layer semiconductor chip are laminated | stacked. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 6 is a diagram showing a connection part and a through electrode formed on a semiconductor substrate in a second embodiment. It is sectional drawing which shows the structure of the semiconductor substrate in which the connection part and the penetration electrode were formed. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29; FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 30; FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 31; FIG. 33 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 32; FIG. 34 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 33; FIG. 35 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 34; FIG. 36 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 35; FIG. 37 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 36; FIG. 38 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 37; FIG. 39 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 38; FIG. 40 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 39; FIG. 41 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 40; FIG. 42 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 41; FIG. 43 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 42; FIG. 44 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 43; It is a figure which shows a mode that a several semiconductor chip is laminated | stacked. It is sectional drawing which shows a mode that a several semiconductor chip is laminated | stacked.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
In the first embodiment, an example in which a plurality of semiconductor chips are stacked will be mainly described. As a method for electrically connecting a plurality of stacked semiconductor chips, bump electrodes are formed on the upper semiconductor chip, terminals are formed on the lower semiconductor chip, and bumps are formed on the upper semiconductor chip. A method is conceivable in which the electrode is connected to the terminal formed in the lower layer using solder.

  In recent years, in order to reduce the size of semiconductor devices, it has been required to reduce the density and pitch of the connecting parts connecting the semiconductor chips, and the terminals arranged at high density and the narrow pitch are connected to the bump electrodes with solder. There is a need to. At this time, the connection using solder requires a step of heating and melting (reflowing) the solder. However, as the density of the connection parts composed of terminals and bump electrodes is increased and the pitch is reduced, the solder fluidizes when the solder is heated and melted. Therefore, it is formed on the terminals arranged at adjacent positions. There is a risk that short-circuit defects may occur due to the joining of existing solders. In other words, the method of connecting the upper semiconductor chip and the lower semiconductor chip using solder shorts between adjacent terminals as the terminals connecting the semiconductor chips and the bump electrodes increase in density and pitch. It has become difficult to connect the terminal and the bump electrode without any problems.

  Therefore, in the first embodiment, a device for electrically connecting the upper semiconductor chip and the lower semiconductor chip is used without using solder. Hereinafter, a device for electrically connecting the upper semiconductor chip and the lower semiconductor chip will be described. In the first embodiment, a bump electrode is formed on the upper semiconductor chip, and a connection portion of the lower semiconductor chip electrically connected to the bump electrode is devised.

  FIG. 1 is a cross-sectional view showing a configuration of a connection portion CNT formed in a lower semiconductor chip. In FIG. 1, a semiconductor element (not shown) such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on the upper surface (main surface, element forming surface) of a semiconductor substrate 1S. An interlayer insulating film IL is formed on the semiconductor substrate 1S on which the semiconductor element is formed. A multilayer wiring (not shown) is formed in the interlayer insulating film IL, and the multilayer wiring is electrically connected to a semiconductor element formed on the semiconductor substrate 1S. Further, a terminal (substrate electrode) TE is formed on the uppermost layer of the interlayer insulating film IL.

  A copper film CF is formed on the interlayer insulating film IL on which the terminals TE are formed, and a nickel film NF is formed on the copper film CF. A gold film AF is formed on the surface of the nickel film NF. At this time, the connection part CNT is formed by processing the copper film CF, the nickel film NF, and the gold film AF formed on the interlayer insulating film IL. Specifically, the connection part CNT has an opening OP formed so as to penetrate the gold film AF and the nickel film NF. Then, the copper film CF exposed from the opening OP is removed, and a cavity CA is formed in the copper film CF. At this time, the size of the cavity CA formed in the copper film CF is larger than the size of the opening OP formed in the nickel film NF and the gold film AF. Therefore, the beam BM made of the nickel film NF and the gold film AF protrudes from the cavity CA. That is, the connection part CNT in the first embodiment includes the copper film CF, the nickel film NF, and the gold film AF as components, the cavity CA is formed in the copper film CF, and the nickel film NF and the gold film AF are formed. It has a structure in which an opening OP is formed. Since the cavity CA includes the opening OP, and the size of the cavity CA is larger than the size of the opening OP, the cavity CA is formed of the nickel film NF and the gold film AF. A beam BM is formed. Note that the copper film CF, the nickel film NF, and the gold film AF also function as a wiring connected to the connection portion CNT.

  The cavity CA and the opening OP constituting the connection part CNT are connected and integrated. The copper film CF constituting the connection part CNT has a function of forming the cavity part CA and electrically connecting the terminal TE and the connection part CNT. The nickel film NF constituting the connection part CNT is a film for constituting the beam BM, and the rigidity of the beam BM is determined by the film thickness of the nickel film NF. That is, the nickel film NF is a film that functions as the beam BM, and the nickel film NF is used as the beam BM because it has high rigidity. The gold film AF formed on the nickel film NF is a film formed for connecting the connection portion CNT and the bump electrode with low resistance.

  The connection part CNT in the first embodiment is configured as described above, and a connection form between the connection part CNT and the bump electrode will be described below. That is, a connection structure between the lower semiconductor chip on which the connection part CNT is formed and the upper semiconductor chip on which the bump electrode is formed will be described.

  FIG. 2 is a diagram in which the semiconductor substrate 1S (lower semiconductor chip) on which the connection portion CNT is formed and the semiconductor substrate 2S (upper semiconductor chip) on which the bump electrode BMP1 is formed are opposed to each other. In FIG. 2, the configuration of the connection portion CNT formed in the semiconductor substrate 1S is the same as that described in FIG. On the other hand, a semiconductor element such as a MISFET is formed on the lower surface (main surface, element formation surface) of FIG. 2 on the semiconductor substrate 2S, and an interlayer insulating film IL2 is formed on the semiconductor substrate 2S on which the semiconductor element is formed. ing. A multilayer wiring is formed in the interlayer insulating film IL2, and the multilayer wiring is electrically connected to a semiconductor element formed on the semiconductor substrate 2S. A pad is formed on the uppermost layer of the interlayer insulating film IL2, and a bump electrode BMP1 is formed on the pad.

  The bump electrode BMP1 is made of, for example, a gold film formed by a plating method. The bump electrode BMP1 formed by the plating method in this way has a characteristic that it is difficult to deform because the material (gold film) of the bump electrode BMP1 is not melted.

  The semiconductor substrate 2S on which the bump electrode BMP1 is formed is connected to the semiconductor substrate 1S on which the connection portion CNT is formed. Specifically, as shown in FIG. 2, alignment between the connection portion CNT formed on the semiconductor substrate 1S and the bump electrode BMP1 formed on the semiconductor substrate 2S is performed. After that, by applying a load to the upper semiconductor substrate 2S, the bump electrodes BMP1 formed on the upper semiconductor substrate 2S are pressed against the connection portions CNT formed on the lower semiconductor substrate 1S. Thereby, as shown in FIG. 3, the upper bump electrode BMP1 and the lower connection portion CNT are connected. Specifically, FIG. 3 is a diagram illustrating a connection state between the bump electrode BMP1 and the connection portion CNT. In FIG. 3, by pressing the bump electrode BMP1 against the connection portion CNT, the beam BM constituting the connection portion CNT bends (bends). Further, when the bump electrode BMP1 is pressed against the connection part CNT, the tip of the bump electrode BMP1 reaches the bottom surface of the cavity CA. At this time, a restoring force acts on the pushed and bent beam BM, and the bump electrode BMP1 inserted to the bottom surface of the cavity CA is sandwiched from the left and right. For this reason, the bump electrode BMP1 inserted into the cavity CA is fixed from the left and right by the restoring force of the beam BM. In this way, the bump electrode BMP1 can be connected to the connection portion CNT.

  At this time, the semiconductor element formed on the semiconductor substrate 2S is electrically connected to the multilayer wiring formed on the interlayer insulating film IL2 and the bump electrode BMP1 formed on the multilayer wiring. The bump electrode BMP1 is connected to the connection part CNT. Specifically, since the bump electrode BMP1 is fixed by the beam BM, the bump electrode BMP1 is connected to the nickel film NF and the gold film AF constituting the beam BM. Since the nickel film NF is connected to the copper film CF, and the copper film CF is connected to the terminal TE formed on the interlayer insulating film IL1, the bump electrode BMP1 is connected via the connection portion CNT. Connected to terminal TE. Further, the terminal TE is connected to the multilayer wiring formed in the interlayer insulating film IL1 and the semiconductor element formed in the lower layer of the multilayer wiring. Therefore, by connecting the bump electrode BMP1 formed on the semiconductor substrate 2S and the connection part CNT formed on the semiconductor substrate 1S, the semiconductor element formed on the semiconductor substrate 2S and the semiconductor substrate 1S are formed. It is possible to electrically connect the semiconductor element. Here, the beam BM constituting the connection portion CNT is connected to the bump electrode BMP1, but since the gold film AF is formed on the surface of the beam BM, the contact resistance between the bump electrode BMP1 and the connection portion CNT. Can be reduced.

  As described above, the first feature of the first embodiment is that, as shown in FIG. 3, by inserting the bump electrode BMP2 formed on the semiconductor substrate 2S into the connection portion CNT formed on the semiconductor substrate 1S, The connection portion CNT and the bump electrode BMP1 are connected. Specifically, the connection part CNT is formed between the beam BM, the cavity CA formed in the copper film CF, the beam BM made of the nickel film NF and the gold film AF formed on the cavity CA. By constituting the opening OP, the bump electrode BMP1 can be inserted into the cavity CA from the opening OP, and the bump electrode BMP1 can be fixed by the restoring force of the deformed beam BM by inserting the bump electrode BMP1. . As a result, according to the first embodiment, the bump electrode BMP1 and the connection part CNT can be connected without using solder. That is, in the first embodiment, the bump electrode BMP1 is inserted into the cavity CA, and the bump electrode BMP1 is fixed by a restoring force due to deformation of the beam BM arranged so as to protrude into the cavity CA. ing. For this reason, in this Embodiment 1, bump electrode BMP1 can be mechanically fixed to the connection part CNT, without using solder. This is because no solder is used to connect the bump electrode BMP1 and the connection part CNT, so even if the density of the connection part CNT and the bump electrode BMP1 is increased or the pitch is reduced, the adjacent connection parts CNT are adjacent to each other. This means that short-circuit defects between the bump electrodes BMP1 can be suppressed. In other words, in the first embodiment, since the molten solder is not used for the connection between the bump electrode BMP1 and the connection part CNT, it is possible to suppress a short circuit failure due to a solder bridge and improve the reliability of the semiconductor device. It can be done.

  2 and 3, for example, the bump electrode BMP1 that is difficult to deform formed by plating is inserted and connected to the connection part CNT. Next, the bump electrode BMP2 that is easy to deform is connected to the connection part CNT. An example of inserting and connecting to the network will be described.

  FIG. 4 is a diagram in which a semiconductor substrate 1S (lower semiconductor chip) on which the connection portion CNT is formed and a semiconductor substrate 2S (upper semiconductor chip) on which the bump electrode BMP2 is formed are opposed to each other. In FIG. 4, the configuration of the connection portion CNT formed in the semiconductor substrate 1S is the same as that described in FIG. On the other hand, the bump electrode BMP2 formed on the semiconductor substrate 2S is different in formation method from the bump electrode BMP1 described in FIG. That is, the bump electrode BMP2 in FIG. 4 is composed of a bump electrode that is easily deformed, such as a stud bump electrode. The stud bump electrode is a bump electrode formed by melting a gold wire and pressing it against a mold called a capillary, and has a characteristic of being easily deformed because it is once melted.

  The semiconductor substrate 2S on which the bump electrode BMP2 is formed is connected to the semiconductor substrate 1S on which the connection portion CNT is formed. Specifically, as shown in FIG. 4, the alignment of the connection portion CNT formed on the semiconductor substrate 1S and the bump electrode BMP2 formed on the semiconductor substrate 2S is performed. After that, by applying a load to the upper semiconductor substrate 2S, the bump electrodes BMP2 formed on the upper semiconductor substrate 2S are pressed against the connection portions CNT formed on the lower semiconductor substrate 1S. As a result, as shown in FIG. 5, the upper bump electrode BMP2 is connected to the lower connection portion CNT. Specifically, FIG. 5 is a diagram illustrating a connection state between the bump electrode BMP2 and the connection portion CNT. In FIG. 5, by pressing the bump electrode BMP2 against the connection part CNT, the beam BM constituting the connection part CNT bends (bends). Further, when the bump electrode BMP2 is pressed against the connection part CNT, the tip of the bump electrode BMP2 reaches the bottom surface of the cavity CA. At this time, a restoring force acts on the pushed and bent beam BM, and the bump electrode BMP2 inserted up to the bottom surface of the cavity CA is sandwiched from the left and right. For this reason, the bump electrode BMP2 inserted into the cavity CA is fixed from the left and right by the restoring force of the beam BM. Furthermore, when a load is applied to the bump electrode BMP2 in this state, the bump electrode BMP2 is plastically deformed, and the tip end portion of the bump electrode BMP2 spreads in the lateral direction. As a result, in addition to the restoring force of the beam BM, the beam BM and the bump electrode BMP2 are caulked, so that the bonding force between the bump electrode BMP2 and the connection portion CNT is improved. In this way, the bump electrode BMP2 can be connected to the connection part CNT.

  Next, an example in which a hemispherical and relatively soft bump electrode BMP3 is inserted and connected to the connection portion CNT will be described. FIG. 6 is a diagram in which the semiconductor substrate 1S (lower semiconductor chip) on which the connection portion CNT is formed and the semiconductor substrate 2S (upper semiconductor chip) on which the bump electrode BMP3 is formed are opposed to each other. In FIG. 6, the configuration of the connection portion CNT formed in the semiconductor substrate 1S is the same as that described in FIG. On the other hand, the bump electrode BMP3 formed on the semiconductor substrate 2S is different in material from the bump electrode BMP1 described with reference to FIG. 2 and the bump electrode BMP2 described with reference to FIG. The bump electrode BMP3 made of this solder has a hemispherical shape and a relatively soft structure.

  The semiconductor substrate 2S on which the bump electrode BMP3 described above is formed and the semiconductor substrate 1S on which the connection portion CNT is formed are connected. Specifically, as shown in FIG. 6, alignment between the connection portion CNT formed on the semiconductor substrate 1S and the bump electrode BMP3 formed on the semiconductor substrate 2S is performed. After that, by applying a load to the upper semiconductor substrate 2S, the bump electrodes BMP3 formed on the upper semiconductor substrate 2S are pressed against the connection portions CNT formed on the lower semiconductor substrate 1S. Thereby, as shown in FIG. 7, the upper bump electrode BMP3 and the lower connection portion CNT are connected. Specifically, FIG. 7 is a diagram illustrating a connection state between the bump electrode BMP3 and the connection portion CNT. In FIG. 7, when the bump electrode BMP3 is pressed against the connection portion CNT, the beam BM constituting the connection portion CNT starts to bend, and the soft bump electrode BMP3 is also deformed along the deflection of the beam BM. Further, when the bump electrode BMP3 is pressed against the connection part CNT, the tip of the bump electrode BMP3 reaches the bottom surface of the cavity CA. At this time, a restoring force acts on the pushed and bent beam BM, and the bump electrode BMP3 inserted up to the bottom surface of the cavity CA is sandwiched from the left and right. For this reason, the bump electrode BMP3 inserted into the cavity CA is fixed from the left and right by the restoring force of the beam BM. In this way, the bump electrode BMP3 can be connected to the connection part CNT.

  From the above, it can be seen that the connection part CNT in the first embodiment can be connected to the bump electrodes BMP1 to BMP3 of various materials and shapes. That is, the connection part CNT according to the first embodiment can connect the semiconductor substrate 1S (lower semiconductor chip) and the semiconductor substrate 2S (upper semiconductor chip) regardless of the type of the bump electrodes BMP1 to BMP3. .

  Next, the positional relationship between the connection part CNT and the terminal TE in the first embodiment will be described. For example, in FIGS. 1 to 7, the position of the connection portion CNT and the position of the terminal TE are formed at positions that are separated in a plane. In this case, the electrical connection between the connection part CNT and the terminal TE is performed by the copper film CF constituting the connection part CNT. That is, when the bump electrodes BMP1 to BMP3 are connected to the connection portion CNT, the bump electrodes BMP1 to BMP3 come into contact with the beam BM. The beam BM is formed of a laminated film of a nickel film NF and a gold film AF, and is electrically connected to the copper film CF. Further, the copper film CF is connected to the terminal TE. Therefore, the bump electrodes BMP1 to BMP3 are connected to the terminal TE by the copper film CF via the connection part CNT. At this time, if the bump electrodes BMP1 to BMP3 are in contact with the beam BM, the bump electrode BMP1 to BMP3 and the terminal can be inevitably connected to the terminal TE through the copper film CF connected to the beam BM. TE can be stably connected.

  On the other hand, for example, in FIG. 8, the position of the connection portion CNT and the position of the terminal TE are arranged so as to overlap in a plane. In other words, the terminal TE is formed at the bottom of the cavity CA constituting the connection part CNT. In this case, the terminal TE formed at the bottom of the cavity CA and the bump electrode BMP can be directly connected. Therefore, since it is not necessary to arrange the terminal TE in the peripheral part of the connection part CNT, a space for forming a connection structure including the connection part CNT and the terminal TE can be reduced. As a result, the connection structure shown in FIG. 8 has an advantage that the miniaturization of the semiconductor device can be promoted.

  As shown in FIG. 9, the first feature point of the first embodiment is that the connection part CNT includes a cavity CA formed in the copper film CF, and a nickel film NF and a gold film formed on the cavity CA. By constituting the beam BM made of AF and the opening OP formed between the beams BM, the bump electrode BMP was inserted into the cavity CA from the opening OP and deformed by inserting the bump electrode BMP. The bump electrode BMP is fixed by the restoring force of the beam BM. With this first feature point, the bump electrode BMP can be connected to the connection portion CNT. However, from the viewpoint of improving the connection between the bump electrode BMP and the connection portion CNT, it is desirable that the following relationship is satisfied. . This relationship will be described with reference to FIG.

  First, FIG. 9 is a diagram showing the dimensions of main components constituting the connection part CNT and the dimensions of the tip of the bump electrode BMP. In FIG. 9, the diameter of the opening OP is a. That is, in other words, the diameter of the opening OP is a distance between the tip portions of the plurality of beams BM. The diameter of the tip of the bump electrode BMP is b. At this time, it is desirable that the condition a <b is satisfied. This is because if the diameter (a) of the opening OP is smaller than the diameter (b) of the tip of the bump electrode BMP, when the bump electrode BMP is inserted into the opening OP, the bump electrode BMP contacts the beam BM, and the bump This is because the beam BM is deformed as the electrode BMP is inserted, and the inserted bump electrode BMP can be fixed by the restoring force of the deformed beam BM.

  The length of the beam BM is c, and the depth of the cavity CA is d. In other words, the depth of the cavity CA can be said to be the thickness of the copper film CF. At this time, it is desirable that the condition c <d is satisfied. This is because if the length (c) of the beam BM is smaller than the depth (d) of the cavity CA, the beam BM contacts the bottom of the cavity CA when the bump electrode BMP is inserted into the cavity CA. This is because it is possible to suppress the insertion of the bump electrode BMP into the cavity CA and the bending of the beam BM in contact with the bottom of the cavity CA. By satisfying these conditions (a <b, c <d), the connection between the bump electrode BMP and the connection part CNT can be improved.

  In the above description, the feature (first feature point) of the connection portion CNT in the first embodiment has been described from the viewpoint of the cross-sectional structure. Next, a further feature of the connection portion CNT in the first embodiment is described as a planar structure. This will be explained from the viewpoint.

  FIG. 10 is a diagram showing a planar structure of the connection part CNT in the first embodiment. In FIG. 10, the connection part CNT is formed on the semiconductor substrate 1S. The connection part CNT has a conductor film CON (nickel film NF + gold film AF) formed on the semiconductor substrate 1S, and an opening OP penetrating the conductor film CON is formed in the conductor film CON. . A cavity CA integrated with the opening OP is formed below the opening OP. The cavity CA includes the opening OP in a plan view, and is formed so that the size of the cavity CA is larger than the size of the opening OP. A plurality of beams BM made of the conductor film CON are formed on the opening OP, and the plurality of beams BM are formed so as to protrude into the opening OP. In the connection portion CNT configured as described above, a cross section cut along the line AA in FIG. 10 corresponds to, for example, FIG.

  The second feature point of the first embodiment is that the opening OP is included in the cavity CA in a plane, the opening OP and the cavity CA are integrated, and the cavity CA of the conductor film CON. In the connection portion CNT where the portion protruding to the beam BM is, the contour shape of the opening OP has a shape that borders the shape from the root of the beam BM protruding to the cavity CA to the tip portion. is there. That is, the opening OP in the first embodiment is greatly opened from the base of the beam BM to the tip between the adjacent beams BM. In particular, the area on the plane of the opening OP is larger than the area on the plane of the beam BM. Thereby, the cavity CA formed in the lower layer of the opening OP can be easily made.

  Specifically, in the first embodiment, the cavity CA is formed by wet etching the base film (copper film) exposed from the opening OP. At this time, the contour shape of the opening OP has a shape that borders the shape from the base of the beam BM protruding into the cavity CA to the tip, and the base of the beam BM is between the adjacent beams BM. If the opening is wide from the tip to the tip, the surface area of the base film exposed from the opening OP increases. In this case, there is an advantage that the circulation of the etching solution is improved and the etching rate is increased. Furthermore, the etching area for forming the cavity CA under the opening OP can also be reduced. That is, the cavity CA is for forming a cavity in the lower layer of the beam BM. However, the shape of the opening OP is greatly opened from the root of the beam BM to the tip between the adjacent beams BM. In this case, since the surface area of the base film exposed from the opening OP increases, etching proceeds from each of the large exposed areas. For this reason, the cavity CA formed in the lower layer of the beam BM can be formed with a smaller etching amount. Thus, according to the first embodiment, the contour shape of the opening OP has a shape that borders the shape from the root of the beam BM protruding to the cavity CA to the tip, and the adjacent beam BM In the meantime, since the shape is wide open from the base to the tip of the beam BM (second feature point), the etching amount for forming the cavity CA can be reduced, and the etching rate can be reduced. Can be faster. This means that the processing time for forming the cavity portion CA is shortened, and thus the cost can be reduced. In particular, when the area on the plane of the opening OP is larger than the area on the plane of the beam BM, the above-described effect is increased.

  Here, for example, consider the structure of the connecting portion CNT2 as shown in FIG. The connection portion CNT2 has a circular opening OPT formed at the center, and a beam BM2 formed outside the opening OPT. At this time, the beam BM2 is divided by the slits SL formed radially from the opening OPT to form the beam BM2. In such a connection part CNT2, it is considered that a hollow part is formed below the opening OPT. In this case, the cavity CA is formed in the lower layer of the beam BM by performing wet etching on the base film exposed from the opening OPT.

  However, in the configuration of the connection part CNT2, unlike the connection part CNT of the first embodiment, the contour shape of the opening OPT has a shape that borders the shape from the root to the tip of the beam BM2 protruding into the cavity. It is not opened between the adjacent beams BM2 from the base to the tip of the beam BM2. That is, in the connection part CNT2, only a linear slit SL is formed between the adjacent beams BM2. For this reason, the etching solution enters only from the opening OPT, and the etching for forming the cavity proceeds concentrically from the opening OPT as shown in FIG. In this case, since the exposed area exposed from the opening OPT is small, the circulation of the etching solution is deteriorated, and since the surface area of the exposed area is small, the simultaneously etched area is also narrowed. Furthermore, since etching proceeds concentrically, the amount of etching that forms a cavity in the entire lower layer of the beam BM2 also increases. This means that the processing time for forming the cavity becomes longer, and this causes an increase in cost.

  On the other hand, in the first embodiment, the contour shape of the opening OP has a shape that borders the shape from the root to the tip of the beam BM protruding into the cavity CA, and between the adjacent beams BM. In FIG. 2, the shape of the beam BM is greatly opened from the base to the tip (second feature point), so that the etching amount for forming the cavity CA can be reduced and the etching rate can be reduced. It has the advantage of being fast.

  Further, in the first embodiment, another effect is also achieved by the second feature point described above. For example, in a structure in which a bump electrode is inserted into the connection portion CNT and a plurality of semiconductor chips are stacked, a resin called underfill is injected between the plurality of semiconductor chips. This underfill has a function of suppressing an exfoliation caused by a difference in thermal expansion coefficient between materials and enhancing an adhesion effect when a thermal load is applied to the semiconductor device. At this time, as in the connection portion CNT of the first embodiment, if the shape is wide open from the root of the beam BM to the tip portion between the adjacent beams BM, this connection portion CNT Even after the bump electrode BMP is inserted into the gap, a gap is generated at the base of each beam BM. Therefore, when the underfill is injected between the semiconductor chips, the underfill is filled up to the inside of the connection portion CNT through the gap generated at the base of the beam BM. For this reason, the connection strength between the connection portion CNT and the bump electrode BMP inserted in the connection portion CNT is improved by filling the gap with an underfill. That is, according to the first embodiment, the contour shape of the opening OP has a shape that borders the shape from the root to the tip of the beam BM protruding into the cavity CA, and between the adjacent beams BM. In this case, the configuration in which the beam BM has a large opening from the base to the tip portion not only shortens the etching processing time but also improves the connection strength between the connection portion CNT and the bump electrode BMP. It can be planned.

  Next, the third feature point in the first embodiment will be described. The third feature point in the first embodiment is in the device for the structure of the beam BM. Specifically, as shown in FIG. 10, the width of the beam BM is characterized in that it increases from the tip of the beam BM toward the root of the beam BM. That is, the beam BM is composed of a so-called equal strength beam. Thereby, when the bump electrode BMP is inserted into the connection part CNT via the beam BM, the stress applied to the beam BM can be made uniform, and the resistance to the stress of the beam BM can be improved.

  For example, when the width of the beam BM is the same from the tip to the base, the stress applied to the beam BM is concentrated at the base. Then, the beam BM may be broken from the root. Therefore, by configuring the beam BM so that the width of the beam BM increases from the tip toward the base, it is possible to improve resistance to the stress at the base of the beam BM. That is, the stress applied to the entire beam BM can be made uniform by increasing the width of the beam BM from the tip to the base. As a result, it is possible to prevent an excessive stress from being applied to the base of the beam BM, and to improve the resistance of the beam BM to bending stress. Therefore, according to the first embodiment, the strength of the beam BM can be ensured and the reliability of the connection portion CNT can be improved by the third feature point in which the beam BM has a so-called equal strength beam structure. can do.

  Furthermore, in this Embodiment 1, the front-end | tip part and base shape of the beam BM are rounded. Thereby, when a load is added to the beam BM, it can suppress that a load concentrates on a front-end | tip part or a root. FIG. 10 shows an example in which four beams BM are formed in the connection part CNT. However, the present invention is not limited to this, and there may be more than four, such as five or six, There may be fewer than four, such as two. Further, only one beam BM may be formed.

  The connection part CNT in the first embodiment is configured as described above. Hereinafter, a plurality of semiconductor chips are electrically connected by the connection part CNT and the bump electrode BMP, and three-dimensionally stacked. A connection example will be described.

  FIG. 12 is a diagram illustrating a state in which a semiconductor substrate (lower semiconductor chip) 1S and a semiconductor substrate (upper semiconductor chip) 2S are stacked. In FIG. 12, a plurality of connection portions CNT are formed on the lower semiconductor substrate 1S, and a plurality of bump electrodes are formed on the upper semiconductor substrate 2S. The semiconductor substrate 1S has a rectangular shape (square shape), and a plurality of connection portions CNT are arranged along the peripheral portion (side) of the semiconductor substrate 1S. For example, the plurality of connection parts CNT formed on the semiconductor substrate 1S are arranged in a peripheral arrangement, but the arrangement of the connection parts CNT is not limited to the peripheral arrangement. On the other hand, the semiconductor substrate 2S also has a rectangular shape (square shape), and a plurality of bump electrodes BMP are formed along the peripheral portion (side) of the semiconductor substrate 2S. The bump electrode BMP is disposed so as to correspond to the connection part CNT.

  FIG. 13 is a cross-sectional view showing a state in which the connection portion CNT formed on the semiconductor substrate 1S is connected to the bump electrode BMP formed on the semiconductor substrate 2S. As shown in FIG. 13, each of the bump electrodes BMP formed on the semiconductor substrate 2S is inserted into each of the connection portions CNT formed on the semiconductor substrate 1S. Thus, the semiconductor substrate 1S and the semiconductor substrate 2S can be three-dimensionally stacked while being electrically connected. That is, in the first embodiment, as shown in FIG. 13, the bump electrode BMP is inserted into the cavity CA, and the restoring force due to the deformation of the beam BM arranged to protrude into the cavity CA is used. Is configured to be fixed. For this reason, in Embodiment 1, the bump electrode BMP can be mechanically fixed to the connection part CNT without using solder. Therefore, since solder is not used for the connection between the bump electrode BMP and the connection part CNT, even if the connection part CNT and the bump electrode BMP have a high density or a narrow pitch, the adjacent connection parts CNT or between the adjacent bump electrodes Short circuit failure between BMPs can be suppressed. In other words, in the first embodiment, since the molten solder is not used for the connection between the bump electrode BMP and the connection portion CNT, it is possible to suppress a short circuit failure due to a solder bridge, and to improve the reliability of the semiconductor device. be able to.

  At this time, in the first embodiment, as shown in FIG. 10, the strength of the beam BM can be ensured by adopting a so-called equal strength beam structure for the beam BM (third feature point). The reliability of the connection part CNT can be improved.

  Further, underfill UF is injected between the semiconductor substrate 1S and the semiconductor substrate 2S. In the first embodiment, as shown in FIG. 10, the contour shape of the opening OP has a shape that borders the shape from the root of the beam BM protruding to the cavity CA to the tip, and the adjacent beam Since the beam BM has a large opening from the base to the tip of the beam BM (second feature point), each beam BM is inserted even after the bump electrode BMP is inserted into the connection portion CNT. There is a gap at the base of Accordingly, when the underfill UF is injected between the semiconductor substrate 1S and the semiconductor substrate 2S, the underfill UF is filled into the connection portion CNT through the gap generated at the base of the beam BM. For this reason, the connection strength between the connection part CNT and the bump electrode BMP inserted in the connection part CNT is improved.

  12 and 13, the example in which the semiconductor substrate (semiconductor chip) 1S and the semiconductor substrate (semiconductor chip) 2S are three-dimensionally stacked has been described. However, the connection portion CNT and the bump electrode in the first embodiment are described. Connection by BMP can also be applied to connection between a semiconductor substrate (semiconductor chip) and a wiring substrate. For example, the connection portion is formed on the wiring substrate, and the bump electrode is formed on the semiconductor substrate. Then, by inserting the bump electrode formed on the semiconductor substrate into the connection portion formed on the wiring substrate, the wiring substrate and the semiconductor substrate can be connected (flip chip connection).

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. In the semiconductor device manufacturing method described below, a process of forming the connection portion CNT which is a feature of the first embodiment will be described.

  First, as shown in FIG. 14, a semiconductor element (not shown) such as a MISFET is formed on the upper surface (main surface, element formation surface) of the semiconductor substrate 1S by using a normal technique. Then, an interlayer insulating film IL is formed on the semiconductor element on which the semiconductor element is formed. Thereafter, a multilayer wiring (not shown) is formed between the interlayer insulating films IL, and a terminal TE is formed on the uppermost layer of the interlayer insulating film IL. At this time, the terminal TE formed in the uppermost layer of the interlayer insulating film IL is electrically connected to the semiconductor element formed in the semiconductor substrate 1S via the multilayer wiring formed in the interlayer insulating film IL. It is connected.

  Next, as shown in FIG. 15, a copper film CF is formed on the interlayer insulating film IL on which the terminals TE are formed. The copper film CF can be formed, for example, by using a sputtering method. In this copper film CF, the cavity is formed in the lower layer of the beam by wet etching in a process described later to form the connection part CNT, so that the movable range of the beam is sufficiently obtained. Thickness is set. For example, the film thickness of the copper film CF is about 10 μm. In addition to the sputtering method, the copper film CF can be formed by forming a copper film CF having a thickness of 0.3 μm to 1 μm by a sputtering method and then forming a copper film CF having a thickness of 10 μm by an electrolytic plating method.

  Subsequently, as shown in FIG. 16, a nickel film NF is formed on the copper film CF. The nickel film NF can be formed, for example, by using a sputtering method. The nickel film NF is a member constituting a beam to be described later, and the rigidity of the beam, that is, the spring constant of the beam is determined by the thickness of the nickel film NF. When the bump electrode is inserted into the beam, it is necessary to obtain a sufficient bonding force by the restoring force of the beam, and the restoring force of the beam is determined by the thickness of the nickel film NF. Therefore, the thickness of the nickel film NF is, for example, 5 μm.

  Thereafter, as shown in FIG. 17, a gold film AF is formed on the nickel film NF. The gold film AF can be formed, for example, by using a sputtering method. Since the gold film AF is a film provided for reducing the contact resistance between the beam and the bump electrode, the gold film AF may be thin. For example, the film thickness of the gold film AF is about 0.2 μm.

  Next, as shown in FIG. 18, after applying a resist film FR1 on the gold film AF, the resist film FR1 is exposed and developed to form an opening OP in the resist film FR1. Then, as shown in FIG. 19, the gold film AF exposed from the opening OP is removed. In order to remove the gold film AF, for example, a milling method can be used, or in addition, a dry etching method or wet etching using an Au etching solution can be used.

  Subsequently, as shown in FIG. 20, the nickel film NF exposed from the opening OP is removed. The nickel film NF can be removed by using, for example, a milling method. Note that the step of removing the gold film AF and the nickel film NF exposed from the opening OP formed in the resist film FR1 can be performed collectively.

  Next, as shown in FIG. 21, the copper film CF exposed from the opening OP is removed by performing wet etching with a copper etchant. By performing wet etching on the copper film CF, a cavity CA is formed in the copper film CF. Since the wet etching is an isotropic etching, the etching progresses not only in the copper film CF immediately below the opening OP but also in the lateral direction, and the cavity CA is formed.

  At this time, the contour shape of the opening OP is as shown in FIG. 10, and the surface area of the base film (copper film CF) exposed from the opening OP increases. In this case, there is an advantage that the circulation of the etching solution is improved and the etching rate is increased. Furthermore, etching proceeds from each of the large exposed areas. For this reason, the cavity CA can be formed with a smaller etching amount. As described above, according to the first embodiment, since the contour shape of the opening OP is the shape shown in FIG. 10 (second feature point), the etching amount for forming the cavity CA is reduced. In addition, the etching rate can be increased.

  The cavity CA includes the opening OP, and the size of the cavity CA is larger than the size of the opening OP. Thus, a beam BM made of the nickel film NF and the gold film AF is formed on the upper part of the cavity CA.

  Thereafter, as shown in FIG. 22, the resist film FR1 is removed by acetone cleaning or ashing using oxygen. In this manner, the connection part CNT having a beam structure can be formed on the semiconductor substrate 1S.

  The difference from the prior art document will be described at the end of the description according to the first embodiment. First, differences from the prior art document 1 (Japanese Patent Laid-Open No. 10-163267) will be described. In Prior Art Document 1, a conductive portion composed of a first plating layer and a second plating layer is formed on a pad of a base material, and a tip portion of a second plating layer constituting the conductive portion protrudes to become a protruding portion. The structure is described. The bump electrode is forcibly inserted into the conductive portion, and the conductive portion and the bump electrode are connected by engaging the protruding portion of the conductive portion with the edge of the bump electrode.

  Here, as shown in FIG. 3, for example, the first feature point in the first embodiment is that the bump electrode BMP1 is inserted into the cavity CA and the beam BM arranged so as to protrude into the cavity CA. The bump electrode BMP1 is configured to be fixed by a restoring force due to deformation. That is, in the first embodiment, the bump electrode BMP1 is fixed by the restoring force of the beam BM, whereas the technique described in the prior art document 1 has the bump electrode edge on the protruding portion of the conductive portion. It is different in that it is fixed by being locked. Due to the difference in the fixing method, the first embodiment can be applied to the shape of the bump to be joined without much limitation, whereas in the prior art document 1, the shape of the bump to be joined is a two-stage shape. Therefore, it is necessary that the edge has a protruding shape. Furthermore, the first embodiment is characterized not only in the cross-sectional structure of the connection part but also in the planar structure. Specifically, as shown in FIG. 10, the second feature point of the first embodiment is that the contour shape of the opening OP borders the shape from the root to the tip of the beam BM protruding into the cavity CA. It has a shape and is in the shape of a large opening from the base to the tip of the beam BM between adjacent beams BM. In particular, the area on the plane of the opening OP is larger than the area on the plane of the beam BM. The third feature point of the first embodiment is that the width of the beam BM is increased from the tip of the beam BM toward the root of the beam BM, as shown in FIG. Such feature points (second feature point and third feature point) in the planar structure of the first embodiment are neither described nor suggested in Prior Art Document 1. Therefore, it is difficult for those skilled in the art to come up with the technical idea in the first embodiment from the prior art document 1.

  Subsequently, in Prior Art Document 2 (Japanese Patent Application Laid-Open No. 2004-12357), the spiral contactor can be deformed corresponding to the shape of the spherical connection terminal when contacting the spherical connection terminal on the insulating substrate. It is configured to make electrical connection with the semiconductor device. At this time, the spiral part and the width of the spiral contact are constant, and the thickness increases as it approaches the root from the tip.

  Here, as shown in FIG. 3, for example, the first feature point in the first embodiment is that the bump electrode BMP1 is inserted into the cavity CA and the beam BM arranged so as to protrude into the cavity CA. The bump electrode BMP1 is configured to be fixed by a restoring force due to deformation. Accordingly, in the first embodiment, the bump electrode BMP1 is fixed by the restoring force of the beam BM, whereas the technique described in the prior art document 2 is fixed by deformation of the spiral contactor. Is different. Furthermore, the prior art document 2 does not describe or suggest the feature point (second feature point) in the planar structure of the first embodiment. Therefore, it is difficult for those skilled in the art to come up with the technical idea in the first embodiment from the prior art document 2.

  Next, Prior Art Document 3 (Japanese Patent Application Laid-Open No. 2004-354179) describes a contact portion in which a slit is formed. Thereby, at the time of connection of a solder ball, a contact part is displaced with this connection. For this reason, the contact area between the solder ball and the contact portion can be increased, and the contact portion and the solder ball can be reliably electrically connected.

  However, unlike the connection part CNT of the first embodiment, the contact part having the slit described in the prior art document 3 has a contour shape of the opening OP from the root of the beam BM protruding into the cavity CA. It does not have a shape that borders the shape reaching the part, and is not greatly opened from the base of the beam BM to the tip between the adjacent beams BM. That is, only the slit is formed in the contact portion of Prior Art Document 3. On the other hand, in the first embodiment, the contour shape of the opening OP has a shape that borders the shape from the root to the tip of the beam BM protruding into the cavity CA, and between the adjacent beams BM. In FIG. 2, the shape of the beam BM is greatly opened from the base to the tip (second feature point), so that the etching amount for forming the cavity CA can be reduced and the etching rate can be reduced. It has the advantage of being fast. In particular, since the area on the plane of the opening OP is larger than the area on the plane of the beam BM, a remarkable effect can be obtained. Further, as in the connection portion CNT of the first embodiment, when the shape is large between the adjacent beams BM from the root of the beam BM to the tip, the connection portion CNT Even after the bump electrode BMP is inserted, a gap is generated at the base of each beam BM. Therefore, when the underfill is injected between the semiconductor chips, the underfill is filled up to the inside of the connection portion CNT through the gap generated at the base of the beam BM. For this reason, the connection strength between the connection part CNT and the bump electrode BMP inserted in the connection part CNT is improved.

  Such feature points (second feature points) in the planar structure of the first embodiment are neither described nor suggested in Prior Art Document 3. Therefore, it is difficult for those skilled in the art to come up with the technical idea in the first embodiment from the prior art document 3. From the above, since the second feature point in the planar structure of the first embodiment is neither described nor suggested in any of the prior art documents 1 to 3, the prior art documents 1 to 3 are combined. However, it is difficult to come up with the technical idea of the first embodiment.

(Embodiment 2)
In the second embodiment, an example will be described in which a through electrode penetrating a semiconductor chip and a connection portion according to the present invention are formed together. For example, an example in which a through electrode and a connection portion of the present invention are formed on a microcomputer chip mounted on a mobile device such as a mobile phone will be described.

  FIG. 23 is a diagram illustrating the connection portion CNT and the through electrode TRE formed in the semiconductor substrate (semiconductor chip) 1S according to the second embodiment. As shown in FIG. 23, the connection part CNT and the through electrode TRE formed in the semiconductor substrate 1S are arranged, for example, in a line.

  FIG. 24 is a cross-sectional view taken along a cross section including the through electrode TRE and the connection portion CNT of FIG. In FIG. 24, a semiconductor element (not shown) such as a MISFET is formed on the lower surface (main surface, element forming surface) of the semiconductor substrate 1S, and an interlayer insulating film is formed on the semiconductor substrate 1S on which the semiconductor element is formed. IL is formed. A multilayer wiring is formed in the interlayer insulating film IL.

  Hereinafter, the configuration of the through electrode TRE will be described. First, a pad PD is formed on the interlayer insulating film IL, and a bump electrode BMP is formed on the pad PD. A hole H1 is formed so as to reach from the back surface (upper surface) of the semiconductor substrate 1S to the inside of the interlayer insulating film. A hole H2 having a smaller diameter than the hole H1 is formed in the pad PD in the interlayer insulating film IL on the bottom surface of the hole H1. It is formed until it reaches. A copper film CF, a nickel film NF, and a gold film AF are sequentially formed on inner walls (side surfaces and bottom surface) of the holes H1 and H2 and a part of the back surface of the semiconductor substrate 1S. Thereby, the copper film CF, the nickel film NF, and the gold film AF are electrically connected to the pad PD.

  Next, the structure of the connection part CNT is demonstrated. The connection part CNT has an opening OP formed so as to penetrate the gold film AF and the nickel film NF formed on the back surface of the semiconductor substrate 1S. Then, the copper film CF exposed from the opening OP is removed, and a cavity CA is formed in the copper film CF. At this time, the size of the cavity CA formed in the copper film CF is larger than the size of the opening OP formed in the nickel film NF and the gold film AF. Therefore, the beam BM made of the nickel film NF and the gold film AF protrudes from the cavity CA. That is, the connection part CNT in the second embodiment includes the copper film CF, the nickel film NF, and the gold film AF, the cavity CA is formed in the copper film CF, and the nickel film NF and the gold film AF are formed. It has a structure in which an opening OP is formed. Since the cavity CA includes the opening OP, and the size of the cavity CA is larger than the size of the opening OP, the cavity CA is formed of the nickel film NF and the gold film AF. A beam BM is formed. The connection part CNT and the through electrode TRE configured as described above are electrically connected.

  The semiconductor device according to the second embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings. First, as shown in FIG. 25, a semiconductor element (not shown) such as a MISFET is formed on the lower surface (main surface, element formation surface) of the semiconductor substrate 1S by using a normal technique. Then, an interlayer insulating film IL is formed on the semiconductor element on which the semiconductor element is formed. Thereafter, a multilayer wiring (not shown) is formed between the interlayer insulating films IL, and a pad PD is formed on the uppermost layer of the interlayer insulating film IL. At this time, the pad PD formed on the uppermost layer of the interlayer insulating film IL is electrically connected to the semiconductor element formed on the semiconductor substrate 1S via the multilayer wiring formed inside the interlayer insulating film IL. It is connected.

  In order to form the through electrode in the semiconductor substrate (semiconductor wafer) 1S, for example, the semiconductor substrate 1S is thinned to about 10 μm to 50 μm, and the difficulty of forming the through electrode is reduced. However, the thinning of the semiconductor substrate 1S may cause a decrease in strength of the semiconductor substrate 1S and a decrease in yield due to warpage of the semiconductor substrate 1S.

  Therefore, in the second embodiment, as shown in FIG. 26, an adhesive BA is applied to the lower surface (main surface, element forming surface) of the semiconductor substrate 1S, and for example, glass, quartz, silicon, or the like is applied by the adhesive BA. The support substrate SB made of is bonded. By sticking the support substrate SB to the semiconductor substrate 1S in this manner, it is possible to suppress a decrease in strength and warpage of the semiconductor substrate 1S after being thinned. The adhesive BA has a function of protecting the semiconductor element formed on the semiconductor substrate 1S.

  Next, as shown in FIG. 27, the back grinding process is performed on the back surface (upper surface) of the semiconductor substrate 1S to reduce the thickness of the semiconductor substrate 1S. As a method of back grinding the back surface of the semiconductor substrate 1S, there is a method of grinding or polishing. Since the flatness after back grinding affects the accuracy of the connecting portion formed on the back surface of the semiconductor substrate 1S, after the back surface of the semiconductor substrate 1S is back ground, dry polishing, etching, or chemical mechanical polishing is performed. It is desirable to perform (CMP: Chemical Mechanical Polishing).

  Subsequently, as shown in FIG. 28, a resist film FR2 is applied on the back surface (upper surface) of the semiconductor substrate 1S. Then, an opening OP2 is formed in the resist film FR by performing exposure / development processing on the applied resist film FR2. As a method of applying the resist film FR2, for example, there is a spinner application method. Note that the opening OP is formed by a method in which a device pattern formed on the element formation surface of the semiconductor substrate 1S is confirmed by infrared spectroscopy, or a method in which a double-sided mask aligner is used.

Next, as shown in FIG. 29, a hole H1 is formed by etching using the resist film FR2 in which the opening OP2 is formed as a mask. Specifically, anisotropic etching is performed by using ICP-RIE (Inductively coupled plasma reactive ion etching) to form the hole H1. Here, for example, SF ₆ and C ₄ H ₈ are used as process gases. Usually, in dry etching of silicon, silicon is etched using a silicon oxide film as a mask. For this reason, in the etching with SF ₆ and C ₄ H ₈ , the etching is stopped at the interlayer insulating film IL mainly composed of the silicon oxide film. The depth of the hole H1 at this time is determined by the film thickness of the semiconductor substrate 1S made of silicon.

Thereafter, the process gas is changed to a mixed gas of SF ₆ and C ₄ H ₈ to C ₃ H ₈ , Ar, and CHF ₄ to process (etch) the interlayer insulating film IL. At this time, no new mask is formed. As a result, the thickness of the interlayer insulating film IL at the bottom of the hole H1 is reduced using the resist film FR2 and the semiconductor substrate 1S as a mask. At this time, the hole H1 reaching the pad PD may be formed by continuing to etch the interlayer insulating film IL, but the interlayer insulating film IL in contact with the pad PD disappears and the strength of the pad PD is reduced. Therefore, in the second embodiment, a method of forming a hole having a smaller diameter than the hole H1 formed in the semiconductor substrate 1S in a range from the lower surface of the interlayer insulating film IL to the pad PD is employed.

  Next, after forming the hole H1, as shown in FIG. 30, the resist film FR2 is removed by an organic solvent or oxygen ashing. Then, as shown in FIG. 31, an insulating film IF1 is formed on the entire back surface of the semiconductor substrate 1S including the inside of the hole H1. The insulating film IF1 is made of, for example, a silicon oxide film, a silicon nitride film, a polyimide resin film, or the like, and can be formed by, for example, a CVD (Chemical Vapor Deposition) method. The insulating film IF1 is formed in the hole H1 so as to cover these surfaces along the inner wall and the bottom surface of the hole H1.

  Subsequently, as shown in FIG. 32, a resist film FR3 is applied to the back surface of the semiconductor substrate 1S including the inside of the hole H1. The resist film FR3 is formed, for example, by spinner application or spray application. When applying with a spinner, in order to fill the hole H1, it is desirable to use a resist film FR3 that can be applied with a film thickness of 5 μm to 30 μm. Furthermore, if bubbles remain in the resist film FR3, exposure in the photolithography process becomes difficult and pattern defects occur. For this reason, it is desirable to remove bubbles by vacuum defoaming. When applying by spray, unlike the case of applying by a spinner, the resist film FR3 is applied along the hole H1. For this reason, the resist shape tends to be biased inside the hole H1. Thereafter, the resist film FR3 applied to the inner surface of the hole H1 is patterned to form an opening OP3 on the bottom surface of the hole H1. At this time, the opening diameter of the opening OP3 is made small so that the resist film FR3 protecting the inner wall of the hole H1 is not patterned.

Thereafter, as shown in FIG. 33, the insulating film IF1 exposed from the opening OP3 and the remainder of the interlayer insulating film IL are all etched to form the hole H2. As a result, the pad PD is exposed at the bottom of the hole H2. For the etching of the insulating film IF1 and the interlayer insulating film IL, for example, a mixed gas mainly containing CHF ₃ or C ₄ H ₈ is used. Then, as shown in FIG. 34, the patterned resist film FR3 is removed by an organic solvent or oxygen ashing.

  Next, as shown in FIG. 35, a copper film CF is formed on the back surface of the semiconductor substrate 1S including the inside of the hole H1 and the hole H2. The copper film CF can be formed, for example, by using a sputtering method. In this copper film CF, the cavity is formed in the lower layer of the beam by wet etching in a process described later to form the connection part CNT, so that the movable range of the beam is sufficiently obtained. Thickness is set. For example, the film thickness of the copper film CF is about 10 μm. In addition to the sputtering method, the copper film CF can be formed by forming a copper film CF having a thickness of 0.3 μm to 1 μm by a sputtering method and then forming a copper film CF having a thickness of 10 μm by an electrolytic plating method.

  Subsequently, as shown in FIG. 36, a nickel film NF is formed on the copper film CF. The nickel film NF can be formed, for example, by using a sputtering method. The nickel film NF is a member constituting a beam to be described later, and the rigidity of the beam, that is, the spring constant of the beam is determined by the thickness of the nickel film NF. When the bump electrode is inserted into the beam, it is necessary to obtain a sufficient bonding force by the restoring force of the beam, and the restoring force of the beam is determined by the thickness of the nickel film NF. Therefore, the thickness of the nickel film NF is, for example, 5 μm.

  Thereafter, as shown in FIG. 37, a gold film AF is formed on the nickel film NF. The gold film AF can be formed, for example, by using a sputtering method. Since the gold film AF is a film provided for reducing the contact resistance between the beam and the bump electrode, the gold film AF may be thin. For example, the film thickness of the gold film AF is about 0.2 μm.

  Next, as shown in FIG. 38, a resist film FR4 is applied on the gold film AF. The resist film FR4 can be formed so as to cover the back surface of the semiconductor substrate 1S, for example, by spinner application or spray application. By performing exposure / development processing on the resist film FR4, an electrode pattern and an opening OP are formed in the resist film FR4. Then, as shown in FIG. 39, the gold film AF exposed from the opening OP is removed. In order to remove the gold film AF, for example, a milling method can be used, or in addition, a dry etching method or wet etching using an Au etching solution can be used. As the Au etching solution, a mixed solution of iodine and ammonium iodide can be considered.

  Subsequently, as shown in FIG. 40, the nickel film NF exposed from the opening OP is removed. The nickel film NF can be removed by using, for example, a milling method. Note that the step of removing the gold film AF and the nickel film NF exposed from the opening OP formed in the resist film FR4 can be performed collectively.

  Next, as shown in FIG. 41, the copper film CF exposed from the opening OP is removed by performing wet etching with a copper etchant. By performing wet etching on the copper film CF, a cavity CA is formed in the copper film CF. Since the wet etching is an isotropic etching, the etching progresses not only in the copper film CF immediately below the opening OP but also in the lateral direction, and the cavity CA is formed.

  At this time, the contour shape of the opening OP is as shown in FIG. 23, and the surface area of the base film (copper film CF) exposed from the opening OP increases. In this case, there is an advantage that the circulation of the etching solution is improved and the etching rate is increased. Furthermore, etching proceeds from each of the large exposed areas. For this reason, the cavity CA can be formed with a smaller etching amount. As described above, according to the first embodiment, since the contour shape of the opening OP has the shape shown in FIG. 23 (second feature point), the etching amount for forming the cavity CA is reduced. In addition, the etching rate can be increased.

  The cavity CA includes the opening OP, and the size of the cavity CA is larger than the size of the opening OP. Thus, a beam BM made of the nickel film NF and the gold film AF is formed on the upper part of the cavity CA.

  Thereafter, as shown in FIG. 42, the resist film FR4 is removed by washing with acetone or ashing using oxygen. Thereby, the semiconductor substrate 1Sni through electrode TRE and the connection part CNT can be formed.

  Next, as shown in FIG. 43, the support substrate SB is peeled off from the semiconductor substrate 1S. For example, in the case of the thermoplastic adhesive BA, the support substrate SB is peeled off from the semiconductor substrate 1S by heating the semiconductor substrate 1S and the support substrate SB.

  Subsequently, the semiconductor substrate 1S is separated into semiconductor chips by blade dicing. Although the semiconductor chip can be separated into individual pieces even when the semiconductor substrate 1Swo is attached to the support substrate SB, the entire support substrate SB is cut. Although handling becomes difficult, the support substrate SB can be reused by peeling the support substrate SB from the semiconductor substrate 1S and dicing.

  Finally, as shown in FIG. 44, the bump electrode BMP is formed on the pad formed on the main surface (element formation surface, lower surface) of the semiconductor substrate 1S. As a method for forming the bump electrode BMP, for example, there is a stud bump method. Other formation methods include a solder paste bump method, a plating method, or a vapor deposition method. As described above, a semiconductor device in which the through electrode TRE and the connection part CNT are formed can be manufactured.

  Next, a connection example in which a plurality of semiconductor chips on which the through electrode TRE and the connection part CNT are formed is electrically connected and three-dimensionally stacked will be described.

  FIG. 45 is a diagram illustrating a state before the semiconductor chip CHP1 formed of, for example, a microcomputer chip and the semiconductor chip CHP2 in which the SDRAM is formed are stacked. In FIG. 45, a semiconductor chip CHP1 is mounted on a wiring board WB, and a semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via an interposer IP that performs rewiring. The semiconductor chip CHP1 has a rectangular shape (square shape), and a through electrode and a connection portion CNT (CHP1) are formed along the peripheral portion (side) of the semiconductor chip CHP1. Similarly, the interposer IP has a rectangular shape (rectangular shape), and through electrodes (bump electrodes BMP (IP)) and connection portions CNT (IP) are formed along the peripheral portion (side) of the interposer IP. . The semiconductor chip CHP2 also has a rectangular shape (square shape), and a through electrode (bump electrode BMP (CHP2)) and a connection portion are formed along the peripheral portion (side) of the semiconductor chip CHP2. For example, a plurality of through-electrodes (bump electrode BMP (IP), bump electrode BMP (CHP2)) formed on the semiconductor chip CHP1, the interposer IP, and the semiconductor chip CHP2 and the connection portion CNT (CHP1) or the connection portion CNT (IP) Are arranged in a peripheral arrangement, but these arrangements are not limited to the peripheral arrangement. For example, the semiconductor chip CHP1, the interposer IP, and the semiconductor chip CHP2 configured as described above insert the bump electrode BMP (IP) formed in the interposer IP into the connection portion CNT (CHP1) formed in the semiconductor chip CHP1, Further, by inserting the bump electrode BMP (CHP2) formed on the semiconductor chip CHP2 into the connection portion CNT (IP) formed on the interposer IP, the semiconductor chip CHP1, the interposer IP, and the semiconductor chip CHP2 are electrically connected. However, it can be laminated three-dimensionally.

  FIG. 46 is a cross-sectional view showing a stacked structure in which the semiconductor chip CHP1 is mounted on the wiring board WB, and the semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via the interposer IP. As shown in FIG. 46, the bump electrode BMP (CHP1) of the semiconductor chip CHP1 is connected to the terminal TE formed on the wiring board WB. A bump electrode BMP (IP) formed in the interposer IP is inserted into the connection portion CNT (CHP1) formed in the semiconductor chip CHP1. Further, the bump electrode BMP (CHP2) of the semiconductor chip CHP2 is inserted into the connection portion CNT (IP) formed in the interposer IP. Thereby, the wiring board WB, the semiconductor chip CHP1, the interposer IP, and the semiconductor chip CHP2 can be three-dimensionally stacked while being electrically connected.

  In the second embodiment, the bump electrode is inserted into the connecting portion, and the bump electrode is fixed by a restoring force due to deformation of the beam arranged so as to protrude into the hollow portion constituting the connecting portion. . For this reason, in this Embodiment 2, a bump electrode can be mechanically fixed to a connection part, without using solder. Therefore, since solder is not used to connect the bump electrode and the connection portion, even if the connection portion and the bump electrode have a high density or a narrow pitch, a short circuit between adjacent connection portions or between adjacent bump electrodes is not possible. Can be suppressed. In other words, in the second embodiment, since the molten solder is not used for the connection between the bump electrode and the connection portion, it is possible to suppress a short circuit failure due to a solder bridge, and to improve the reliability of the semiconductor device. it can.

  At this time, in the second embodiment, the beam structure is a so-called equal strength beam structure (third feature point), whereby the strength of the beam can be ensured and the reliability of the connecting portion is improved. be able to.

  Further, underfill UF is injected between the wiring substrate WB and the semiconductor chip CHP1, between the semiconductor chip CHP1 and the interposer IP, and between the interposer IP and the semiconductor chip CHP2. In the second embodiment, the contour shape of the opening that constitutes the connecting portion has a shape that borders the shape from the root of the beam protruding into the cavity portion to the tip portion, and between the adjacent beams, the beam (Second feature point), a gap is generated at the base of each beam even after the bump electrode is inserted into the connection portion. Therefore, when the underfill UF is injected, the underfill UF is filled up to the inside of the connecting portion through the gap generated at the base of the beam. For this reason, the connection intensity | strength of a connection part and the bump electrode inserted in this connection part can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1S Semiconductor substrate 2S Semiconductor substrate AF Gold film BM Beam BM2 Beam BMP Bump electrode BMP1 Bump electrode BMP2 Bump electrode BMP3 Bump electrode BMP (IP) Bump electrode BMP (CHP1) Bump electrode BMP (CHP2) Bump electrode CA Cavity part CF Copper film CHP Semiconductor chip CHP2 Semiconductor chip CNT connection part CNT2 connection part CNT (CHP1) connection part CNT (IP) connection part CON Conductor film FR1 Resist film FR2 Resist film FR3 Resist film FR4 Resist film H1 hole H2 hole IF1 Insulating film IL Interlayer insulating film IL2 Interlayer insulating film IP interposer NF Nickel film OP opening OPT opening OP2 opening OP3 opening PD pad SL slit TE terminal TRE through electrode UF underfill WB wiring board

Claims (27)

(A) a first substrate;
(B) a first conductor film formed on the first substrate and patterned;
(C) a cavity formed in the first conductor film;
(D) a second conductor film formed on the first conductor film and patterned so as to partially protrude into the cavity;
(E) an opening formed in the second conductor film,
A semiconductor in which the opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film that protrudes into the cavity functions as a beam A device,
The contour shape of the opening has a shape that borders the shape from the root of the beam protruding to the cavity to the tip, and the area on the plane of the opening is the area on the plane of the beam A semiconductor device characterized by being larger than the above. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the opening functions as an etching hole when the cavity is formed. The semiconductor device according to claim 1,
The width of the beam increases from the tip of the beam toward the base of the beam. The semiconductor device according to claim 1,
The semiconductor device, wherein the patterned first conductor film and the second conductor film patterned so that a part of the first conductor film protrudes into the cavity portion constitute a wiring. The semiconductor device according to claim 4,
The semiconductor device, wherein the first conductor film is formed of a copper film, and the second conductor film is formed of a nickel film. The semiconductor device according to claim 4,
A semiconductor device, wherein a third conductor film is formed on the second conductor film. The semiconductor device according to claim 6,
The semiconductor device, wherein the third conductor film is formed of a gold film. The semiconductor device according to claim 1,
The semiconductor device, wherein the first substrate is a wiring substrate connected to a semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device, wherein the first substrate is a semiconductor substrate. The semiconductor device according to claim 1,
Furthermore, it has the 2nd board | substrate with which the bump electrode was formed,
By inserting the bump electrode formed on the second substrate into the cavity formed on the first substrate through the beam formed on the first substrate, Connecting the beam and the bump electrode with a restoring force, electrically connecting the first substrate and the second substrate, and laminating the first substrate and the second substrate; Semiconductor device. The semiconductor device according to claim 10,
A semiconductor device, wherein the hollow portion is filled with underfill. The semiconductor device according to claim 10,
There are a plurality of the beams protruding into the cavity,
The distance between the tip of one of the beams and the tip of the other one of the beams is a,
The diameter of the tip of the bump electrode is b,
The length of the beam protruding into the cavity is c,
When the depth of the cavity is d,
A semiconductor device characterized by satisfying condition a <b and condition c <d. (A) a first semiconductor substrate;
(B) a hole reaching the element forming surface opposite to the back surface from the back surface of the first semiconductor substrate;
(C) a first conductor film formed on the back surface of the first semiconductor substrate including the inside of the hole and patterned;
(D) a cavity formed in the first conductor film formed on the back surface of the first semiconductor substrate;
(E) a second conductor film formed on the first conductor film and patterned so as to partially protrude into the cavity,
(F) an opening formed in the second conductor film,
A semiconductor in which the opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film that protrudes into the cavity functions as a beam A device,
The contour shape of the opening has a shape that borders the shape from the root of the beam protruding to the cavity to the tip, and the area on the plane of the opening is the area on the plane of the beam A semiconductor device characterized by being larger than the above. A semiconductor device according to claim 13,
The semiconductor device according to claim 1, wherein the opening functions as an etching hole when the cavity is formed. A semiconductor device according to claim 13,
The width of the beam increases from the tip of the beam toward the base of the beam. A semiconductor device according to claim 13,
Furthermore, it has the 2nd semiconductor substrate in which the bump electrode was formed,
By inserting the bump electrode formed in the second semiconductor substrate into the cavity formed in the first semiconductor substrate through the beam formed in the first semiconductor substrate, The beam and the bump electrode are connected by the restoring force of the beam, the first semiconductor substrate and the second semiconductor substrate are electrically connected, and the first semiconductor substrate and the second semiconductor substrate are A semiconductor device characterized by stacking layers. The semiconductor device according to claim 16, wherein
A semiconductor device, wherein the hollow portion is filled with underfill. (A) forming a first conductor film on the first surface of the first substrate;
(B) forming a second conductor film on the first conductor film;
(C) forming an opening that penetrates the second conductor film;
(D) forming a cavity in the first conductor film by wet etching the first conductor film using the opening as an etching hole,
A semiconductor device in which the opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film protruding into the cavity is a beam A manufacturing method of
The contour shape of the opening has a shape that borders the shape from the root of the beam protruding to the cavity to the tip, and the area on the plane of the opening is the area on the plane of the beam A method for manufacturing a semiconductor device, wherein A method of manufacturing a semiconductor device according to claim 18,
After the step (b) and before the step (c),
(E) forming a third conductor film on the second conductor film;
(F) forming the opening in the third conductor film,
In the step (c), the opening that penetrates the second conductor film is formed by removing the second conductor film exposed from the opening formed in the third conductor film. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 19,
Forming the first conductor film formed in the step (a) from a copper film;
Forming the second conductor film formed in the step (b) from a nickel film;
A method of manufacturing a semiconductor device, wherein the third conductor film formed in the step (e) is formed of a gold film. 19. The method of manufacturing a semiconductor device according to claim 18, further comprising:
(G) preparing a second substrate on which bump electrodes are formed;
(H) After the step (d), the bump electrode formed on the second substrate is transferred to the cavity formed in the first substrate via the beam formed on the first substrate. The first substrate and the second substrate are electrically connected to each other by the restoring force of the beam, and the first substrate and the second substrate are electrically connected. A method of manufacturing a semiconductor device, comprising: stacking two substrates. A method of manufacturing a semiconductor device according to claim 21,
Furthermore, after the step (h),
(I) A method of manufacturing a semiconductor device, comprising a step of filling the cavity with an underfill. (A) forming a hole reaching the electrode formed on the element forming surface opposite to the back surface from the back surface of the first semiconductor substrate;
(B) forming a first conductor film on the back surface of the first semiconductor substrate including the inside of the hole;
(C) forming a second conductor film on the first conductor film;
(D) forming an opening in the second conductor film formed on the back surface of the first semiconductor substrate by patterning the second conductor film;
(E) forming a cavity in the first conductor film by wet etching the first conductor film using the opening as an etching hole,
A semiconductor device in which the opening is included in the cavity in a plane, the opening and the cavity are integrated, and a portion of the second conductor film protruding into the cavity is a beam A manufacturing method of
The contour shape of the opening has a shape that borders the shape from the root of the beam protruding to the cavity to the tip, and the area on the plane of the opening is the area on the plane of the beam A method for manufacturing a semiconductor device, wherein A method of manufacturing a semiconductor device according to claim 23, wherein
After the step (c) and before the step (d),
(F) forming a third conductor film on the second conductor film;
(G) forming the opening in the third conductor film,
The step (d) forms the opening that penetrates the second conductor film by removing the second conductor film exposed from the opening formed in the third conductor film. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 24, wherein
Forming the first conductor film formed in the step (b) from a copper film;
Forming the second conductor film formed in the step (c) from a nickel film;
A method of manufacturing a semiconductor device, wherein the third conductor film formed in the step (f) is formed of a gold film. 24. A method of manufacturing a semiconductor device according to claim 23, further comprising:
(H) preparing a second semiconductor substrate on which bump electrodes are formed;
(I) After the step (e), the bump electrode formed on the second semiconductor substrate is formed on the first semiconductor substrate via the beam formed on the first semiconductor substrate. The beam and the bump electrode are connected by the restoring force of the beam, the first semiconductor substrate and the second semiconductor substrate are electrically connected, and the first semiconductor substrate and the second semiconductor substrate are electrically connected. 1. A method for manufacturing a semiconductor device, comprising: stacking a semiconductor substrate and the second semiconductor substrate. 27. A method of manufacturing a semiconductor device according to claim 26, comprising:
Furthermore, after the step (i),
(J) A method of manufacturing a semiconductor device comprising a step of filling the cavity with an underfill.

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