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JP2011014644A - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof Download PDF

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JP2011014644A
JP2011014644A JP2009155966A JP2009155966A JP2011014644A JP 2011014644 A JP2011014644 A JP 2011014644A JP 2009155966 A JP2009155966 A JP 2009155966A JP 2009155966 A JP2009155966 A JP 2009155966A JP 2011014644 A JP2011014644 A JP 2011014644A
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strip
element connection
connection pad
wiring conductor
wiring board
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Shigeji Kimura
茂治 木村
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
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Abstract

【課題】 半導体素子の電極端子と半田を介して接続するための素子接続パッドの幅を十分に確保し、半導体素子の電極端子と素子接続パッドとを半田を介して強固に接続することが可能な配線基板を提供することにある。
【解決手段】 絶縁基体１上に半導体素子接続用の帯状配線導体２が複数並んで形成されているとともに、帯状配線導体２の一部に半導体素子Ｓの電極端子がフリップチップ接続される素子接続パッド３が形成されており、かつ絶縁基体１上および帯状配線導体２上に、素子接続パッド３を露出させる開口部４を有するソルダーレジスト層５が被着されている配線基板１０であって、帯状配線導体２は、ソルダーレジスト層７が被着する表面が粗化処理されているとともに素子接続パッド３の露出面が前記粗化処理された表面よりも外側に膨出した平滑面である。
【選択図】図３PROBLEM TO BE SOLVED: To secure a sufficient width of an element connection pad for connecting to an electrode terminal of a semiconductor element via solder and to firmly connect the electrode terminal of the semiconductor element and the element connection pad via solder. And providing a simple wiring board.
A plurality of strip-like wiring conductors 2 for connecting semiconductor elements are formed side by side on an insulating substrate 1, and an electrode connection in which an electrode terminal of a semiconductor element S is flip-chip connected to a part of the strip-like wiring conductor 2 is provided. A wiring substrate 10 in which a pad 3 is formed and a solder resist layer 5 having an opening 4 exposing the element connection pad 3 is deposited on the insulating substrate 1 and the strip-shaped wiring conductor 2. The band-shaped wiring conductor 2 is a smooth surface in which the surface to which the solder resist layer 7 is applied is roughened and the exposed surface of the element connection pad 3 bulges outward from the roughened surface.
[Selection] Figure 3

Description

本発明は配線基板およびその製造方法に関し、より詳細には、例えば半導体素子をフリップチップ接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting, for example, a semiconductor element by flip chip connection and a manufacturing method thereof.

従来から、半導体素子として、多数の電極端子を、その一方の主面の外周に沿って配設したペリフェラル型や、一方の主面の全域に電極端子を配設したエリア型の半導体素子がある。
このような半導体素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法がある。フリップチップ接続とは、配線基板上に設けた半導体素子接続用の配線導体の一部を半導体素子の電極端子の配置に対応した並びに露出させ、この半導体素子接続用の配線導体の露出部と前記半導体素子の電極端子とを対向させ、これらを半田等の導電バンプを介して電気的に接続する方法である。 Conventionally, as a semiconductor element, there are a peripheral type semiconductor element in which a large number of electrode terminals are arranged along the outer periphery of one main surface, and an area type semiconductor element in which electrode terminals are provided over the entire area of one main surface. .
As a method of mounting such a semiconductor element on a wiring board, there is a method of connecting by flip chip connection. The flip-chip connection means that a part of the wiring conductor for connecting the semiconductor element provided on the wiring substrate is exposed corresponding to the arrangement of the electrode terminals of the semiconductor element, and the exposed portion of the wiring conductor for connecting the semiconductor element and the above-mentioned In this method, the electrode terminals of the semiconductor element are opposed to each other, and these are electrically connected via conductive bumps such as solder.

図８は、ペリフェラル型の半導体素子をフリップチップ接続により搭載した従来の配線基板を示す断面図であり、図９は図８に示す配線基板の平面図である。
図８、図９に示すように、従来の配線基板１００は、絶縁基体１０１の上面に半導体素子接続用の帯状配線導体１０２が複数並んで形成されているとともに、帯状配線導体１０２の一部に半導体素子
Ｓの電極端子がフリップチップ接続される素子接続パッド１０３が形成されている。また、絶縁基体１０１の上および帯状配線導体１０２の上には、素子接続パッド１０３を露出させる開口部１０４を有するソルダーレジスト層１０５が被着されている。 FIG. 8 is a cross-sectional view showing a conventional wiring board on which peripheral type semiconductor elements are mounted by flip-chip connection, and FIG. 9 is a plan view of the wiring board shown in FIG.
As shown in FIGS. 8 and 9, the conventional wiring substrate 100 has a plurality of strip-like wiring conductors 102 for connecting semiconductor elements formed on the upper surface of an insulating base 101, and a part of the strip-like wiring conductor 102. An element connection pad 103 to which the electrode terminal of the semiconductor element S is flip-chip connected is formed. A solder resist layer 105 having an opening 104 for exposing the element connection pad 103 is deposited on the insulating substrate 101 and the strip-shaped wiring conductor 102.

そして、この配線基板１００においては、素子接続パッド１０３に半田１０６をめっきや溶着により予め被着させておくとともに、半導体素子Ｓの電極端子と半田１０６とを当接させた状態で加熱し、半田１０６を溶融させ、半導体素子Ｓの電極端子と素子接続パッド１０３とを半田１０６を介して電気的に接続することによって半導体素子Ｓが配線基板１００上に実装される。   In this wiring board 100, the solder 106 is preliminarily deposited on the element connection pad 103 by plating or welding, and the electrode terminal of the semiconductor element S and the solder 106 are heated in contact with each other. The semiconductor element S is mounted on the wiring substrate 100 by melting the electrode 106 and electrically connecting the electrode terminal of the semiconductor element S and the element connection pad 103 via the solder 106.

ところで、この配線基板１００においては、ソルダーレジスト層１０５と帯状配線導体１０２との密着度を向上させるため、帯状配線導体１０２のソルダーレジスト層１０５で被覆される面が粗化面となっている。また、素子接続パッド１０３の露出面は、半田１０６との接合を良好とするために粗化面が除去されて平滑な面になっている。このような粗化面および平滑面は、通常、図１０（ａ），（ｂ）に示すように、絶縁基体１０１の上面に素子接続パッド１０３を有する帯状配線導体１０２を形成後、図１１（ａ），（ｂ）に示すように、帯状配線導体１０２の側面および上面の全面を粗化液で化学的に粗化し、次に図１２（ａ），（ｂ）に示すように、素子接続パッド１０３を露出させる開口部１０４を有するソルダーレジスト層１０５を形成した後、図１３（ａ），（ｂ）に示すように、開口部１０４から露出する帯状配線導体１０２の表面をエッチングして粗化面を除去して平滑にすることにより形成される。   By the way, in this wiring board 100, in order to improve the adhesion between the solder resist layer 105 and the strip-shaped wiring conductor 102, the surface covered with the solder resist layer 105 of the strip-shaped wiring conductor 102 is a roughened surface. Further, the exposed surface of the element connection pad 103 is a smooth surface from which the roughened surface is removed in order to improve the bonding with the solder 106. Such a roughened surface and a smooth surface are usually formed as shown in FIGS. 11A and 11B after forming the strip-like wiring conductor 102 having the element connection pads 103 on the upper surface of the insulating base 101 as shown in FIGS. As shown in a) and (b), the entire side surface and upper surface of the strip-shaped wiring conductor 102 are chemically roughened with a roughening solution, and then, as shown in FIGS. After forming the solder resist layer 105 having the opening 104 that exposes the pad 103, as shown in FIGS. 13A and 13B, the surface of the strip-shaped wiring conductor 102 exposed from the opening 104 is etched and roughened. It is formed by removing the chemical surface and smoothing it.

ところが近年、半導体素子は、その高集積度化が急激に進み、半導体素子における電極端子のピッチは例えば５０μｍ以下と狭ピッチになってきており、これに伴い、素子接続パッド１０３の幅が狭くなってくる。この状況の中で、絶縁基体１０１の上面に帯状配線導体１０２を形成後、帯状配線導体１０２の側面および上面の全面を化学的に粗化し、次に素子接続パッド１０３を露出させる開口部１０４を有するソルダーレジスト層１０５を形成した後、開口部１０４から露出する帯状配線導体１０２の表面をエッチングして粗化面を除去して平滑にする工程を行なうと、素子接続パッド１０３は、粗化の際および粗化面を除去して平滑にするエッチングの際にその露出表面が１．５〜２μｍ程度の厚みだけ除去される。その結果、素子接続パッド１０３の幅が狭くなりすぎて半導体素子Ｓの電極端子と素子接続パッド１０３とを半田１０６を介して強固に接続するのに必要な幅が十分に確保することができないという問題点がでてきた。   However, in recent years, the integration density of semiconductor elements has rapidly increased, and the pitch of electrode terminals in the semiconductor elements has become narrow, for example, 50 μm or less, and accordingly, the width of the element connection pads 103 has become narrower. Come. In this situation, after forming the strip-shaped wiring conductor 102 on the upper surface of the insulating base 101, the opening 104 that exposes the element connection pad 103 is then formed by chemically roughening the entire side surface and upper surface of the strip-shaped wiring conductor 102. After forming the solder resist layer 105, the element connection pad 103 is subjected to a roughening process by etching the surface of the strip-shaped wiring conductor 102 exposed from the opening 104 to remove the roughened surface and smoothing it. The exposed surface is removed by a thickness of about 1.5 to 2 [mu] m during etching for smoothing by removing the roughened surface. As a result, the width of the element connection pad 103 becomes too narrow, and a sufficient width for firmly connecting the electrode terminal of the semiconductor element S and the element connection pad 103 via the solder 106 cannot be secured. The problem came out.

特開２００７−３１７８９９号公報JP 2007-317899 A

本発明の配線基板の製造方法は、かかる従来の問題点に鑑み案出されたものであり、その課題は、半導体素子の電極端子のピッチが狭くなったとしても、半導体素子の電極端子と半田を介して接続するための素子接続パッドの幅を十分に確保することができ、それにより半導体素子の電極端子と素子接続パッドとを半田を介して強固に接続することができる配線基板を提供することにある。   The method for manufacturing a wiring board of the present invention has been devised in view of such conventional problems, and the problem is that even if the pitch of the electrode terminals of the semiconductor element is reduced, the electrode terminals of the semiconductor element and the solder Provided is a wiring board capable of ensuring a sufficient width of an element connection pad for connection via a semiconductor device, and thereby firmly connecting an electrode terminal of the semiconductor element and the element connection pad via solder. There is.

本発明の配線基板は、絶縁基体上に半導体素子接続用の帯状配線導体が複数並んで形成されているとともに、帯状配線導体の一部に半導体素子の電極端子がフリップチップ接続される素子接続パッドが形成されており、かつ絶縁基体上および帯状配線導体上に、素子接続パッドを露出させる開口部を有するソルダーレジスト層が被着されている配線基板であって、帯状配線導体は、ソルダーレジスト層が被着する表面が粗化処理されているとともに素子接続パッドの露出面が前記粗化処理された表面よりも外側に膨出した平滑面であることを特徴とするものである。   The wiring board according to the present invention has a plurality of strip-shaped wiring conductors for connecting semiconductor elements formed on an insulating substrate, and an element connection pad in which electrode terminals of the semiconductor elements are flip-chip connected to a part of the strip-shaped wiring conductor And a solder resist layer having an opening for exposing the element connection pad is deposited on the insulating substrate and the strip-shaped wiring conductor, wherein the strip-shaped wiring conductor is a solder resist layer. The surface to be deposited is roughened and the exposed surface of the element connection pad is a smooth surface bulging outward from the roughened surface.

また、本発明の配線基板の製造方法は、絶縁基体上に半導体素子の電極端子がフリップチップ接続される素子接続パッドを有する帯状配線導体を複数並べて形成する工程と、帯状配線導体における素子接続パッドをエッチングレジストで選択的に覆うとともに該エッチングレジストから露出する帯状配線導体の表面を粗化処理した後、エッチングレジストを除去する工程と、絶縁基体上および帯状配線導体上に、素子接続パッドを露出させる開口部を有するソルダーレジスト層を被着させる工程とを備えることを特徴とするものである。   In addition, the method for manufacturing a wiring board according to the present invention includes a step of forming a plurality of strip-shaped wiring conductors having element connection pads on which an electrode terminal of a semiconductor element is flip-chip connected on an insulating substrate, and an element connection pad in the strip-shaped wiring conductor. Are selectively covered with an etching resist and the surface of the strip wiring conductor exposed from the etching resist is roughened, and then the etching resist is removed, and the element connection pads are exposed on the insulating substrate and the strip wiring conductor. And a step of depositing a solder resist layer having an opening to be formed.

本発明の配線基板によれば、素子接続パッドの表面は、該素子接続パッドが形成された帯状配線導体における粗化処理された表面よりも外側に膨出する平滑面となっていることから、その幅を十分に確保することができる。したがって、半導体素子の電極端子と半田を介して接続するための素子接続パッドの幅を十分に確保し、半導体素子の電極端子と素子接続パッドとを半田を介して強固に接続することができる。
また、本発明の配線基板の製造方法によれば、絶縁基体上に半導体素子の電極端子がフリップチップ接続される素子接続パッドを有する帯状配線導体を複数並べて形成し、次に、帯状配線導体における素子接続パッドをエッチングレジストで選択的に覆うとともに該エッチングレジストから露出する帯状配線導体の表面を粗化処理した後、エッチングレジストを除去し、次に絶縁基体上および帯状配線導体上に、素子接続パッドを露出させる開口部を有するソルダーレジスト層を被着させることから、素子接続パッドは粗化によりその幅が減少することはなく、しかも素子接続パッドの露出面は粗化されていないのでエッチングにより平滑にする必要もないので、素子接続パッドの幅が粗化やエッチングにより狭くなることはない。したがって、半導体素子の電極端子と半田を介して接続するための素子接続パッドの幅を十分に確保し、半導体素子の電極端子と素子接続パッドとを半田を介して強固に接続することが可能な配線基板を提供することができる。 According to the wiring board of the present invention, the surface of the element connection pad is a smooth surface that bulges outward from the roughened surface of the strip-shaped wiring conductor in which the element connection pad is formed. The width can be secured sufficiently. Therefore, it is possible to secure a sufficient width of the element connection pad for connecting to the electrode terminal of the semiconductor element via the solder, and to firmly connect the electrode terminal of the semiconductor element and the element connection pad via the solder.
Further, according to the method for manufacturing a wiring board of the present invention, a plurality of strip-like wiring conductors having element connection pads to which electrode terminals of semiconductor elements are flip-chip connected are formed side by side on an insulating substrate, The element connection pads are selectively covered with an etching resist and the surface of the strip-shaped wiring conductor exposed from the etching resist is roughened, and then the etching resist is removed, and then the element connection is formed on the insulating substrate and the strip-shaped wiring conductor. Since the solder resist layer having an opening that exposes the pad is deposited, the width of the element connection pad is not reduced by roughening, and the exposed surface of the element connection pad is not roughened. Since it is not necessary to make it smooth, the width of the element connection pad is not reduced by roughening or etching. Therefore, it is possible to secure a sufficient width of the element connection pad for connecting to the electrode terminal of the semiconductor element via the solder, and to firmly connect the electrode terminal of the semiconductor element and the element connection pad via the solder. A wiring board can be provided.

図１は、本発明の配線基板の実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板の概略平面図である。FIG. 2 is a schematic plan view of the wiring board shown in FIG. 図３（ａ）は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図であり、図３（ｂ）はその概略平面図である。FIG. 3A is a schematic cross-sectional view for explaining an example of an embodiment of the method for manufacturing a wiring board of the present invention, and FIG. 3B is a schematic plan view thereof. 図４（ａ），（ｂ）は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図とその概略平面図である。4A and 4B are a schematic cross-sectional view and a schematic plan view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図５（ａ），（ｂ）は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図とその概略平面図である。5A and 5B are a schematic cross-sectional view and a schematic plan view for explaining an example of an embodiment of the method for manufacturing a wiring board according to the present invention. 図６（ａ），（ｂ）は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図とその概略平面図である。6A and 6B are a schematic cross-sectional view and a schematic plan view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図７（ａ），（ｂ）は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図とその概略平面図である。7A and 7B are a schematic cross-sectional view and a schematic plan view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図８は、従来の配線基板を示す概略断面図である。FIG. 8 is a schematic cross-sectional view showing a conventional wiring board. 図９は、図８に示す配線基板の概略平面図である。FIG. 9 is a schematic plan view of the wiring board shown in FIG. 図１０（ａ），（ｂ）は、従来の配線基板の製造方法を説明するための概略断面図とその概略平面図である。10A and 10B are a schematic cross-sectional view and a schematic plan view for explaining a conventional method of manufacturing a wiring board. 図１１（ａ），（ｂ）は、従来の配線基板の製造方法を説明するための概略断面図とその概略平面図である。11A and 11B are a schematic cross-sectional view and a schematic plan view for explaining a conventional method of manufacturing a wiring board. 図１２（ａ），（ｂ）は、従来の配線基板の製造方法を説明するための概略断面図とその概略平面図である。12A and 12B are a schematic cross-sectional view and a schematic plan view for explaining a conventional method of manufacturing a wiring board. 図１３（ａ），（ｂ）は、従来の配線基板の製造方法を説明するための概略断面図とその概略平面図である。FIGS. 13A and 13B are a schematic cross-sectional view and a schematic plan view for explaining a conventional method of manufacturing a wiring board.

以下、本発明にかかる配線基板およびその製造方法について図面を参照して詳細に説明する。図１、図２に示すように、本例の配線基板１０は、絶縁基体１の上面に半導体素子接続用の帯状配線導体２が複数並んで形成されているとともに、帯状配線導体２の一部に半導体素子Ｓの電極端子がフリップチップ接続される素子接続パッド３が形成されている。また、絶縁基体１の上および帯状配線導体２の上には、素子接続パッド３を露出させる開口部４を有するソルダーレジスト層５が被着されている。   Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. As shown in FIGS. 1 and 2, the wiring substrate 10 of this example has a plurality of strip-like wiring conductors 2 for connecting semiconductor elements formed side by side on the upper surface of an insulating substrate 1 and a part of the strip-like wiring conductor 2. An element connection pad 3 to which the electrode terminal of the semiconductor element S is flip-chip connected is formed. Further, a solder resist layer 5 having an opening 4 for exposing the element connection pad 3 is deposited on the insulating substrate 1 and the strip-shaped wiring conductor 2.

そして、この配線基板１０においては、素子接続パッド３に半田６をめっきや溶着により予め被着させておくとともに、半導体素子Ｓの電極端子と半田６とを当接させた状態で加熱し、半田６を溶融させ、半導体素子Ｓの電極端子と素子接続パッド３とを半田６を介して電気的に接続することによって半導体素子Ｓが配線基板１０上に実装される。   In this wiring board 10, solder 6 is previously applied to the element connection pads 3 by plating or welding, and the electrode terminals of the semiconductor element S and the solder 6 are heated in contact with the solder, The semiconductor element S is mounted on the wiring substrate 10 by melting the electrode 6 and electrically connecting the electrode terminals of the semiconductor element S and the element connection pads 3 via the solder 6.

この配線基板１０においては、図３（ａ），（ｂ）に示すように、ソルダーレジスト層５と帯状配線導体２との密着度を向上させるため、帯状配線導体２のソルダーレジスト層５で被覆される面が図中、ギザギザの線で示すように、粗化液で粗化処理された粗化面となっている。また、素子接続パッド３の露出面は、半田６との接合を良好なものとするために粗化処理されておらず、粗化面よりも外側に膨出した平滑面となっている。このように、素子接続パッド３の表面は、素子接続パッド３が形成された帯状配線導体２における粗化処理された表面よりも外側に膨出する平滑面となっていることから、その幅を十分に確保することができる。したがって、半導体素子Ｓの電極端子と半田６を介して接続するための素子接続パッド３の幅が十分に確保され、半導体素子Ｓの電極端子と素子接続パッド３とを半田６を介して強固に接続することができる。   In this wiring board 10, as shown in FIGS. 3A and 3B, in order to improve the adhesion between the solder resist layer 5 and the strip-shaped wiring conductor 2, the strip-shaped wiring conductor 2 is covered with the solder resist layer 5. The surface to be processed is a roughened surface that has been roughened with a roughening solution, as indicated by a jagged line in the figure. Further, the exposed surface of the element connection pad 3 is not roughened in order to improve the bonding with the solder 6, and is a smooth surface that bulges outward from the roughened surface. Thus, the surface of the element connection pad 3 is a smooth surface that bulges outward from the roughened surface of the strip-shaped wiring conductor 2 on which the element connection pad 3 is formed. It can be secured sufficiently. Therefore, the width of the element connection pad 3 for connecting to the electrode terminal of the semiconductor element S via the solder 6 is sufficiently secured, and the electrode terminal of the semiconductor element S and the element connection pad 3 are firmly connected via the solder 6. Can be connected.

このように、帯状配線導体２のソルダーレジスト層５で被覆される面を粗化面とするとともに、素子接続パッド３の露出面を前記粗化面よりも外側に膨出した平滑面とするには、まず、図４（ａ），（ｂ）に示すように、絶縁基体１の上面に帯状配線導体２を形成する。絶縁基体１は、例えばガラス繊維基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて熱硬化させた絶縁材料やエポキシ樹脂の熱硬化性樹脂に無機絶縁性フィラーを分散させた樹脂フィルムを熱硬化させた絶縁材料を単独で、或いは複数積層して形成することができる。帯状配線導体２は、例えば銅箔や銅めっき層から成り、周知のセミアディティブ法を採用することにより絶縁基体１の上面に複数を並べて形成することができる。このとき、帯状配線導体２の側面および上面は平滑な面となっている。   Thus, the surface covered with the solder resist layer 5 of the strip-shaped wiring conductor 2 is a roughened surface, and the exposed surface of the element connection pad 3 is a smooth surface bulging outward from the roughened surface. First, as shown in FIGS. 4A and 4B, a strip-shaped wiring conductor 2 is formed on the upper surface of the insulating base 1. The insulating substrate 1 is made of, for example, an inorganic insulating filler dispersed in an insulating material obtained by impregnating a glass fiber base material with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, or a thermosetting resin such as an epoxy resin. The insulating material obtained by thermosetting the resin film can be formed singly or in a plurality of layers. The strip-shaped wiring conductor 2 is made of, for example, a copper foil or a copper plating layer, and a plurality of strip-shaped wiring conductors 2 can be formed side by side on the upper surface of the insulating substrate 1 by employing a known semi-additive method. At this time, the side surface and the upper surface of the strip-shaped wiring conductor 2 are smooth surfaces.

次に、図５（ａ），（ｂ）に示すように、絶縁基体１の上面における素子接続パッド３およびその近傍を覆うようにしてエッチングレジスト７を被着させる。エッチングレジスト７は、例えば光感光性アルカリ現像型ドライフィルムレジストを使用し、素子接続パッド３およびその近傍を覆うようにしてレジストが帯状に残るように感光させ、現像処理を行なうことにより形成される。   Next, as shown in FIGS. 5A and 5B, an etching resist 7 is deposited so as to cover the element connection pads 3 on the upper surface of the insulating substrate 1 and the vicinity thereof. The etching resist 7 is formed, for example, by using a photosensitive alkali developing dry film resist, exposing the element connection pad 3 and its vicinity so that the resist remains in a strip shape, and performing development processing. .

次に、図６（ａ），（ｂ）に示すように、エッチングレジスト７から露出する帯状配線導体２の表面を粗化液で粗化処理して粗化面を形成する。粗化処理は、例えば硫酸・過酸化水素エッチング剤及び汚れ除去剤で脱脂した後、銅系の錯化剤を含む溶剤でエッチングを行った後、塩酸にて粗化面に残った銅化合物を除去することにより行なわれる。このとき、粗化面のエッチング量は粗化前の帯状配線導体２の表面から０．２〜１．２μｍであり、表面粗さは通常０．３μｍ〜１．２μｍである。   Next, as shown in FIGS. 6A and 6B, the surface of the strip-shaped wiring conductor 2 exposed from the etching resist 7 is roughened with a roughening solution to form a roughened surface. For the roughening treatment, for example, after degreasing with a sulfuric acid / hydrogen peroxide etchant and a stain remover, after etching with a solvent containing a copper complexing agent, the copper compound remaining on the roughened surface with hydrochloric acid is removed. This is done by removing. At this time, the etching amount of the roughened surface is 0.2 to 1.2 μm from the surface of the strip-shaped wiring conductor 2 before roughening, and the surface roughness is usually 0.3 μm to 1.2 μm.

次に、図７（ａ），（ｂ）に示すように、エッチングレジスト７を除去する。エッチングレジスト７の除去には、アルカリ系のレジスト剥離液を用いればよい。   Next, as shown in FIGS. 7A and 7B, the etching resist 7 is removed. For removing the etching resist 7, an alkaline resist stripping solution may be used.

最後に、図３（ａ），（ｂ）に示したように、素子接続パッド３を露出させる開口部４を有するソルダーレジスト層５を被着させることにより図１，２に示した配線基板１０が完成する。なお、ソルダーレジスト層５は、例えばアクリル変性エポキシ樹脂等を含有する光感光性樹脂等を塗布あるいは、シート状のものを貼着した後、開口部４を有するように露光および現像した後、硬化させることにより形成される。なお、帯状配線導体２の粗化面の一部がソルダーレジスト５の開口部４内に３００〜６００μｍ程度の長さで露出することが好ましい。   Finally, as shown in FIGS. 3A and 3B, the wiring board 10 shown in FIGS. 1 and 2 is formed by depositing a solder resist layer 5 having openings 4 through which the element connection pads 3 are exposed. Is completed. The solder resist layer 5 is, for example, coated with a photosensitive resin containing an acrylic-modified epoxy resin or the like, or a sheet-like material is applied, and then exposed and developed so as to have an opening 4 and then cured. Is formed. A part of the roughened surface of the strip-shaped wiring conductor 2 is preferably exposed in the opening 4 of the solder resist 5 with a length of about 300 to 600 μm.

このように、本発明の配線基板の製造方法によれば、絶縁基体１上に半導体素子Ｓの電極端子がフリップチップ接続される素子接続パッド３を有する帯状配線導体２を複数並べて形成し、次に、帯状配線導体２における素子接続パッド３をエッチングレジスト７で選択的に覆うとともにエッチングレジスト７から露出する帯状配線導体２の表面を粗化処理した後、エッチングレジスト７を除去し、次に絶縁基体１上および帯状配線導体２上に、素子接続パッド３を露出させる開口部４を有するソルダーレジスト層５を被着させることから、素子接続パッド３は粗化によりその幅が減少することはなく、しかも素子接続パッド３の露出面は粗化されていないのでエッチングにより平滑にする必要もないので、素子接続パッド３の幅が粗化やエッチングにより狭くなることはない。したがって、半導体素子Ｓの電極端子と半田を介して接続するための素子接続パッド３の幅を十分に確保し、半導体素子Ｓの電極端子と素子接続パッド３とを半田６を介して強固に接続することが可能な配線基板を提供することができる。   As described above, according to the method for manufacturing a wiring board of the present invention, a plurality of strip-like wiring conductors 2 having element connection pads 3 to which the electrode terminals of the semiconductor element S are flip-chip connected are formed side by side on the insulating substrate 1. Further, after selectively covering the element connection pads 3 in the strip-shaped wiring conductor 2 with the etching resist 7 and roughening the surface of the strip-shaped wiring conductor 2 exposed from the etching resist 7, the etching resist 7 is removed and then insulated. Since the solder resist layer 5 having the opening 4 exposing the element connection pad 3 is deposited on the substrate 1 and the strip-shaped wiring conductor 2, the width of the element connection pad 3 is not reduced by roughening. In addition, since the exposed surface of the element connection pad 3 is not roughened, it is not necessary to make the surface smooth by etching. Not be narrowed by the ring. Therefore, a sufficient width of the element connection pad 3 for connecting to the electrode terminal of the semiconductor element S via the solder is secured, and the electrode terminal of the semiconductor element S and the element connection pad 3 are firmly connected via the solder 6. A wiring board that can be provided can be provided.

なお、本発明は上述の実施形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、上述の実施形態例では、素子接続パッド３は長方形であったが、素子接続パッド３は長方形に限らず、正方形、円形、紡錘形等の他の形状であってもよい。また上述の実施の形態例ではペリフェラル型の半導体素子を搭載する場合を示したが、エリア型の半導体素子を搭載する配線基板に適用してもよ。   The present invention is not limited to an example of the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. In the above-described embodiment, the element connection pad 3 is Although it was rectangular, the element connection pad 3 is not limited to a rectangle, but may be other shapes such as a square, a circle, and a spindle. In the above-described embodiment, the case where a peripheral type semiconductor element is mounted is shown. However, the present invention may be applied to a wiring board on which an area type semiconductor element is mounted.

１ 絶縁基体
２ 帯状配線導体
３ 素子接続パッド
４ 開口部
５ ソルダーレジスト
６ 半田
７ エッチングレジスト
１０ 配線基板
Ｓ 半導体素子 DESCRIPTION OF SYMBOLS 1 Insulation base | substrate 2 Strip | belt-shaped wiring conductor 3 Element connection pad 4 Opening part 5 Solder resist 6 Solder 7 Etching resist 10 Wiring board S Semiconductor element

Claims (2)

絶縁基体上に半導体素子接続用の帯状配線導体が複数並んで形成されているとともに、該帯状配線導体の一部に半導体素子の電極端子がフリップチップ接続される素子接続パッドが形成されており、かつ前記絶縁基体上および前記帯状配線導体上に、前記素子接続パッドを露出させる開口部を有するソルダーレジスト層が被着されている配線基板であって、前記帯状配線導体は、ソルダーレジスト層が被着する表面が粗化処理されているとともに素子接続パッドの露出面が前記粗化処理された表面よりも外側に膨出した平滑面であることを特徴とする配線基板。   A plurality of strip-shaped wiring conductors for connecting semiconductor elements are formed side by side on an insulating substrate, and an element connection pad for flip-chip connection of electrode terminals of the semiconductor elements is formed on a part of the strip-shaped wiring conductor, And a wiring board having a solder resist layer having an opening for exposing the element connection pads on the insulating substrate and the strip-shaped wiring conductor, wherein the strip-shaped wiring conductor is covered with the solder resist layer. A wiring board characterized in that a surface to be worn is roughened and an exposed surface of an element connection pad is a smooth surface bulging outward from the roughened surface. 絶縁基体上に半導体素子の電極端子がフリップチップ接続される素子接続パッドを有する帯状配線導体を複数並べて形成する工程と、前記帯状配線導体における前記素子接続パッドをエッチングレジストで選択的に覆うとともに該エッチングレジストから露出する前記帯状配線導体の表面を粗化処理した後、前記エッチングレジストを除去する工程と、前記絶縁基体上および前記帯状配線導体上に、前記素子接続パッドを露出させる開口部を有するソルダーレジスト層を被着させる工程とを備えることを特徴とする配線基板の製造方法。   A step of forming a plurality of strip-like wiring conductors having element connection pads on which an electrode terminal of a semiconductor element is flip-chip connected on an insulating substrate, and selectively covering the element connection pads on the strip-like wiring conductor with an etching resist A step of removing the etching resist after roughening the surface of the strip-shaped wiring conductor exposed from the etching resist, and an opening for exposing the element connection pad on the insulating substrate and the strip-shaped wiring conductor; And a process for depositing a solder resist layer.
JP2009155966A 2009-06-30 2009-06-30 Wiring board and manufacturing method thereof Pending JP2011014644A (en)

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JP2013093538A (en) * 2011-10-04 2013-05-16 Ngk Spark Plug Co Ltd Wiring board and manufacturing method of the same
WO2014073128A1 (en) 2012-11-07 2014-05-15 日本特殊陶業株式会社 Circuit board and method for producing same
US9578743B2 (en) 2014-09-29 2017-02-21 Ngk Spark Plug Co., Ltd. Circuit board
CN108987372A (en) * 2017-05-31 2018-12-11 台湾积体电路制造股份有限公司 chip package
US20190386193A1 (en) * 2018-03-22 2019-12-19 Innolux Corporation Display device having an electronic device disposed on a first pad and a second pad
CN110915307A (en) * 2017-05-19 2020-03-24 佐佐木贝慈 Substrate for mounting electronic component and method for manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013093538A (en) * 2011-10-04 2013-05-16 Ngk Spark Plug Co Ltd Wiring board and manufacturing method of the same
WO2014073128A1 (en) 2012-11-07 2014-05-15 日本特殊陶業株式会社 Circuit board and method for producing same
KR20140086951A (en) 2012-11-07 2014-07-08 니혼도꾸슈도교 가부시키가이샤 Wiring board and manufacturing method of the same
US9420703B2 (en) 2012-11-07 2016-08-16 Ngk Spark Plug Co., Ltd. Wiring board and manufacturing method of the same
US9578743B2 (en) 2014-09-29 2017-02-21 Ngk Spark Plug Co., Ltd. Circuit board
CN110915307A (en) * 2017-05-19 2020-03-24 佐佐木贝慈 Substrate for mounting electronic component and method for manufacturing the same
JPWO2018211991A1 (en) * 2017-05-19 2020-04-09 ベジ 佐々木 Electronic component mounting substrate and method of manufacturing the same
JP7048593B2 (en) 2017-05-19 2022-04-05 ベジ 佐々木 Substrate for mounting electronic components and its manufacturing method
CN110915307B (en) * 2017-05-19 2023-02-03 佐佐木贝慈 Substrate for mounting electronic component and method for manufacturing the same
CN108987372A (en) * 2017-05-31 2018-12-11 台湾积体电路制造股份有限公司 chip package
US20190386193A1 (en) * 2018-03-22 2019-12-19 Innolux Corporation Display device having an electronic device disposed on a first pad and a second pad
US11114597B2 (en) * 2018-03-22 2021-09-07 Innolux Corporation Display device having an electronic device disposed on a first pad and a second pad

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