JP2011009311A - Solid-state image sensor and method of manufacturing the same - Google Patents

Abstract

Provided is a solid-state imaging device in which luminance shading and wiring interlayer leakage are improved.
A solid-state imaging device 10 having a pixel region 20 in which a plurality of pixels are arranged, a semiconductor substrate 101, and a light receiving unit 102 that is formed in the pixel region 20 in the semiconductor substrate 101 and performs photoelectric conversion for each pixel. A wiring layer 105b having a wiring 111b, an insulating film 112b that insulates the wiring 111b, and a diffusion prevention film 113b that prevents diffusion of atoms included in the wiring 111b, and is formed in the pixel region 20 above the semiconductor substrate 101. The insulating film 112b included in the multilayer wiring layer 105 has a film thickness in the peripheral portion 21 of the pixel region 20 smaller than that in the central portion 22 of the pixel region 20.
[Selection] Figure 2

Description

  The present invention relates to a solid-state imaging device formed on a semiconductor substrate and a manufacturing method thereof, and more particularly to a solid-state imaging device having a multilayer wiring structure and a manufacturing method thereof.

  In recent years, in a solid-state imaging device, the number of pixels has been increased and the pixel size has been reduced, and accordingly, the wiring used has been changed from an Al wiring to a Cu wiring. Even in the case of a solid-state imaging device with a large pixel size, the peripheral circuit is becoming finer and faster, and the Al wiring has been changed to the Cu wiring in the same manner as the solid-state imaging device having a fine pixel. The demand for improved color mixing and shading is also significant.

  As a method for improving sensitivity and reducing noise, a multilayer wiring layer formed on a semiconductor substrate is composed of a film having a single refractive index in a region disposed on a light receiving region, which is a region where a light receiving unit is formed. By doing so, it has been proposed to reduce the influence of reflection and multiple interference on the light receiving unit (see, for example, Patent Document 1).

  Below, the conventional solid-state image sensor shown by patent document 1 is demonstrated, referring FIGS. 15-18. As shown in FIG. 15, the conventional solid-state imaging device 70 includes a pixel region 80 in which a plurality of pixels are arranged in a two-dimensional array, and a peripheral circuit region 90 that is a peripheral region thereof. The pixel region 80 further includes a central portion 82 that is a region including the center of the pixel region 80 and a peripheral portion 81 that is a region around the central portion 82.

  FIG. 16 is a structural cross-sectional view showing the structure of a conventional solid-state image sensor 70. FIG. 16 shows one pixel included in the pixel region 80.

  As shown in FIG. 16, in a conventional solid-state imaging device 70, a light receiving portion 302 that performs photoelectric conversion is formed on a Si substrate 301. Further, an SiN film 303 and a poly interlayer film 304 are disposed on the upper surface of the Si substrate 301. On the poly interlayer film 304, a wiring 311a, an insulating film 312a, and a diffusion preventing film 313a are disposed.

  Further, the wiring 311b, the insulating film 312b, and the diffusion preventing film 313b are disposed on the diffusion preventing film 313a, and further, the wiring 311c, the insulating film 312c, and the diffusion preventing film 313c are disposed thereon, and further thereon. An interlayer film 312d is disposed. As described above, the conventional solid-state imaging device 70 includes the multilayer wiring layer 305 constituting a multilayer structure including the three layers of the first wiring layer 305a, the second wiring layer 305b, and the third wiring layer 305c. A protective film 306 made of a SiN film, a color filter 307, and a micro lens 308 are disposed on the multilayer wiring layer 305.

  As shown in FIG. 16, each diffusion prevention film 313a, 313b and 313c has an opening in the light receiving region, and each insulation film is formed on each diffusion prevention film and on the insulation film exposed by the opening. After the deposition, the deposited insulating film is planarized by a CMP (Chemical Mechanical Polishing) method.

  As described above, by configuring the region disposed on the light receiving region with a film having a single refractive index, the influence on reflection to the light receiving unit 302 and multiple interference has been reduced.

JP-A-2005-311015

  However, in the above-described prior art, when oblique light is incident, there is a problem that vignetting of incident light due to wiring increases in the peripheral portion of the pixel region, and luminance shading deteriorates. Specifically, it is as follows.

  A step is generated by opening each diffusion prevention film above the light receiving region, and this step also causes a step in the deposited insulating film. Thereafter, when the insulating film is planarized by CMP, the insulating film 312b in the central portion 82 of the pixel region 80 becomes thinner than the insulating film 312b in the peripheral portion 81 of the pixel region 80 as shown in FIG. FIG. 17 is a schematic cross-sectional view taken along the line CC of FIG.

  Further, in the pixel region 80 and its peripheral circuit region 90, the wiring density of the pixel region 80 is smaller and the area ratio of the wiring is smaller, so that the wiring is flattened by the CMP method. Similarly, erosion occurs in the pixel region 80.

  Thus, when erosion occurs in the pixel region 80, a difference occurs in the film thicknesses of the insulating films 312 b and 312 c in the central portion 82 and the peripheral portion 81 of the pixel region 80. Therefore, as shown in FIG. 18, the multilayer wiring layer 305 is higher in the peripheral portion 81 than in the central portion 82 of the pixel region 80 due to the film thickness difference between the insulating films 312b and 312c.

  For this reason, when oblique light is incident, the vignetting of incident light in the wiring increases in the peripheral portion 81 of the pixel region 80, and luminance shading deteriorates. In particular, in the solid-state imaging device 70 having a large pixel area 80 and a large pixel, the effect of erosion becomes significant, and a thin insulating film in the central portion 82 of the pixel area 80 causes a problem of wiring interlayer leakage.

  Therefore, the present invention has been made to solve the above problems, and is a solid-state imaging device having a multilayer wiring including a Cu wiring, which improves luminance shading and improves interlayer leakage, and It aims at providing the manufacturing method.

  In order to solve the above problems, a solid-state imaging device according to the present invention is a solid-state imaging device having a pixel region in which a plurality of pixels are arranged, and is formed in a semiconductor substrate and the pixel region in the semiconductor substrate, A light receiving portion that performs photoelectric conversion for each pixel, a wiring, an insulating film that insulates the wiring, and a plurality of wiring layers each having a diffusion prevention film that prevents diffusion of atoms included in the wiring; A multilayer wiring layer formed in the pixel region above the semiconductor substrate, and the thickness of the at least one insulating film included in the multilayer wiring layer in the periphery of the pixel region is the center of the pixel region It is smaller than the film thickness in the part.

  Thereby, the film thickness of the insulating film in the central part of the pixel region is formed to be larger than the film thickness of the insulating film in the peripheral part, and the vignetting due to the wiring with respect to the light input to the peripheral part is reduced. Therefore, luminance shading can be improved. In addition, interlayer leakage can be improved by increasing the thickness of the insulating film. These exhibit a great effect particularly in a solid-state imaging device having large pixels.

  The solid-state imaging device further includes a peripheral region that surrounds the pixel region, and the multilayer wiring layer is formed in the pixel region and the peripheral region above the semiconductor substrate, and the multilayer The film thickness in the pixel region of at least one of the insulating films included in the wiring layer may be larger than the film thickness in the peripheral region.

  Thereby, since the film thickness of the insulating film in the pixel region where many wirings are arranged can be made larger than the film thickness of the insulating film in the peripheral region, interlayer leakage can be further improved.

  The at least one diffusion preventing film included in the multilayer wiring layer may be formed only on the wiring among the wiring and the light receiving unit.

  Thereby, since no diffusion prevention film is formed above the light receiving part, reflection of incident light and multiple interference can be reduced through the diffusion prevention film, so that the light collection ratio to the light receiving part is increased. be able to.

  The at least one insulating film included in the multilayer wiring layer may be formed of a film having a single refractive index different from the refractive index of the diffusion prevention film above the light receiving portion.

  As a result, by forming the region above the light receiving portion with a film having a single refractive index, reflection of incident light and multiple interference can be reduced, so that the light collection rate on the light receiving portion can be increased. it can.

  The diffusion preventing film included in the uppermost layer of the multilayer wiring layer is formed on the wiring included in the uppermost layer and above the light receiving portion, and is below the diffusion preventing film included in the uppermost layer. And the said insulating film formed above the said light-receiving part may be comprised with the film | membrane which has a single refractive index different from the refractive index of the said diffusion prevention film.

  As a result, by forming the region above the light receiving portion with a film having a single refractive index, reflection of incident light and multiple interference can be reduced, so that the light collection rate on the light receiving portion can be increased. it can.

  The solid-state imaging device may further include a color filter formed above the multilayer wiring layer and a microlens that is formed on the color filter and collects light on the light receiving unit.

  Further, the wiring may be a Cu wiring, and the diffusion prevention film may be a SiN film.

  The method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device having a pixel region in which a plurality of pixels are arranged, and performs photoelectric conversion for each pixel in the pixel region on a semiconductor substrate. Multi-layer wiring having a plurality of wiring layers each having a light receiving portion forming step for forming a light receiving portion, a wiring, an insulating film for insulating the wiring, and a diffusion preventing film for preventing diffusion of atoms included in the wiring A multilayer wiring layer forming step of forming a layer in the pixel region above the semiconductor substrate, wherein in the multilayer wiring layer forming step, the pixel region of at least one of the insulating films included in the multilayer wiring layer The multilayer wiring layer is formed so that the film thickness in the peripheral part of the pixel region is smaller than the film thickness in the central part of the pixel region.

  Thereby, the film thickness of the insulating film in the central part of the pixel region is formed to be larger than the film thickness of the insulating film in the peripheral part, and the vignetting due to the light wiring input to the peripheral part can be reduced. As a result, luminance shading can be improved. In addition, interlayer leakage can be improved by increasing the thickness of the insulating film.

  The multilayer wiring layer forming step includes depositing the insulating film in the pixel region above the semiconductor substrate, and patterning and etching the insulating film deposited in the depositing step, thereby forming the insulating film on the insulating film. A dummy pattern forming step of forming a dummy pattern in which the insulating film is denser than a peripheral portion in a central portion of the pixel region, and polishing the insulating film on which the dummy pattern is formed, And a polishing step for making the film thickness in the peripheral part of the pixel region smaller than the film thickness in the central part of the pixel region.

  As a result, the insulating film in which the dummy pattern in which the insulating film is denser in the central portion than the peripheral portion is polished by the CMP method or the like so that the insulating film thickness in the central portion can be easily insulated. It can be made thicker than the film thickness in the film.

  The solid-state imaging device further includes a peripheral region that surrounds the pixel region, and the multilayer wiring layer forming step includes the step of forming the multilayer wiring layer between the pixel region and the periphery above the semiconductor substrate. In the region, the film thickness of the at least one insulating film included in the multilayer wiring layer in the pixel region may be larger than the film thickness in the peripheral region.

  Thereby, since the film thickness of the insulating film in the pixel region where many wirings are arranged can be made larger than the film thickness of the insulating film in the peripheral region, interlayer leakage can be further improved.

  According to the solid-state imaging device and the manufacturing method thereof according to the present invention, it is possible to improve luminance shading and interlayer leakage.

2 is a schematic plan view illustrating an example of a configuration of a solid-state imaging element according to Embodiment 1. FIG. 2 is a structural cross-sectional view illustrating an example of a configuration of a solid-state imaging element according to Embodiment 1. FIG. FIG. 3 is a schematic cross-sectional view showing an example of an insulating film before polishing by the CMP method according to the first embodiment. 4 is a schematic cross-sectional view showing an example of an insulating film after polishing by the CMP method according to the first embodiment. FIG. 3 is a schematic plan view showing an example of a dummy pattern of an insulating film according to the first embodiment. FIG. 3 is a schematic plan view showing an example of a dummy pattern of an insulating film according to the first embodiment. FIG. 3 is a schematic plan view showing an example of a dummy pattern of an insulating film according to the first embodiment. FIG. 5 is a structural cross-sectional view showing one step of the method for manufacturing the solid-state imaging element according to Embodiment 1. FIG. 5 is a structural cross-sectional view showing one step of the method for manufacturing the solid-state imaging element according to Embodiment 1. FIG. 5 is a structural cross-sectional view showing one step of the method for manufacturing the solid-state imaging element according to Embodiment 1. FIG. 5 is a structural cross-sectional view showing one step of the method for manufacturing the solid-state imaging element according to Embodiment 1. FIG. 5 is a structural cross-sectional view showing one step of the method for manufacturing the solid-state imaging element according to Embodiment 1. FIG. 5 is a structural cross-sectional view showing one step of the method for manufacturing the solid-state imaging element according to Embodiment 1. FIG. 5 is a structural cross-sectional view showing one step of the method for manufacturing the solid-state imaging element according to Embodiment 1. FIG. 6 is a schematic plan view illustrating an example of a configuration of a solid-state imaging device according to Embodiment 2. FIG. 6 is a schematic cross-sectional view showing an example of an insulating film before polishing by a CMP method according to Embodiment 2. FIG. 6 is a schematic cross-sectional view showing an example of an insulating film after polishing by a CMP method according to Embodiment 2. FIG. 6 is a schematic plan view showing an example of a step pattern of an insulating film according to Embodiment 2. FIG. It is a schematic plan view which shows the structure of the conventional solid-state image sensor. It is structural sectional drawing which shows the structure of the conventional solid-state image sensor. It is a schematic sectional drawing which shows the structure of the insulating film after performing grinding | polishing by the conventional CMP method. It is structural sectional drawing which shows the structure of the center part and peripheral part of the pixel area | region of the conventional solid-state image sensor.

  Hereinafter, a solid-state imaging device and a manufacturing method thereof according to the present invention will be described in detail based on embodiments with reference to the drawings.

(Embodiment 1)
The solid-state imaging device according to the present embodiment includes a semiconductor substrate, a light receiving portion that performs photoelectric conversion for each pixel, a wiring, an insulating film that insulates the wiring, and the wiring. A plurality of wiring layers each having a diffusion preventing film for preventing diffusion of contained atoms, a multilayer wiring layer formed in a pixel region above the semiconductor substrate, and at least one insulating layer included in the multilayer wiring layer The film thickness of the film in the peripheral part of the pixel region is smaller than the film thickness in the central part of the pixel region.

  FIG. 1 is a schematic plan view showing an example of the configuration of a solid-state imaging device 10 according to the present embodiment. FIG. 1 shows a solid-state imaging device 10 that is formed into a chip. The solid-state imaging device 10 includes a pixel region 20 in which a plurality of pixels are arranged in a two-dimensional manner, and a peripheral circuit formed around the pixel region 20. Region 30. In the pixel region 20, a light receiving portion that performs photoelectric conversion is formed for each pixel. The peripheral circuit region 30 is a circuit region arranged around the pixel region 20 and includes a shift register, an AD converter, and the like.

  The pixel region 20 is divided into a central portion 22 and a peripheral portion 21. The central portion 22 is a predetermined region that includes the center of the pixel region 20 and does not include the periphery of the pixel region 20. The peripheral portion 21 is a region around the central portion 22 and includes the periphery of the pixel region 20. Regarding the two pixels included in the solid-state imaging device 10, the pixel closer to the center of the pixel region 20 in the plane is regarded as a pixel included in the central portion 22, and the other pixel is regarded as a pixel included in the peripheral portion 21. Also good.

  FIG. 2 is a structural cross-sectional view showing an example of the configuration of the solid-state imaging device 10 according to the present embodiment. FIG. 2 shows a cross section of the pixel included in the peripheral portion 21 of the pixel region 20 and a cross section of the pixel included in the central portion 22 of the pixel region 20.

  As shown in FIG. 2, the solid-state imaging device 10 includes a semiconductor substrate 101, a light receiving unit 102, a SiN film 103, a poly interlayer film 104, a multilayer wiring layer 105, a protective film 106, a color filter 107, And a microlens 108.

  The semiconductor substrate 101 is, for example, a Si substrate. As shown in FIG. 1, the semiconductor substrate 101 is divided into a pixel region 20 and a peripheral circuit region 30 in the planar direction.

  The light receiving unit 102 is, for example, a photodiode that performs photoelectric conversion. The light receiving unit 102 is formed for each pixel in the pixel region 20 of the semiconductor substrate 101.

The SiN film 103 is an example of an insulating film formed on the semiconductor substrate 101 and the light receiving unit 102, and may be an SiO ₂ film. The SiN film 103 may function as an antireflection film for light incident on the light receiving unit 102.

  The poly interlayer film 104 is an example of an interlayer insulating film such as BPSG (Boron Phosphorus Silicon Glass) formed on the SiN film 103.

  The multilayer wiring layer 105 includes a plurality of stacked wiring layers. In the example shown in FIG. 2, the multilayer wiring layer 105 includes three wiring layers, that is, a first wiring layer 105a, a second wiring layer 105b, and a third wiring layer 105c.

  The first wiring layer 105a includes a wiring 111a, an insulating film 112a that insulates the wiring 111a, and a diffusion prevention film 113a that prevents diffusion of atoms contained in the wiring 111a. Similarly, the second wiring layer 105b includes a wiring 111b, an insulating film 112b, and a diffusion preventing film 113c, and the third wiring layer 105c includes a wiring 111c, an insulating film 112c, and a diffusion preventing film 113c. .

  The wirings 111a, 111b, and 111c are all Cu wirings. Further, the thickness of the wiring 111a is, for example, 260 nm, and the thickness of the wiring 111b and the wiring 111c is, for example, 190 nm.

The insulating films 112a, 112b and 112c are all SiO ₂ films. The insulating films 112b and 112c are thinner in the peripheral portion 21 than in the central portion 22 of the pixel region 20. The film thickness of the insulating film 112a is, for example, 280 nm, and the film thicknesses of the insulating film 112b and the insulating film 112c are, for example, 320 nm at the central portion 22 of the pixel region 20 and 170-220 nm at the peripheral portion 21 of the pixel region 20. The insulating films 112a, 112b, and 112c formed above the light receiving portion 102 are formed of films having a single refractive index different from the refractive indexes of the diffusion prevention films 113a, 113b, and 113c.

  The diffusion preventing films 113a, 113b and 113c are all SiN films. Of diffusion preventing films 113a and 113b, the portion above the light receiving region is removed. Specifically, the diffusion prevention films 113a and 113b may be formed only on the wirings 111a and 111b, respectively, on the wirings 111a and 111b and above the light receiving region. The light receiving area is an area where the light receiving unit 102 is formed. The film thickness of the diffusion preventing film 113a and the diffusion preventing film 113b is, for example, 165 nm, and the film thickness of the diffusion preventing film 113c is 100 nm.

  The thickness of the diffusion prevention film 113c included in the third wiring layer 105c that is the uppermost layer of the multilayer wiring layer 105 is smaller than that of the other diffusion prevention films 113a and 113b, and the portion above the light receiving region of the diffusion prevention film 113c is The reason why the protective film 106 made of the same material is formed on the diffusion prevention film 113c is not removed. Therefore, the diffusion preventing film 113c may be used also as the protective film 106.

  The protective film 106 is an SiN film or the like that is formed on the diffusion prevention film 113 c and protects the surface of the multilayer wiring layer 105. Note that the protective film 106 also functions as a planarization film that maintains the flatness of the surface.

  The color filter 107 is a filter that is formed on the protective film 106 and transmits light of a predetermined color component. For example, the color filter 107 is formed to transmit light such as red (R), green (G), and blue (B) for each pixel. An infrared filter may be formed instead of the color filter.

  The micro lens 108 is formed on the color filter 107 and condenses incident light on the light receiving unit 102.

  As shown in FIG. 2, by reducing the thickness of the insulating films 112b and 112c in the peripheral portion 21 from the central portion 22 of the pixel region 20, vignetting due to the wiring 111c is reduced even when oblique incident light is incident. Luminance shading can be improved.

  Next, in the solid-state imaging device 10 according to the present embodiment, a method for making the film thickness of the insulating film 112b in the central portion 22 of the pixel region 20 different from the film thickness of the insulating film 112b in the peripheral portion 21 will be described.

  FIG. 3A is a schematic cross-sectional view showing the insulating film 112b taken along the line AA shown in FIG. 1 before polishing by the CMP method. FIG. 3B is a schematic cross-sectional view showing the insulating film 112b after polishing by the CMP method along the line AA shown in FIG. 3A and 3B, for simplicity, the SiN film 103 and the poly interlayer film 104, and the wiring 111a and the diffusion prevention film 113a included in the first wiring layer 105a are not shown. In addition, although the light receiving unit 102 is formed separately for each pixel as described above, for the sake of simplicity, the light receiving unit 102 is not illustrated as being separated.

  As shown in FIG. 3A, after an insulating film 112b is deposited on the entire surface of the first wiring layer 105a, a dummy pattern 120 is formed on the insulating film 112b by patterning and etching such as photolithography. The dummy pattern 120 is dense at the central portion 22 of the pixel region 20 and sparse at the peripheral portion 21. That is, the dummy pattern 120 is a pattern in which the volume ratio of the insulating film 112b left in the central portion 22 is larger than that of the insulating film 112b left in the peripheral portion 21.

  The insulating film 112b on which the dummy pattern 120 as shown in FIG. 3A is formed is polished by the CMP method, so that the insulating film becomes thicker than the peripheral part 21 in the central part 22 as shown in FIG. 3B. 112b is formed.

  4A to 4C show examples of the dummy pattern 120. FIG. As shown in each figure, dummy patterns 120a, 120b and 120c are formed in the central portion 22 so that more insulating films 112b are left in comparison with the peripheral portion 21.

  Although the insulating film 112b has been described above, the insulating film 112c is also insulated so that the central portion 22 is thicker than the peripheral portion 21 by polishing by the CMP method after forming a similar dummy pattern. A film 112c can be formed.

  Next, a method for manufacturing the solid-state imaging device 10 according to the present embodiment will be described with reference to FIGS. 5 to 11 are structural cross-sectional views showing the steps of the method for manufacturing the solid-state imaging device 10 according to the present embodiment.

  First, the light receiving portion 102 that performs photoelectric conversion is formed on the semiconductor substrate 101. A SiN film 103 is formed on the semiconductor substrate 101 in the pixel region 20 in which pixels including the light receiving unit 102 are two-dimensionally arranged. Further, BPSG or the like is deposited on the SiN film 103 and planarized by a CMP method, thereby forming a poly interlayer film 104. Through the above steps, a configuration as shown in FIG. 5 is formed. As shown in FIG. 5, the film thicknesses of the semiconductor substrate 101, the SiN film 103, and the poly interlayer film 104 are the same in the peripheral portion 21 and the central portion 22 of the pixel region 20.

  Next, as shown in FIG. 6, a first wiring layer 105 a is formed on the poly interlayer film 104. Specifically, first, an insulating film 112a is deposited on the poly interlayer film 104, and a wiring 111a is formed by a dual damascene method. Further, a diffusion preventing film 113a is formed on the entire surface over the wiring 111a and the insulating film 112a. At this time, the thickness of the insulating film 112 a is the same in the peripheral portion 21 and the central portion 22 of the pixel region 20.

  Next, as shown in FIG. 7, by removing the diffusion prevention film 113a formed above the light receiving portion 102, an opening corresponding to the light receiving region is formed by photolithography and etching. Further, an insulating film 112b is deposited on the diffusion preventing film 113a and on the insulating film 112a exposed in the opening formed in the diffusion preventing film 113a. Since the insulating film 112b has not yet been polished by the CMP method, the film thickness of the insulating film 112b at the time of deposition is the same in the peripheral portion 21 and the central portion 22 of the pixel region 20. .

  At this time, as shown in FIG. 3A, a dummy pattern is formed on the insulating film 112b by photolithography and etching. The pattern density of the dummy pattern is formed so that the area ratio is smaller and sparser in the peripheral portion 21 than in the central portion 22 of the pixel region 20.

  Thereafter, as shown in FIG. 8, the insulating film 112 b is planarized by the CMP method, so that the insulating film 112 b is formed with the peripheral portion 21 thinner than the central portion 22 of the pixel region 20 by about 50 to 100 nm. Yes (see FIG. 3B).

  Next, as shown in FIG. 9, the wiring 111 b and the diffusion prevention film 113 b are formed in the same manner as in FIGS. 6 and 7, and the diffusion prevention film 113 b formed above the light receiving unit 102 is removed. An opening corresponding to the light receiving region is formed. Further, an insulating film 112c is deposited on the diffusion preventing film 113b and on the insulating film 112b exposed in the opening formed in the diffusion preventing film 113b. Since the insulating film 112c has not yet been polished by the CMP method, the film thickness of the insulating film 112c at the time of deposition is the same in the peripheral portion 21 and the central portion 22 of the pixel region 20. .

  At this time, a dummy pattern is formed on the insulating film 112c similarly to the insulating film 112b by photolithography and etching. Then, by planarizing the insulating film 112c by a CMP method, the insulating film 112c can be formed with a peripheral portion 21 thinner than the central portion 22 of the pixel region 20 by about 50 to 100 nm as shown in FIG. (See FIGS. 3A and 3B).

  Next, as shown in FIG. 11, the wiring 111c and the diffusion preventing film 113c are formed in the insulating film 112c in the same manner as in FIG. Furthermore, the solid-state imaging device 10 shown in FIG. 2 can be manufactured by forming the protective film 106, the color filter 107, and the microlens 108 on the diffusion preventing film 113c.

  As described above, the solid-state imaging device 10 according to the present embodiment includes the multilayer wiring layer 105 having a structure in which a plurality of wiring layers including wiring, an insulating film, and a diffusion prevention film are stacked, and is included in the multilayer wiring layer 105. The film thickness of the at least one insulating film in the peripheral portion 21 of the pixel region 20 is smaller than the film thickness in the central portion 22 of the pixel region 20.

  With this configuration, even when oblique light is incident, it is possible to reduce vignetting due to the wiring 111c, which is an upper layer wiring, in the peripheral portion 21, and to improve luminance shading. In addition, since the thick insulating film is formed in the pixel region 20, it is possible to reduce wiring interlayer leakage.

(Embodiment 2)
The solid-state imaging device according to this embodiment has a peripheral region that is a region surrounding the pixel region, and the film thickness of the insulating film formed in the pixel region above the semiconductor substrate is in the peripheral region above the semiconductor substrate. It is characterized by being larger than the thickness of the formed insulating film.

  FIG. 12 is a schematic plan view showing an example of the configuration of the solid-state imaging device 40 according to the present embodiment. FIG. 12 shows a chip-shaped solid-state imaging device 40. The solid-state imaging device 40 includes a pixel region 50 in which a plurality of pixels are arranged in a two-dimensional manner, and a peripheral circuit formed around the pixel region 50. Region 60. In the pixel region 50, a light receiving portion that performs photoelectric conversion is formed for each pixel. The peripheral circuit area 60 is a circuit area arranged around the pixel area and includes a shift register, an AD converter, and the like.

  In the solid-state imaging device 40 according to the present embodiment, the configuration of each pixel is the same as the cross-sectional structure of the solid-state imaging device 10 according to Embodiment 1 shown in FIG. In addition, the manufacturing method of the solid-state imaging device 40 according to the present embodiment is substantially the same as the manufacturing method of the solid-state imaging device 10 according to the first embodiment described with reference to FIGS. The description of the same points is omitted, and different points are mainly described.

  The manufacturing method of the solid-state imaging device 40 according to the present embodiment is different from the manufacturing method of the solid-state imaging device 10 according to the first embodiment in that a step is not formed when a dummy pattern is formed when the insulating film 112b is formed. The difference is that the pattern is formed. Specifically, it is as follows.

  FIG. 13A is a schematic cross-sectional view showing the insulating film 112b before the polishing by the CMP method, taken along the line BB shown in FIG. FIG. 13B is a schematic cross-sectional view showing the insulating film 112b after polishing by the CMP method along the line BB shown in FIG. 13A and 13B do not show the SiN film 103 and the poly interlayer film 104, and the wiring 111a and the diffusion prevention film 113a included in the first wiring layer 105a for simplicity. In addition, although the light receiving unit 102 is formed separately for each pixel as described above, for the sake of simplicity, the light receiving unit 102 is not illustrated as being separated.

  As shown in FIG. 13A, after an insulating film 112b is deposited on the entire surface of the first wiring layer 105a, a step pattern 220 is formed on the insulating film 112b by photolithography and etching. The step pattern 220 is a pattern formed such that the film thickness of the insulating film 112 b is larger in the pixel region 50 than in the peripheral circuit region 60.

  The insulating film 112b on which the step pattern 220 as shown in FIG. 13A is formed is polished by the CMP method so that the insulating film 112 is thicker than the peripheral circuit area 60 in the pixel area 50 as shown in FIG. 13B. A film 112b is formed. For example, the insulating film 112b in the pixel region 50 is formed to be 100 to 200 nm thicker than the insulating film 112b in the peripheral circuit region 60. Note that the film thickness of the insulating film 112b is, for example, 320 nm in the pixel region 50.

  FIG. 14 is a schematic plan view showing an example of the step pattern 220. In the example shown in the figure, the step pattern 220 has a step formed at the boundary between the pixel region 50 and the peripheral circuit region 60.

  Accordingly, it is possible to improve the leakage or short circuit between the wirings caused by the thin insulating film 112b in the pixel region 50 due to erosion. Further, by forming the dummy pattern described in the first embodiment in the pixel region 50 of the step pattern 220, the luminance shading in the peripheral portion of the pixel region 50 can be improved as in the first embodiment.

  As described above, the solid-state imaging device and the manufacturing method thereof according to the present invention have been described based on the embodiments. However, the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which made the said embodiment the various deformation | transformation which those skilled in the art think, and the form constructed | assembled combining the component in various modifications are also contained in the scope of the present invention.

  For example, in Embodiment 1, the structure in which the film thicknesses of the two insulating films 112b and 112c are different between the central part and the peripheral part of the pixel region has been described. It may be different, or the thickness of the insulating film 112a may be different. The same applies to the second embodiment. That is, the film thickness in the central part of the pixel region of at least one of the plurality of insulating films included in the multilayer wiring layer 105 may be made larger than the film thickness in the peripheral part of the pixel region.

  In the embodiment, the color filter 107 and the microlens 108 are not necessarily required, and can be similarly applied to a structure in which these are not provided.

  The solid-state imaging device and the manufacturing method thereof according to the present invention have an effect that luminance shading and wiring interlayer leakage can be improved, and can be used for, for example, a solid-state imaging device such as a digital camera.

10, 40, 70 Solid-state imaging device 20, 50, 80 Pixel region 21, 81 Peripheral portion 22, 82 Central portion 30, 60, 90 Peripheral circuit region 101 Semiconductor substrate 102, 302 Light receiving portion 103, 303 SiN film 104, 304 poly Interlayer films 105, 305 Multilayer wiring layers 105a, 305a First wiring layers 105b, 305b Second wiring layers 105c, 305c Third wiring layers 106, 306 Protective films 107, 307 Color filters 108, 308 Microlenses 111a, 111b, 111c, 311a, 311b, 311c Wiring 112a, 112b, 112c, 312a, 312b, 312c Insulating film 113a, 113b, 113c, 313a, 313b, 313c Diffusion prevention film 120, 120a, 120b, 120c Dummy pattern 220 Step pattern 301 S i-board

Claims (10)

A solid-state imaging device having a pixel region in which a plurality of pixels are arranged,
A semiconductor substrate;
A light receiving portion that is formed in the pixel region of the semiconductor substrate and performs photoelectric conversion for each pixel;
A plurality of wiring layers each having a wiring, an insulating film that insulates the wiring, and a diffusion prevention film that prevents diffusion of atoms included in the wiring, and is formed in the pixel region above the semiconductor substrate; Multi-layer wiring layer,
A solid-state imaging device, wherein a film thickness of the at least one insulating film included in the multilayer wiring layer in the peripheral portion of the pixel region is smaller than a film thickness in a central portion of the pixel region. The solid-state imaging device further includes a peripheral region that is a region surrounding the pixel region,
The multilayer wiring layer is formed in the pixel region and the peripheral region above the semiconductor substrate,
The solid-state imaging element according to claim 1, wherein a film thickness of the at least one insulating film included in the multilayer wiring layer in the pixel region is larger than a film thickness in the peripheral region. 3. The solid-state imaging device according to claim 1, wherein at least one of the diffusion prevention films included in the multilayer wiring layer is formed only on the wiring among the wiring and the light receiving unit. The at least one said insulating film contained in the said multilayer wiring layer is comprised with the film | membrane which has a single refractive index different from the refractive index of the said diffusion prevention film above the said light-receiving part. The solid-state image sensor of Claim 1. The diffusion prevention film included in the uppermost layer of the multilayer wiring layer is formed on the wiring included in the uppermost layer and above the light receiving unit,
The insulating film formed below the diffusion prevention film included in the uppermost layer and above the light receiving portion is formed of a film having a single refractive index different from the refractive index of the diffusion prevention film. The solid-state image sensor of any one of Claims 1-4. The solid-state imaging device further includes:
A color filter formed above the multilayer wiring layer;
The solid-state imaging device according to claim 1, further comprising: a microlens that is formed on the color filter and collects light on the light receiving unit. The wiring is a Cu wiring,
The solid-state imaging device according to claim 1, wherein the diffusion prevention film is a SiN film. A method for manufacturing a solid-state imaging device having a pixel region in which a plurality of pixels are arranged,
A light receiving portion forming step for forming a light receiving portion that performs photoelectric conversion for each pixel in the pixel region of the semiconductor substrate;
A multilayer wiring layer having a plurality of wiring layers each having a wiring, an insulating film for insulating the wiring, and a diffusion preventing film for preventing diffusion of atoms included in the wiring, the pixel region above the semiconductor substrate A multilayer wiring layer forming step to be formed,
In the multilayer wiring layer forming step,
The multilayer wiring layer is formed so that the film thickness of the at least one insulating film included in the multilayer wiring layer is smaller than the film thickness in the central part of the pixel region. Device manufacturing method. The multilayer wiring layer forming step includes
A deposition step of depositing the insulating film in the pixel region above the semiconductor substrate;
Patterning and etching the insulating film deposited in the deposition step, thereby forming a dummy pattern forming a dummy pattern in which the insulating film is denser than the peripheral part in the central part of the pixel region;
9. The polishing step of polishing the insulating film on which the dummy pattern is formed so that the film thickness in the peripheral part of the pixel region is smaller than the film thickness in the central part of the pixel region. Manufacturing method of the solid-state image sensor. The solid-state imaging device further includes a peripheral region that is a region surrounding the pixel region,
The multilayer wiring layer forming step includes
The multilayer wiring layer is formed in the pixel area and the peripheral area above the semiconductor substrate, and the film thickness in the pixel area of the at least one insulating film included in the multilayer wiring layer is the film thickness in the peripheral area. The method for manufacturing a solid-state imaging device according to claim 8 or 9, wherein the solid-state imaging device is formed to be larger.

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