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JP2011009288A - Substrate built-in chip resistor and method of manufacturing the same - Google Patents

Substrate built-in chip resistor and method of manufacturing the same Download PDF

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JP2011009288A
JP2011009288A JP2009148771A JP2009148771A JP2011009288A JP 2011009288 A JP2011009288 A JP 2011009288A JP 2009148771 A JP2009148771 A JP 2009148771A JP 2009148771 A JP2009148771 A JP 2009148771A JP 2011009288 A JP2011009288 A JP 2011009288A
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substrate
chip resistor
film
internal electrode
thick film
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Katsumi Ariga
克実 有賀
Hidekazu Karasawa
秀和 唐澤
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Koa Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a substrate built-in chip resistor that makes a thick-film chip resistor small in thickness and is free of large warpage of a large-sized substrate, and to provide a method of manufacturing the same.SOLUTION: The substrate built-in chip resistor includes: an insulating substrate 11 of ≤10 μm in thickness which has a top and a reverse surface; a pair of internal electrodes 12a and 12b formed on the top surface of the substrate and made of thick-film sintered bodies; a resistance film 13 made of a thick-film sintered body, formed between the pair of internal electrodes; and a glass or metal layer 16 formed on the reverse surface of the substrate 11 and made of a thick-film sintered body. The resistance film 13 is coated with protective films 17 and 18, second internal electrodes 19a and 19b are formed of conductive resin films on parts of the protective films and the internal electrodes 12a and 12b, and a plating layer is formed on a top surface of the second internal electrode.

Description

本発明は、厚膜チップ抵抗器に係り、特に回路基板に内蔵して用いる厚さが極めて薄い基板内蔵用チップ抵抗器およびその製造方法に関する。   The present invention relates to a thick film chip resistor, and more particularly to a substrate built-in chip resistor having a very thin thickness for use in a circuit board and a method for manufacturing the same.

電子機器の軽薄短小化に伴い、チップ抵抗器等の電子部品も回路基板の表面に実装するのではなく、積層回路基板等の内層に実装する場合が生じ、その薄型化の要請に対応した構成例が提案されている(特許文献1参照)。係る基板内蔵用チップ抵抗器では、その厚さはできるだけ薄いことが好ましく、且つ片面のみに電極と抵抗体と保護膜を配置することが薄型化の観点から好ましい。   As electronic devices become lighter, thinner and smaller, electronic components such as chip resistors are not mounted on the surface of the circuit board, but may be mounted on the inner layer of a laminated circuit board, etc. An example has been proposed (see Patent Document 1). In such a chip resistor with a built-in substrate, the thickness is preferably as thin as possible, and it is preferable to dispose an electrode, a resistor, and a protective film on only one side from the viewpoint of thinning.

特開2004−140285号公報JP 2004-140285 A

しかしながら、チップ抵抗器ではアルミナ等の絶縁性基板が不可欠であり、この厚さを薄くすると基板の片面のみに電極と抵抗体と保護膜とが配置されるため、その製造段階で大判の基板に反りが生じやすく、不良品が発生し易いという問題がある。   However, an insulating substrate such as alumina is indispensable for a chip resistor, and if this thickness is reduced, an electrode, a resistor, and a protective film are disposed only on one side of the substrate. There is a problem that warpage is likely to occur and defective products are likely to occur.

本発明は、上述の事情に基づいてなされたもので、厚膜チップ抵抗器の厚さを薄くしつつ且つ製造段階で大判の基板の反りが生じない、基板内蔵用チップ抵抗器およびその製造方法を提供することを目的とする。   The present invention has been made based on the above-described circumstances, and reduces the thickness of the thick film chip resistor and does not cause warping of a large substrate at the manufacturing stage, and a method of manufacturing the chip resistor. The purpose is to provide.

本発明の基板内蔵用チップ抵抗器は、表面と裏面とを有する厚さが100μm以下の絶縁性基板と、該基板の表面に形成された一対の厚膜焼成体からなる内部電極と、該一対の内部電極間に形成された厚膜焼成体からなる抵抗膜と、該基板の裏面に形成された厚膜焼成体からなるガラス層または金属層と、を備えたことを特徴とする。   The chip resistor for a substrate according to the present invention includes an insulating substrate having a surface and a back surface and a thickness of 100 μm or less, an internal electrode made of a pair of thick film fired bodies formed on the surface of the substrate, and the pair And a glass layer or a metal layer made of a thick film fired body formed on the back surface of the substrate.

また、本発明の基板内蔵用チップ抵抗器の製造方法は、表面と裏面とを有する厚さが100μm以下の大判の絶縁性基板を準備し、該大判の基板の表面の各区画に厚膜焼成体からなる内部電極を形成し、該大判の基板の裏面に厚膜焼成体からなるガラス層または金属層を形成し、 前記内部電極と接続する厚膜焼成体からなる抵抗膜を形成し、該抵抗膜を覆う保護膜を形成し、大判の基板を各区画毎のチップ片に分割し、該チップ片の電極表面にメッキ層を形成する、ことを特徴とする。   In addition, the method for manufacturing a chip resistor with a built-in substrate according to the present invention provides a large-sized insulating substrate having a surface and a back surface and a thickness of 100 μm or less, and fires a thick film on each section of the surface of the large-sized substrate. Forming an internal electrode made of a body, forming a glass layer or a metal layer made of a thick film fired body on the back surface of the large substrate, forming a resistance film made of a thick film fired body connected to the internal electrode, A protective film covering the resistance film is formed, a large substrate is divided into chip pieces for each section, and a plating layer is formed on the electrode surface of the chip pieces.

本発明によれば、絶縁性基板の裏面にガラス層からなる厚膜焼成体を形成するので、その製造段階で、薄い大判の基板の表面にのみ厚膜内部電極、厚膜抵抗膜、厚膜ガラス保護膜等の厚膜焼成体を形成するに際して、両者の熱膨張がバランスして、大判の基板の反りを防止できる。従って、通常の寸法の大判の基板(例えば50mm×60mm)を用いつつ、従来生じていた基板の反りによる基板の割れ等を防止することができ、高い歩留まりで基板内蔵用チップ抵抗器を製造することができる。   According to the present invention, since a thick film fired body made of a glass layer is formed on the back surface of the insulating substrate, the thick film internal electrode, the thick film resistance film, and the thick film are formed only on the surface of the thin large substrate in the manufacturing stage. When forming a thick film fired body such as a glass protective film, the thermal expansion of the two is balanced, and warping of a large substrate can be prevented. Therefore, while using a large-sized substrate having a normal size (for example, 50 mm × 60 mm), it is possible to prevent the substrate from being cracked due to the warping of the substrate, and to manufacture a chip resistor with a built-in substrate with a high yield. be able to.

本発明の第1実施形態の基板内蔵用チップ抵抗器の(a)は断面図であり、(b)は上面図であり、(c)は底面図である。FIG. 2A is a cross-sectional view, FIG. 2B is a top view, and FIG. 3C is a bottom view of the chip resistor with a built-in substrate according to the first embodiment of the present invention. そのチップ抵抗器の各部の厚さの例を示す説明図である。It is explanatory drawing which shows the example of the thickness of each part of the chip resistor. 本発明の第2実施形態の基板内蔵用チップ抵抗器とその変形例の断面図である。It is sectional drawing of the chip resistor for board | substrates of 2nd Embodiment of this invention, and its modification. 本発明の第1実施形態のチップ抵抗器の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the chip resistor of 1st Embodiment of this invention. 本発明の第2実施形態のチップ抵抗器の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the chip resistor of 2nd Embodiment of this invention. 本発明の第2実施形態の変形例のチップ抵抗器の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the chip resistor of the modification of 2nd Embodiment of this invention. 本発明のチップ抵抗器の積層回路基板への内装状態を示す説明図である。It is explanatory drawing which shows the interior state to the multilayer circuit board of the chip resistor of this invention.

以下、本発明の実施形態について、図1乃至図7を参照して説明する。なお、各図中、同一または相当する部材または要素には、同一の符号を付して説明する。   Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 7. In addition, in each figure, the same code | symbol is attached | subjected and demonstrated to the same or equivalent member or element.

本発明の第1実施形態のチップ抵抗器は、図1および図2に示すように、表面と裏面とを有する厚さが100μm程度のアルミナ等の絶縁性基板11の表面に、厚さが10μm程度のAg−Pd等の厚膜焼成体からなる一対の内部電極12a,12bを備え、該一対の電極間に跨るようにRuO等の厚膜焼成体からなる抵抗膜13が配置されている。抵抗膜13は厚膜焼成体からなるガラス層保護膜17およびエポキシ樹脂等からなる保護膜18に被覆されている。そして、内部電極12a,12bはそれぞれ厚さ7μm程度のNiメッキ層14a,14bおよびCuメッキ層15a,15bにより被覆されている。 As shown in FIGS. 1 and 2, the chip resistor according to the first embodiment of the present invention has a thickness of 10 μm on the surface of an insulating substrate 11 such as alumina having a surface and a back surface of about 100 μm. A pair of internal electrodes 12a and 12b made of a thick film fired body such as Ag—Pd is provided, and a resistance film 13 made of a thick film fired body such as RuO 2 is disposed between the pair of electrodes. . The resistance film 13 is covered with a glass layer protective film 17 made of a thick film fired body and a protective film 18 made of an epoxy resin or the like. The internal electrodes 12a and 12b are covered with Ni plating layers 14a and 14b and Cu plating layers 15a and 15b having a thickness of about 7 μm, respectively.

基板11の裏面に、厚さ10μm程度の例えばホウケイ酸鉛系の厚膜焼成体からなるガラス層16が形成されている。このガラス層16は、基板11の厚さが薄いためこの機械的強度を増すための補強層としての役割を果たしている。   On the back surface of the substrate 11, a glass layer 16 made of, for example, a lead borosilicate thick film fired body having a thickness of about 10 μm is formed. The glass layer 16 serves as a reinforcing layer for increasing the mechanical strength because the substrate 11 is thin.

そして、抵抗器全体としての厚さは134μmとなり、厚さ150μm以下の回路基板に内蔵が可能な厚膜チップ抵抗器が得られる。なお、抵抗器のサイズは、例えば1005型(1.0mm×0.5mm)および0603型(0.6mm×0.3mm)等の通常のチップ抵抗器サイズに適用が可能であり、通常のチップ抵抗器の厚さの半分以下の厚さに低減できる。   The thickness of the entire resistor is 134 μm, and a thick film chip resistor that can be built in a circuit board having a thickness of 150 μm or less is obtained. The size of the resistor can be applied to normal chip resistor sizes such as 1005 type (1.0 mm × 0.5 mm) and 0603 type (0.6 mm × 0.3 mm). The thickness can be reduced to less than half the thickness of the resistor.

図3は本発明の第2実施形態とその変形例の基板内蔵用チップ抵抗器を示す。第2実施形態のチップ抵抗器は図3(a)に示すように、内部電極12a,12b上にこれに接続し、且つこれよりも大面積で、保護膜17,18に重なるAgを主成分とした導電性樹脂からなる第2内部電極19a,19bを備え、該電極上にNiメッキ層14a,14bおよびCuメッキ層15a,15bが被着されている。   FIG. 3 shows a substrate built-in chip resistor according to the second embodiment of the present invention and its modification. As shown in FIG. 3A, the chip resistor of the second embodiment is mainly composed of Ag connected to the internal electrodes 12a and 12b and having a larger area and overlapping the protective films 17 and 18. The second internal electrodes 19a and 19b made of the conductive resin are provided, and Ni plating layers 14a and 14b and Cu plating layers 15a and 15b are deposited on the electrodes.

基板内蔵用チップ抵抗器では、回路基板に内装した後、レーザビームを照射して外部電極を露出させ外部配線に接続する場合があり、外部電極はできるだけ大きいことが好ましい。この実施形態では、保護膜17,18の形成後に保護膜17,18に重なるようにAgを主成分とした導電性樹脂からなる第2内部電極19a,19bを形成し、その上にNiメッキ層14a,14bおよびCuメッキ層15a,15bを形成することで、内部電極12a,12bよりも大きな外部電極を備えた基板内蔵用チップ抵抗器を作成できる。   In the case of the chip resistor for a built-in substrate, there is a case where the external electrode is exposed by irradiating a laser beam after being built in the circuit board and connected to the external wiring, and the external electrode is preferably as large as possible. In this embodiment, after forming the protective films 17 and 18, second internal electrodes 19a and 19b made of a conductive resin mainly composed of Ag are formed so as to overlap the protective films 17 and 18, and a Ni plating layer is formed thereon. By forming 14a and 14b and Cu plating layers 15a and 15b, a chip resistor with a built-in substrate having an external electrode larger than the internal electrodes 12a and 12b can be produced.

図3(b)はこの変形例のチップ抵抗器を示す。この例では、抵抗膜13上に内部電極12a,12bを配置し、その他の構成は図3(a)の実施形態と変わらない。この場合、図3(a)のように内部電極端部に抵抗膜端部が重ならないので、抵抗膜内部電極12a,12bと保護膜17,18とが重なる部分の高さを平坦化することができ、チップ抵抗器全体としての高さを低減することができる。   FIG. 3B shows a chip resistor of this modification. In this example, the internal electrodes 12a and 12b are arranged on the resistance film 13, and other configurations are the same as those in the embodiment of FIG. In this case, the resistance film end does not overlap the internal electrode end as shown in FIG. 3A, so that the height of the portion where the resistance film internal electrodes 12a, 12b and the protective films 17, 18 overlap is flattened. Thus, the height of the entire chip resistor can be reduced.

図3(c)はさらなる変形例のチップ抵抗器を示す。この例では、図3(b)に示す実施形態に対して、内部電極12a,12bを省略し、第2内部電極19a,19bで直接抵抗膜13と接続するようにしたものである。これにより、さらなるチップ抵抗器の高さの低減が可能である。   FIG. 3 (c) shows a further modified chip resistor. In this example, the internal electrodes 12a and 12b are omitted and the second internal electrodes 19a and 19b are directly connected to the resistance film 13 in the embodiment shown in FIG. As a result, the height of the chip resistor can be further reduced.

次に、本発明のチップ抵抗器の製造工程について説明する。まず、図4(a)に示すように、表面と裏面とを有する厚さが100μm以下のアルミナ等のセラミックスからなる大判の絶縁性基板21を準備する。この基板21には、縦横の分割溝21aを備え、デバイス形成後に各区画毎にチップ片に分割可能となっている。なお、分割溝21aは型押しやレーザ加工機により形成する。   Next, the manufacturing process of the chip resistor of the present invention will be described. First, as shown in FIG. 4A, a large insulating substrate 21 made of ceramics such as alumina having a thickness of 100 μm or less and having a front surface and a back surface is prepared. This substrate 21 is provided with vertical and horizontal dividing grooves 21a, and can be divided into chip pieces for each section after device formation. The dividing groove 21a is formed by embossing or a laser processing machine.

そして、図4(b)に示すように、基板21の表面の各区画に跨る内部電極パターンをAg−Pdペーストのスクリーン印刷にて形成し、乾燥後焼成することで、厚膜焼成体からなる内部電極22を形成する。基板21の裏面には、一例としてホウケイ酸鉛系のガラスペーストをその全面にスクリーン印刷し、乾燥後焼成して厚膜焼成体からなるガラス層26を形成する。   And as shown in FIG.4 (b), it forms from the thick film fired body by forming the internal electrode pattern ranging over each division of the surface of the board | substrate 21 by screen printing of Ag-Pd paste, and baking after drying. The internal electrode 22 is formed. On the back surface of the substrate 21, as an example, a lead borosilicate glass paste is screen-printed on the entire surface, dried and fired to form a glass layer 26 made of a thick film fired body.

なお、内部電極22の焼成とガラス層26の焼成とは同時に行ってもよい。このように、基板21の裏面に厚膜焼成体からなるガラス層を形成することで、薄い基板21の表裏面に厚膜焼成体が形成され、熱膨張がバランスし、以降の熱処理工程で基板21の反りを抑制できる。   The firing of the internal electrode 22 and the firing of the glass layer 26 may be performed simultaneously. Thus, by forming a glass layer made of a thick film fired body on the back surface of the substrate 21, a thick film fired body is formed on the front and back surfaces of the thin substrate 21, and thermal expansion is balanced. 21 warpage can be suppressed.

次に、図4(c)に示すように、RuOペーストのスクリーン印刷にて一区画両側の内部電極22,22に跨る抵抗膜パターンを形成し、乾燥後焼成することで、厚膜焼成体からなる抵抗膜13を各区画に形成する。そして、図4(d)に示すように、ガラスペーストのスクリーン印刷にて抵抗膜13を被覆するガラス保護膜パターンをスクリーン印刷にて形成し、乾燥後焼成することで、抵抗膜13を被覆する厚膜焼成体からなるガラス保護膜17を形成する。 Next, as shown in FIG. 4 (c), a thick film fired body is formed by forming a resistive film pattern straddling the inner electrodes 22 and 22 on both sides of one section by screen printing of RuO 2 paste, and firing after drying. The resistance film 13 made of is formed in each section. Then, as shown in FIG. 4D, a glass protective film pattern that covers the resistive film 13 is formed by screen printing by screen printing of glass paste, and dried and baked to cover the resistive film 13. A glass protective film 17 made of a thick film fired body is formed.

次に、図4(e)に示すように、レーザトリミングを適宜行い、抵抗値を調整する。図中の符号Tはトリミング跡を示す。そして、図4(f)に示すように、エポキシ樹脂等の樹脂ペーストのスクリーン印刷にてガラス保護膜17を被覆する樹脂保護膜パターンをスクリーン印刷にて形成し、加温硬化することで、ガラス保護膜を被覆する樹脂保護膜18を形成する。   Next, as shown in FIG. 4E, laser trimming is appropriately performed to adjust the resistance value. A symbol T in the figure indicates a trimming mark. And as shown in FIG.4 (f), the resin protective film pattern which coat | covers the glass protective film 17 by screen printing of resin pastes, such as an epoxy resin, is formed by screen printing, and it heat-hardens, so that glass A resin protective film 18 that covers the protective film is formed.

次に、1次ブレークと2次ブレークにより、大判の基板21をチップ個片の基板11に分割し、この時、大判の基板段階の内部電極22はチップ個片両端の内部電極12a,12bに分割され、裏面の全面に形成したガラス層はチップ個片毎のガラス層16に分割される。なお、分割はダイシングまたはスクライビングによって行ってもよい。   Next, the large-sized substrate 21 is divided into chip pieces of the substrate 11 by the primary break and the secondary break. At this time, the internal electrodes 22 of the large-sized substrate stage are connected to the internal electrodes 12a and 12b at both ends of the chip pieces. The glass layer which is divided and formed on the entire back surface is divided into glass layers 16 for each chip piece. The division may be performed by dicing or scribing.

そして、保護膜17,18に被覆されていない内部電極12a,12bの表面にNiメッキおよびCuメッキを施すことで、Niメッキ層14a,14bおよびCuメッキ層15a,15bを形成する。この段階を図4(f)に示し、この段階でこのチップ抵抗器の製造工程が完了する。   Then, Ni plating layers 14a and 14b and Cu plating layers 15a and 15b are formed by performing Ni plating and Cu plating on the surfaces of the internal electrodes 12a and 12b not covered with the protective films 17 and 18, respectively. FIG. 4F shows this stage, and at this stage, the manufacturing process of this chip resistor is completed.

上記製造工程によれば、その初期段階で大判の基板の裏面にガラス層からなる厚膜焼成体を形成するので、薄い大判の基板の表面にのみ厚膜内部電極、厚膜抵抗膜、厚膜ガラス保護膜等の厚膜焼成体を形成するに際して、両者の熱膨張がバランスして、大判の基板の反りを防止できる。従って、通常の寸法の大判の基板(例えば50mm×60mm)を用いつつ、従来生じていた基板の反りによる基板の割れ等を防止することができ、高い歩留まりで基板内蔵用チップ抵抗器を製造することができる。   According to the above manufacturing process, since the thick film fired body made of the glass layer is formed on the back surface of the large substrate at the initial stage, the thick film internal electrode, the thick film resistance film, and the thick film are formed only on the surface of the thin large substrate. When forming a thick film fired body such as a glass protective film, the thermal expansion of the two is balanced, and warping of a large substrate can be prevented. Therefore, while using a large-sized substrate having a normal size (for example, 50 mm × 60 mm), it is possible to prevent the substrate from being cracked due to the warp of the substrate, which is conventionally generated, and to manufacture a chip resistor with a built-in substrate at a high yield. be able to.

また、このチップ抵抗器は、薄いセラミックス絶縁性基板11の裏面に厚膜焼成体であるガラス層16を備えるので、ガラス層16が基板11の補強材として機能し、その使用段階で基板の折損等に対して補強効果を発揮できる。なお、ガラス層16は、金属層にしてもよい。この場合、例えば、内部電極22と同じ材料を基板11の裏面にスクリーン印刷やスピンコート等の方法で印刷し、焼成する。金属層とした場合は、基板の補強等の効果に加えて、抵抗体の放熱効果も向上する。ただし、後の工程において金属層にメッキ層が形成されることから、チップ抵抗器全体の厚みが増すことになる。このため、低背化という点においてはガラス層とすることが好ましい。   In addition, since this chip resistor includes a glass layer 16 that is a thick film fired body on the back surface of the thin ceramic insulating substrate 11, the glass layer 16 functions as a reinforcing material for the substrate 11, and breaks the substrate at the stage of use. Reinforcing effects can be demonstrated. The glass layer 16 may be a metal layer. In this case, for example, the same material as that of the internal electrode 22 is printed on the back surface of the substrate 11 by a method such as screen printing or spin coating, and baked. When the metal layer is used, in addition to the effect of reinforcing the substrate, the heat dissipation effect of the resistor is also improved. However, since a plating layer is formed on the metal layer in a later process, the thickness of the entire chip resistor is increased. For this reason, it is preferable to use a glass layer in terms of reducing the height.

次に、図3(a)に示す本発明の第2実施形態の基板内蔵用チップ抵抗器の製造工程について、図5を参照して説明する。図5(a)−(f)の工程、すなわち、分割溝21aを備えた大判の基板21を準備し、基板表面に内部電極22を形成し、基板裏面にガラス層26を形成し、基板表面に抵抗膜13、ガラス保護膜17,樹脂保護膜18を形成する工程は図4(a)−(f)の工程と同じである。   Next, a manufacturing process of the substrate built-in chip resistor of the second embodiment of the present invention shown in FIG. 3A will be described with reference to FIG. 5 (a)-(f), that is, a large substrate 21 provided with a dividing groove 21a is prepared, an internal electrode 22 is formed on the substrate surface, a glass layer 26 is formed on the substrate back surface, and the substrate surface The steps of forming the resistance film 13, the glass protective film 17, and the resin protective film 18 are the same as the steps of FIGS.

このチップ抵抗器の製造工程では、樹脂保護膜18の形成後に、Agを主成分とした導電性樹脂ペーストをスクリーン印刷して、保護膜17,18の一部と内部電極22上に第2内部電極パターンを形成し、加温硬化することでAgを主成分とした導電性樹脂による第2内部電極19を形成する。なお、図示の例では、第2内部電極19は分割性を低下させないように分割溝21aを覆わないように形成しているが、連続して形成してもよい。   In this chip resistor manufacturing process, after the resin protective film 18 is formed, a conductive resin paste containing Ag as a main component is screen-printed to form a second internal portion on the protective films 17 and 18 and the internal electrode 22. By forming an electrode pattern and heating and curing, the second internal electrode 19 made of a conductive resin mainly composed of Ag is formed. In the example shown in the figure, the second internal electrode 19 is formed so as not to cover the dividing groove 21a so as not to deteriorate the dividing property, but may be formed continuously.

そして、1次ブレークと2次ブレークにより、大判の基板21をチップ個片の基板11に分割し、第2内部電極19a,19bの表面にNiメッキおよびCuメッキを施すことで、Niメッキ層14a,14bおよびCuメッキ層15a,15bを形成する。この段階で、図3(a)に示す本発明の第2実施形態のチップ抵抗器が完成する。このチップ抵抗器では、第1実施形態のチップ抵抗器と比べ、大きな外部電極が得られるので、回路基板に内蔵後、良好な実装性が得られることは上述のとおりである。   Then, the large-sized substrate 21 is divided into chip-piece substrates 11 by the primary break and the secondary break, and Ni plating and Cu plating are applied to the surfaces of the second internal electrodes 19a and 19b. , 14b and Cu plating layers 15a, 15b. At this stage, the chip resistor according to the second embodiment of the present invention shown in FIG. Since this chip resistor provides a larger external electrode as compared with the chip resistor of the first embodiment, it is as described above that good mountability can be obtained after being incorporated in the circuit board.

次に、図3(c)に示す本発明の第2実施形態の変形例のチップ抵抗器の製造工程について、図6を参照して説明する。このチップ抵抗器は、抵抗膜13を基板表面の最下層に配置し、内部電極12a,12bの配置を省略し、直接第2内部電極19a,19bを抵抗膜13に接続するようにした点で、図3(a)に示したチップ抵抗器と異なる。   Next, a manufacturing process of the chip resistor of the modification of the second embodiment of the present invention shown in FIG. 3C will be described with reference to FIG. In this chip resistor, the resistive film 13 is disposed in the lowest layer on the substrate surface, the internal electrodes 12a and 12b are omitted, and the second internal electrodes 19a and 19b are directly connected to the resistive film 13. This is different from the chip resistor shown in FIG.

このため、図6(b)に示すように、大判の基板の表面に抵抗膜23を配置し、裏面にガラス層26を配置する。そして、図6(c)に示すようにガラス保護膜17を配置し、図6(d)に示すようにガラス保護膜17の両端部を被覆するように第2内部電極19を抵抗膜23上に配置する。そして、図6(e)に示すように抵抗膜23の各区画毎に適宜トリミングを行い、図6(f)に示すように第2内部電極19の一部を被覆するように樹脂保護膜18を形成する。   For this reason, as shown in FIG. 6B, a resistance film 23 is disposed on the surface of a large substrate, and a glass layer 26 is disposed on the back surface. Then, the glass protective film 17 is disposed as shown in FIG. 6C, and the second internal electrode 19 is placed on the resistance film 23 so as to cover both ends of the glass protective film 17 as shown in FIG. 6D. To place. Then, trimming is appropriately performed for each section of the resistance film 23 as shown in FIG. 6E, and the resin protective film 18 is covered so as to cover a part of the second internal electrode 19 as shown in FIG. Form.

そして、1次ブレークと2次ブレークにより、大判の基板21をチップ個片の基板11に分割し、第2内部電極19a,19bの表面にNiメッキおよびCuメッキを施すことで、Niメッキ層14a,14bおよびCuメッキ層15a,15bを備えた図3(c)に示すチップ抵抗器が完成する。このチップ抵抗器では、図3(a)に示すチップ抵抗器と比べ、低背化できることは上述のとおりである。   Then, the large-sized substrate 21 is divided into chip-piece substrates 11 by the primary break and the secondary break, and Ni plating and Cu plating are applied to the surfaces of the second internal electrodes 19a and 19b. 14b and the Cu plating layers 15a and 15b, the chip resistor shown in FIG. 3C is completed. As described above, this chip resistor can be reduced in height as compared with the chip resistor shown in FIG.

図7は、本発明のチップ抵抗器の積層回路基板への内装例を示す。この例では、積層回路基板31は、基板31a,31b,31cが積層して形成され、基板31bに設けた凹部に本発明のチップ抵抗器が内装されている。このチップ抵抗器は、絶縁性基板11の表面に抵抗膜が配置され、保護膜18により該抵抗膜が被覆され、その両側にCuメッキ層を表面に備えた外部電極18が配置されている。そして、絶縁性基板11の裏面側には厚膜焼成体であるガラス層16が配置されている。   FIG. 7 shows an example of the interior of the chip resistor of the present invention on a laminated circuit board. In this example, the laminated circuit board 31 is formed by laminating boards 31a, 31b, and 31c, and the chip resistor of the present invention is housed in a recess provided in the board 31b. In this chip resistor, a resistive film is disposed on the surface of the insulating substrate 11, the resistive film is covered with a protective film 18, and external electrodes 18 having a Cu plating layer on the surface are disposed on both sides thereof. A glass layer 16 that is a thick film fired body is disposed on the back side of the insulating substrate 11.

積層回路基板31の内層には配線層32が設けられ、このチップ抵抗器の外部電極15に接続されている。そして、このチップ抵抗器は接着剤33を介して上層の基板31aに接合されている。このチップ抵抗器は厚さ(高さ)が150μm以下と極めて薄く、且つ裏面に補強材としてのガラス層16を備え、十分な機械的強度を有するので、軽薄短小が要求される回路基板の内装用の抵抗器として好適である。   A wiring layer 32 is provided in the inner layer of the multilayer circuit board 31 and is connected to the external electrode 15 of this chip resistor. The chip resistor is bonded to the upper substrate 31 a via an adhesive 33. This chip resistor has an extremely thin thickness (height) of 150 μm or less, and has a glass layer 16 as a reinforcing material on the back surface and has sufficient mechanical strength. It is suitable as a resistor for use.

これまで本発明の一実施形態について説明したが、本発明は上述の実施形態に限定されず、その技術的思想の範囲内において種々異なる形態にて実施されてよいことは言うまでもない。   Although one embodiment of the present invention has been described so far, it is needless to say that the present invention is not limited to the above-described embodiment, and may be implemented in various forms within the scope of the technical idea.

本発明のチップ抵抗器は、軽薄短小が要求される回路基板の内装用の抵抗器として好適に利用可能である。   The chip resistor of the present invention can be suitably used as a resistor for interior of a circuit board that is required to be light and thin.

Claims (7)

表面と裏面とを有する厚さが100μm以下の絶縁性基板と、
該基板の表面に形成された一対の厚膜焼成体からなる内部電極と、
該一対の内部電極間に形成された厚膜焼成体からなる抵抗膜と、
該基板の裏面に形成された厚膜焼成体からなるガラス層または金属層と、を備えた基板内蔵用チップ抵抗器。
An insulating substrate having a thickness of 100 μm or less having a front surface and a back surface;
An internal electrode made of a pair of thick film fired bodies formed on the surface of the substrate;
A resistive film made of a thick film fired body formed between the pair of internal electrodes;
A chip resistor with a built-in substrate, comprising: a glass layer or a metal layer made of a thick film fired body formed on the back surface of the substrate.
前記抵抗器の高さが150μm以下である、請求項1に記載の基板内蔵用チップ抵抗器。   The chip resistor for a substrate according to claim 1, wherein the height of the resistor is 150 μm or less. 前記抵抗膜が保護膜に被覆され、該保護膜の一部と前記内部電極上に導電性樹脂膜からなる第2内部電極を備え、該第2内部電極の表面にメッキ層を備えた請求項1に記載の基板内蔵用チップ抵抗器。   The resistance film is covered with a protective film, and a second internal electrode made of a conductive resin film is provided on a part of the protective film and the internal electrode, and a plating layer is provided on the surface of the second internal electrode. The chip resistor for a substrate according to 1. 表面と裏面とを有する厚さが100μm以下の大判の絶縁性基板を準備し、
該大判の基板の表面の各区画に厚膜焼成体からなる内部電極を形成し、
該大判の基板の裏面に厚膜焼成体からなるガラス層または金属層を形成し、
前記内部電極と接続する厚膜焼成体からなる抵抗膜を形成し、
該抵抗膜を覆う保護膜を形成し、
前記大判の基板を各区画毎のチップ片に分割し、
該チップ片の電極表面にメッキ層を形成する、基板内蔵用チップ抵抗器の製造方法。
Preparing a large-sized insulating substrate having a thickness of 100 μm or less having a front surface and a back surface;
Forming an internal electrode made of a thick film fired body in each section of the surface of the large substrate;
A glass layer or a metal layer made of a thick film fired body is formed on the back surface of the large substrate,
Forming a resistive film made of a thick film fired body connected to the internal electrode;
Forming a protective film covering the resistive film;
Dividing the large substrate into chip pieces for each compartment;
A method of manufacturing a chip resistor for incorporating a substrate, wherein a plating layer is formed on the electrode surface of the chip piece.
表面と裏面とを有する厚さが100μm以下の大判の絶縁性基板を準備し、
該大判の基板の表面の各区画に厚膜焼成体からなる抵抗膜を形成し、
該大判の基板の裏面に厚膜焼成体からなるガラス層または金属層を形成し、
前記抵抗膜と接続する厚膜焼成体からなる内部電極を形成し、
前記抵抗膜を覆う保護膜を形成し、
前記大判の基板を各区画毎のチップ片に分割し、
該チップ片の電極表面にメッキ層を形成する、基板内蔵用チップ抵抗器の製造方法。
Preparing a large-sized insulating substrate having a thickness of 100 μm or less having a front surface and a back surface;
Forming a resistive film made of a thick film fired body in each section of the surface of the large substrate;
A glass layer or a metal layer made of a thick film fired body is formed on the back surface of the large substrate,
Forming an internal electrode made of a thick film fired body connected to the resistance film;
Forming a protective film covering the resistive film;
Dividing the large substrate into chip pieces for each compartment;
A method of manufacturing a chip resistor for incorporating a substrate, wherein a plating layer is formed on the electrode surface of the chip piece.
前記大判の基板には分割溝が形成されている、請求項4または請求項5に記載の基板内蔵用チップ抵抗器の製造方法。   6. The method of manufacturing a chip resistor with a built-in substrate according to claim 4, wherein a split groove is formed in the large substrate. 前記保護膜の一部と前記内部電極上に導電性樹脂膜からなる第2内部電極を形成し、該第2内部電極の表面にメッキ層を形成する、請求項4または請求項5に記載の基板内蔵用チップ抵抗器の製造方法。   The second internal electrode made of a conductive resin film is formed on a part of the protective film and the internal electrode, and a plating layer is formed on the surface of the second internal electrode. A method of manufacturing a chip resistor for a substrate.
JP2009148771A 2009-06-23 2009-06-23 Substrate built-in chip resistor and method of manufacturing the same Pending JP2011009288A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160172083A1 (en) 2014-12-15 2016-06-16 Samsung Electro-Mechanics Co., Ltd. Resistor element and method of manufacturing the same
CN115295262A (en) * 2022-07-14 2022-11-04 捷群电子科技(淮安)有限公司 Anti-vulcanization thick film sheet type fixed resistor and use method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160172083A1 (en) 2014-12-15 2016-06-16 Samsung Electro-Mechanics Co., Ltd. Resistor element and method of manufacturing the same
US10204721B2 (en) 2014-12-15 2019-02-12 Samsung Electro-Mechanics Co., Ltd. Resistor element and method of manufacturing the same
CN115295262A (en) * 2022-07-14 2022-11-04 捷群电子科技(淮安)有限公司 Anti-vulcanization thick film sheet type fixed resistor and use method thereof
CN115295262B (en) * 2022-07-14 2024-06-11 捷群电子科技(淮安)有限公司 Anti-vulcanization thick film chip type fixed resistor and use method thereof

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