JP2011008824A - Information memory device, information transmission method, information transmission system, information processor, and program - Google Patents

Abstract

Transfer processing is performed in correspondence with two transfer modes.
A first command set that can be recognized by a first host system including a plurality of areas in which physical address spaces are not continuous is a command indicated by C. The second command set that can be recognized by the second host system having a continuous physical address space is a command indicated by B. On the other hand, a command set that can be recognized by the storage system is a command set indicated by A including a first command set indicated by C and a second command set indicated by B. In other words, the command set that can be recognized by the storage system includes two types of command sets: a first command set that can be recognized by the first host system and a second command set that can be recognized by the second host system. You can say that. The present invention can be applied to a storage system.
[Selection] Figure 11

Description

  The present invention relates to an information storage device, an information transfer method, an information transfer system, an information processing device, a program, and a recording medium, and in particular, an information storage device, an information transfer method, and information suitable for use in transferring information. The present invention relates to a transfer system, an information processing apparatus, a program, and a recording medium.

  Conventionally, a data processing device to which a memory card or the like incorporating a memory is connected is used (for example, see Patent Document 1).

  Conventionally, a DMA (Direct Memory Access) controller has been used to transfer data between the host and the storage. Direct Memory Access is the direct transfer of data between memory and memory or memory and I / O device regardless of the machine language instruction group. The DMA controller is a controller for controlling the DMA function.

  For data transfer using the DMA function, data transfer is performed using a descriptor in which data transfer control information such as data transfer address and data transfer size is described, and transfer information is registered without using a transfer element. In some cases, data transfer is performed by directly writing to the data.

  For example, as shown in FIG. 1, the transfer method using the descriptor is a separate physical address space managed for each page as in a memory system used in a personal computer or the like, that is, continuous logical addresses. The information defined as being stored in the space is preferably used for data transfer in a case where the information is stored in the actual physical address space with a plurality of discrepancies. On the other hand, in the case shown in FIG. 1, if data transfer is performed by directly writing the transfer information to a register or the like, it is necessary to write the transfer information to the register at every transfer delimiter. It may increase and cause a decrease in the transfer rate.

  On the other hand, as shown in FIG. 2, when data transfer using a descriptor is performed in an embedded system that can secure a continuous physical address space as in the logical address space, The transfer time required for automatic acquisition becomes a transfer overhead, which can be a factor of reducing the transfer rate.

  An example of conventional data transfer will be described with reference to FIG.

  The host system 1 and the storage system 2 are connected by a common bus 3.

  Data is transferred to the DMA controller 12 in either a data transfer mode, in which data is transferred using a descriptor, or data is transferred by directly writing transfer information to a register or the like without using a descriptor. It is set whether or not.

  When receiving a data transfer command from an operation input unit (not shown), the CPU 11 of the host system 1 supplies a command for starting DMA transfer to the DMA controller 12. When the DMA controller 12 receives a command to start DMA transfer from the CPU 11, the DMA controller 12 acquires information on data transfer based on the setting, and the storage memory of the storage system 2 via the I / F 14, the common bus 3, and the I / F 23. Data is read from 22 and written to the memory 13 or vice versa. Then, when the transfer of the designated size data is completed, the DMA controller 12 notifies the CPU 11 of completion using an interrupt or the like.

  As described above, the DMA controller 12 is normally mounted on the host system 1, reads data from the storage system 2 connected by the common bus 3, writes the data to the memory 13, and vice versa. Or

  Conventionally, a dedicated interface may be used as an interface between the host system 1 and the storage system 2.

  In addition, a high-speed bus called PCI (Peripheral Components Interconnect) Express has been widely put into practical use (see Non-Patent Document 1).

JP 2004-46891 A

“PCI SIG-PCI Express”, [Search June 23, 2006], Internet, <URL: http://www.pcisig.com/specifications/pciexpress/>

  As described above, there are two types of DMA transfer: using descriptors and writing transfer information directly to registers without using descriptors. Has been made.

  For example, in a storage system such as removable silicon storage, the system configuration of the host device to be connected can take various forms, so the memory for data transfer may be allocated to a fixed area. May be dynamically allocated by the operating system. As described above, if the memory that performs data transfer is dynamically allocated, it is preferable to use a descriptor. On the other hand, if the memory that performs data transfer is allocated to a fixed area, it is It is easier to control the writing of the transfer information directly in the register than the transfer using the child because it is not necessary to prepare the descriptor on the device side.

  As described above, in the storage system, the transfer method to be taken differs depending on the system configuration of the host device to be connected. However, the conventional storage system basically has only one type of command set. For this reason, there may be a difference in data transfer performance depending on the connected host device.

  As described above, with the progress of practical use of high-speed buses such as PCI Express, it is required to increase the data transfer speed. Therefore, there has been a demand to prevent a difference in data transfer performance depending on the host device connected to.

  In addition, for example, in silicon storage such as a Flash memory card, it is required to hide the detailed control of DMA as described above from the user and provide an access method using a simpler command set. ing.

  For example, it is conceivable that the user performs an operation input depending on the host device of the connection destination and other conditions, and the CPU 11 performs all the detailed settings of the DMA controller 12, but in this case, the operation becomes complicated.

  The present invention has been made in view of such a situation, and makes it possible to perform data transfer in an appropriate data transfer mode without performing a complicated operation by a user.

  An information storage device according to a first aspect of the present invention analyzes a command supplied from an information processing device including a first storage unit and a second storage unit without request from others, and exchanges information. A first data transfer mode for directly specifying the physical address of the second storage means related to the data, and a second data transfer mode for indirectly specifying the physical address of the second storage means related to information exchange The command analysis means for determining which data transfer mode is selected, and the information of the first storage means and the second storage means based on the data transfer mode determined by the command analysis means Information transfer control means for controlling transfer.

  The second data transfer mode designates a physical address of the second storage unit in which a list composed of a plurality of descriptors including a physical address of the second storage unit involved in information exchange is stored. The data transfer mode can be set.

  The first data transfer mode further includes a physical address of the second storage means related to information exchange performed by the information processing device in the first register. The second data transfer mode is a data transfer mode in which the information processing apparatus sets a physical address of the second storage unit in which the list is stored in the second register. Can be.

  The first data transfer mode is used for exchanging information with the information processing apparatus in which a physical address space is continuously set in the second storage means, and the second data transfer mode is the second data transfer mode. The second storage means can be used for exchanging information with the information processing apparatus in which the physical address space is set discontinuously.

  The command set that can be analyzed by the command analysis means includes a first command set including a command adapted to the first data transfer mode, and a second command set including a command adapted to the second data transfer mode. Can be included.

  A part of the first command set and a part of the second command set may include different commands instructing the same processing.

  A part of the first command set and a part of the second command set may include the same command.

  In the information transfer method according to the first aspect of the present invention, the information storage device including the first storage unit analyzes the command supplied from the information processing device including the second storage unit without request from others. The first data transfer mode for directly specifying the physical address of the second storage means related to the exchange of information and the second address for indirectly specifying the physical address of the second storage means related to the exchange of information. A step of determining which one of the two data transfer modes, and controlling the exchange of information between the first storage unit and the second storage unit based on the determined data transfer mode including.

  The program according to the first aspect of the present invention analyzes a command supplied to a computer of an information storage device including a first storage unit without request from another information processing device including a second storage unit. The first data transfer mode for directly specifying the physical address of the second storage means related to the exchange of information and the second address for indirectly specifying the physical address of the second storage means related to the exchange of information. A step of determining which one of the two data transfer modes, and controlling the exchange of information between the first storage unit and the second storage unit based on the determined data transfer mode The process including is executed.

  In the first aspect of the present invention, a command supplied from an information processing apparatus including the second storage unit without being requested by another is analyzed, and the physicality of the second storage unit involved in the exchange of information is analyzed. Which data transfer mode is a first data transfer mode in which an address is directly specified and a second data transfer mode in which a physical address of the second storage means related to information exchange is indirectly specified Based on the determined data transfer mode, transfer of information between the first storage unit and the second storage unit is controlled.

  An information transfer system according to a second aspect of the present invention includes an information storage device and an information processing device that exchanges information with the information storage device. The information storage device includes a first storage unit and the information storage device. A first data transfer mode for analyzing a command supplied from a processing device without request from others, and directly specifying a physical address of a second storage means of the information processing device involved in information transmission and reception; and A command analysis unit that determines which data transfer mode is the second data transfer mode that indirectly specifies a physical address of the second storage unit related to the exchange of information, and the command analysis unit And an information transmission / reception control unit that controls transmission / reception of information between the first storage unit and the second storage unit based on the data transfer mode. Comprising a second storage unit, and a command sending means for sending a command to adapt to any of the data transfer mode of said first data transfer mode and the second data transfer mode in the information storage device.

  In the second aspect of the present invention, the information storage device including the first storage device analyzes a command supplied from the information processing device without request from others, and performs the information processing related to the exchange of information. A first data transfer mode in which the physical address of the second storage means of the apparatus is directly specified, and a second data transfer mode in which the physical address of the second storage means related to information exchange is indirectly specified It is determined which data transfer mode, and based on the determined data transfer mode, information exchange between the first storage unit and the second storage unit is controlled, and the second storage unit is controlled. An information processing apparatus comprising a device, wherein the transfer mode is one of commands that are suitable for one of the first data transfer mode and the second data transfer mode. It said command to accommodate is sent to the information storage device.

  An information processing apparatus according to a third aspect of the present invention includes a first data transfer mode for directly specifying a physical address of the first storage unit, the first storage unit involved in information transfer, and information transfer An information storage device comprising a second storage means for a command adapted to any one of the second data transfer modes for indirectly specifying the physical address of the first storage means related to Then, based on the data transfer mode indicated by the command, the information is transmitted to the information storage device that controls the exchange of information between the first storage means and the second storage means without request from others. Command sending means.

  The second data transfer mode designates a physical address of the first storage means in which a list composed of a plurality of descriptors including a physical address of the first storage means related to information exchange is stored. The data transfer mode can be set.

  The first data transfer mode is a data transfer mode in which the information processing apparatus sets a physical address of the first storage means related to information exchange in a register of the information storage apparatus, and the second data transfer mode The mode may be a data transfer mode in which the information processing apparatus sets a physical address of the first storage unit in which the list is stored in a register of the information storage apparatus.

  The first data transfer mode is used when a physical address space is set continuously in the first storage means, and the second data transfer mode is used in a physical address space in the first storage means. Can be used when is set discontinuously.

  An information transfer method according to a third aspect of the present invention includes a first data transfer mode in which an information processing apparatus including a first storage unit directly specifies a physical address of the first storage unit related to information exchange, And a second storage means for a command adapted to one of the data transfer modes of the second data transfer mode for indirectly specifying the physical address of the first storage means involved in the exchange of information. An information storage device that responds to a request from another to the information storage device that controls transmission / reception of information between the first storage unit and the second storage unit based on the data transfer mode indicated by the command It includes the step of sending without relying on.

  A program according to a third aspect of the present invention includes a first data transfer mode for directly specifying a physical address of the first storage unit involved in information transfer to a computer of an information processing apparatus including the first storage unit, And a second storage means for a command adapted to one of the data transfer modes of the second data transfer mode for indirectly specifying the physical address of the first storage means involved in the exchange of information. An information storage device that responds to a request from another to the information storage device that controls transmission / reception of information between the first storage unit and the second storage unit based on the data transfer mode indicated by the command The processing including the step of sending without depending on is executed.

  In the third aspect of the present invention, the first data transfer mode for directly specifying the physical address of the first storage means involved in the exchange of information, and the physical address of the first storage means involved in the exchange of information A command adapted to any one of the second data transfer modes for indirectly designating is an information storage device comprising a second storage means, and the data transfer mode indicated by the command The information is sent to the information storage device that controls transmission / reception of information between the first storage means and the second storage means without any other request.

  As described above, according to the first to third aspects of the present invention, it is possible to exchange information with a host device. In particular, the same storage device can be applied to different types of transfer modes. Can exchange information with the device.

It is a figure for demonstrating the case where a physical address space is not continuous. It is a figure for demonstrating the case where the physical address space is continuing. It is a block diagram which shows the conventional host system and storage system. It is a block diagram which shows the host system and storage system to which this invention is applied. It is a functional block diagram which shows the function which a controller has. It is a figure for demonstrating the example of a 1st command set. It is a figure for demonstrating a descriptor. It is a figure for demonstrating the example of a 2nd command set. It is a figure for demonstrating the example of data transfer information. It is a figure for demonstrating the example of the command used similarly in the host system using a link list transfer mode, and also in the host system using a direct transfer mode. A command set recognizable by the storage system, a command set recognizable by the first host system whose physical address space is not continuous, and a command recognizable by the second host system 62 whose physical address space is continuous It is a figure for demonstrating a set. It is a flowchart for demonstrating the process of a storage system. It is a flowchart for demonstrating the process of a host system and a storage system. It is a flowchart for demonstrating the process of a host system and a storage system.

  Embodiments to which the present invention is applied will be described below with reference to the drawings.

  FIG. 4 is a block diagram showing a configuration of a storage system and a host system to which the present invention is applied.

  The storage system 61 and the host system 62 are connected by a storage I / F 63. For the storage I / F 63, for example, a high-speed bus such as PCI (Peripheral Components Interconnect) Express is preferably used.

  The storage system 61 includes a controller 81, an internal bus 82, a register 83, a DMA controller 84, a buffer memory 85, a storage I / F bus 86, a storage memory controller 87, storage memories 88-1 to 88-n, and a drive 89. Consists of including.

  The controller 81 controls the operation of the storage system 61. For example, the controller 81 controls the storage memory controller 87 to write or read data to or from the storage memories 88-1 to 88-n, or to the host system. Based on the command supplied from 62 and written in one of the registers 83, processing such as setting of the DMA controller 84 is executed.

  A controller 81, a register 83, a DMA controller 84, and a buffer memory 85 are connected to the internal bus 82, and a drive 89 is also connected as necessary.

  The register 83 can include a plurality of registers, and commands, descriptors, transfer processes, and other processes supplied from the host system 62 via the storage I / F 63 and the storage I / F bus 86 from the host system 62. Holds information and arguments necessary for.

  The DMA controller 84 controls data exchange between the buffer memory 85 of the storage system 61 and the host memory 92 of the host system 62. The DMA controller 84 has two operation modes and is set by the controller 81.

  In the first transfer mode, the address of a link list constituted by a plurality of descriptors (also referred to as entries) is supplied from the host system 62 to the register 83 of the storage system 61, and the storage system 61 receives this link list. This is a link list transfer mode in which transfer processing is executed by reading the data, and the second transfer mode has information related to data transfer directly from the host system 62 to the register 83 of the storage system 61 without using a link list. Direct transfer mode described.

  In the link list transfer mode, as described with reference to FIG. 1, when the physical address space in the host memory 92 of the host system 62 is managed for each page, that is, it is not continuous like the logical address space. It is preferable to use it when the values are set differently. On the other hand, as described with reference to FIG. 2, when the physical address space in the host memory 92 of the host system 62 is set continuously like the logical address space, the control is simple. Direct transfer mode can be used.

  The buffer memory 85 temporarily buffers the data supplied from the host system 62 via the storage I / F 63 and the storage I / F bus 86, and controls the storage memories 88-1 to 88- under the control of the storage memory controller 87. The data read from any one of n and supplied to the host system 62 via the storage I / F 63 and the storage I / F bus 86 is temporarily buffered.

  The storage I / F bus 86 is a bus that connects the register 83, the DMA controller 84, the buffer memory 85, and the storage I / F.

  The storage memory controller 87 controls the writing and reading of data to and from the storage memories 88-1 to 88-n based on the control of the controller 81.

  Data is written to and read from the storage memories 88-1 to 88-n by the storage memory controller 87.

  In the following description, the storage memories 88-1 to 88-n are simply referred to as the storage memory 88 when it is not necessary to distinguish them individually.

  Further, the drive 89 is connected to the internal bus 82 as necessary. For example, when a removable medium 101 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is mounted, the drive 89 drives them and acquires programs and data recorded therein. The acquired program and data are transferred to the stream memory 88 and recorded or installed in the controller 81.

  The host system 62 includes a host CPU 91 and a host memory 92. Note that the host system 62 may be configured to include other components such as a communication unit, a display unit, an operation input unit, an imaging unit, a sound acquisition unit, or a data compression processing unit, for example. Needless to say. As the host system 62, for example, various information processing apparatuses such as a general personal computer, a digital still camera, and a digital video camera can be used.

  The host CPU 91 controls the operation of the host system 62. For example, the data stored in the host memory 92 is stored in the storage system 61 based on a user operation input input by an operation input unit (not shown). Commands related to data exchange with the storage system 61, such as commands for writing to the memory 88, commands for reading data stored in the storage memory 88 of the storage system 61 and storing them in the host memory 92, or In addition to this, for example, a command for controlling the storage memory 88 such as an instruction to erase data stored in the storage memory 88 is generated, and the register 83 of the storage system 61 is transmitted via the storage I / F 63. Process to write to Can be done.

  The host memory 92 stores predetermined data based on the control of the host CPU 91.

  As described above, in the configuration of the storage system 61 and the host system 62 shown in FIG. 4, unlike the conventional case, a DMA controller for controlling DMA transfer is provided not on the host side but on the storage side.

  Here, as described with reference to FIG. 1, the physical address space in the host memory 92 of the host system 62 is not continuous as the logical address space in the storage format of the data in the host memory 92, and is separated. As described with reference to FIG. 2 and the first data storage format set in the above, the physical address space in the host memory 92 of the host system 62 is set continuously in the same manner as the logical address space. A description will be given on the assumption that there are two types of data storage formats: a data storage format. In other words, the host system 62 is different from the logical address space in the host memory 92. The host system 62 includes a first host system 62 configured by a plurality of areas that are not continuous (separated), and a host In the memory 92, there is a second host system 62 in which both the physical address space and the logical address space are continuous.

  That is, the link list transfer mode described above is executed in the first host system 62, and the direct transfer mode described above is executed in the second host system 62 to transfer data with the storage system 61. It is made to be able to. Note that the command set of the first host system 62 that executes the link list transfer mode and the command set of the second host system 62 that executes the direct transfer mode differ at least in commands related to data transfer. . Details of the command set will be described later.

  Next, operations of the storage system 61 and the host system 62 will be described.

  For example, when a process of writing data recorded in the host memory 92 of the host system 62 to the storage memory 88 of the storage system 61 is executed, the host CPU 91 of the host system 62 uses the storage I / F 63 and the storage I / F. A write command, which is a command for instructing processing for writing data recorded in the host memory 92 of the host system 62 to the storage memory 88, is transmitted to the register 83 via the bus 86. The register 83 receives the command and temporarily holds it.

  The controller 81 of the storage system 61 acquires the command held in the register 83 and interprets its contents. As described above, in the storage system 61 and the host system 62, the data transfer is executed using one of the link list transfer mode and the direct transfer mode. And setting based on the transfer mode.

  That is, when the data transfer mode is the link list transfer mode, the host CPU 91 of the host system 62 writes the address in which the link list is written in the host memory 92 to the register 83. The entry is read from the host memory 92 one entry at a time, data transfer processing is executed based on the read entry, and data transfer processing is executed in the same manner for all entries in the link list. When the data transfer mode is the direct transfer mode, the host CPU 91 of the host system 62 directly writes the data transfer information such as the data size and address in the register 83. Therefore, the DMA controller 83 refers to the register 83, Execute data transfer processing.

  That is, when data is written from the host system 62 to the storage system 61, the DMA controller 84 reads data written in the storage memory 88 among data recorded in the host memory 92, and stores the storage I / F 63 and storage I / F 63. The data is supplied to the buffer memory 85 via the / F bus 86 and buffered.

  The data stored in the buffer memory 85 is written into the storage memory 88 by the storage memory controller 87 starting from the time when the contents of the data stored in the buffer memory 85 become valid.

  Further, for example, when the process of reading the data recorded in the storage memory 88 of the storage system 61 and storing it in the host memory 92 of the host system 62 is executed, the host CPU 91 of the host system 62 uses the storage I / F 63. A write command for instructing to read data recorded in the storage memory 88 of the storage system 61 is transmitted to the register 83 via the storage I / F bus 86. The register 83 receives the command and temporarily holds it.

  The controller 81 of the storage system 61 acquires the command held in the register 83 and interprets its contents. As described above, in the storage system 61 and the host system 62, the data transfer is executed using one of the link list transfer mode and the direct transfer mode. And setting based on the transfer mode.

  When the host system 62 reads data from the storage system 61, the controller 81 controls the storage memory controller 87 to transfer the read data from the storage memory 88 to the buffer memory 85. The data stored in the buffer memory 85 is started by the DMA controller 84 via the storage I / F bus 86 and the storage I / F from the time when the contents of the data stored in the buffer memory 85 become valid. Transferred to the host memory 92.

  FIG. 5 is a functional block diagram showing functions of the controller 81 of the storage system 61.

  The command acquisition unit 141 acquires the command supplied from the host system 62 stored in the register 83 and supplies the command to the command analysis unit 142.

  The command analysis unit 142 analyzes the command acquired by the command acquisition unit 141.

  The DMA controller setting processing unit 143 sets the DMA controller 84 to either the link list transfer mode or the direct transfer mode based on the command analysis result by the command analysis unit 142.

  As described above, the DMA controller 84 of the storage system 61 has two transfer modes: a link list transfer mode and a direct transfer mode.

  That is, the command analysis unit 142 of the controller 81 recognizes two types of command sets that the host system 62 transmits to the storage system 61, and the DMA controller 143 corresponds to the command set and the DMA controller 84 uses the link list. It is possible to set whether to operate in transfer mode or direct transfer mode.

  Then, the command execution unit 144 controls execution of processing according to the command based on the command analysis result by the command analysis unit 142.

  As described with reference to FIG. 1, the physical address space of the host memory 92 is different from the logical address space, and the data included in the first host system 62 composed of a plurality of areas that are not continuous (dissociated). An example of a first command set related to transfer is shown in FIG.

  The READ_DATA_LINKLIST command is a command for instructing to continuously read data of a specified size from a specified address in the link list transfer mode.

  The WRITE_DATA_LINKLIST command is a command for instructing to continuously write data of a specified size from a specified address in the link list transfer mode.

  In the link list transfer mode, a link list using a plurality of descriptors in the format shown in FIG. 7 is used to write data into or read data from the discrete physical address space. Individual descriptors constituting this linked list are also referred to as entries.

  One entry is configured to include at least transfer address, transfer size, and transfer control information (EOT) indicating whether it is the final entry of the list structure. In the link list transfer mode, which is a transfer mode using a link list, the host system 62 sets the head address where the link list of the host memory 92 is stored in the register 83 of the storage system 61. The DMA controller 84 reads the first entry from the host memory 92 according to this setting. Based on the transfer information described in this entry, the DMA controller 84 can perform necessary transfer. When the transfer using the first entry is completed, the DMA controller 84 automatically acquires the next entry from the link list and performs the transfer in the same manner. The DMA controller 84 refers to the EOT flag of the transfer control information in the entry, determines whether or not this entry is the last entry, and repeats this operation until the last entry.

  The link list transfer mode is used when transferring to a discontinuous physical address space as described with reference to FIG. That is, it is suitable for the case where the physical address space in the host memory 92 of the host system 62 is not continuous as in the logical address space as in FIG. It is. In other words, when the physical address space in the host memory 92 of the host system 62 is not continuous as in the logical address space as in the case of FIG. 1 described above, The command set relating to data transfer that the system 62 has is only that shown in FIG. 6, and does not need to have the command set of FIG. 8 described later.

  Next, as described with reference to FIG. 2, an example of a first command set related to data transfer included in the second host system 62 in which the physical address space of the host memory 92 is continuous in the same manner as the logical address space. As shown in FIG.

  The READ_DATA_DIRECT command is a command for instructing to continuously read data of a specified size from a specified address in the direct transfer mode.

  The WRITE_DATA_DIRECT command is a command for instructing to continuously write data of a specified size from a specified address in the direct transfer mode.

  In the direct transfer mode, data transfer information is directly set in the register 83 from the host CPU 91 via the storage I / F 63.

  As shown in FIG. 9, the data transfer information set directly in the register 83 is configured to include information basically equivalent to the descriptor as the data transfer information, that is, a transfer address and a transfer size. Since the data transfer information is supplied from the host CPU 91 to the register 83 via the storage I / F 63, the DMA controller 84 performs data transfer based on the set information. When the host system 62 further has data to be exchanged with the storage system 61, the host system 62 further generates a READ_DATA_DIRECT command or a WRITE_DATA_DIRECT command, notifies the storage system 61 of the next transfer information, and Execute the transfer process.

  The direct transfer mode is used when transferring to a continuous physical address space as described with reference to FIG. That is, it is suitable for the case where the physical address space in the host memory 92 of the host system 62 is set continuously like the logical address space as in FIG. In other words, when the physical address space in the host memory 92 of the host system 62 is set continuously as in the case of FIG. 2 described above, the command set related to data transfer that the host system 62 has is shown in FIG. It is not necessary to have the command set shown in FIG.

  Further, as described with reference to FIG. 1, the physical address space in the host memory 92 of the host system 62 is not continuous as in the logical address space, but is set differently, or FIG. As described with reference to FIG. 5, the command that instructs the processing to perform the same processing in any case where the processing is continuously set as in the logical address space, the link list transfer mode is set in the data transfer mode. The same command can be issued also in the host system 62 that uses the direct transfer mode as the data transfer mode.

  For example, as shown in FIG. 10, an ERASE command for erasing data of a specified size from a specified address, a CHECK_ERASED command for checking the erased state of data of a specified size from a specified address, and a BLANK command for initializing May be the same command regardless of the state of the host memory 92 of the host system 62.

  Referring to FIG. 11, the first host system configured by a command set recognizable by storage system 61 and a plurality of non-contiguous (separated) areas different from logical address space in physical address space. A command set that can be recognized by the second host system 62 in which both the physical address space and the logical address space are continuous will be described.

  Unlike the logical address space, the first command set that can be recognized by the first host system 62 composed of a plurality of non-contiguous (separated) areas is different from the logical address space. These commands are READ_DATA_LINKLIST, WRITE_DATA_LINKLIST, ERASE, CHECK_ERASED, and BLANK. A second command set that can be recognized by the second host system 62 in which both the physical address space and the logical address space are continuous is READ_DATA_DIRECT, WRITE_DATA_DIRECT, ERASE, and CHECK_ERASED indicated by B in FIG. And BLANK commands. On the other hand, the command set that can be recognized by the storage system 61 includes a first command set indicated by C and a second command set indicated by B in FIG. Command set. That is, commands that can be recognized by the storage system 61 are READ_DATA_LINKLIST, WRITE_DATA_LINKLIST, ERASE, READ_DATA_DIRECT, WRITE_DATA_DIRECT, CHECK_ERASED, and BLANK commands.

  In other words, the command set that can be recognized by the storage system 61 is recognized by the first host system 62 composed of a plurality of non-contiguous (separated) areas unlike the logical address space in the physical address space. It can be said that there are two types of command sets: a first command set that can be recognized, and a second command set that can be recognized by the second host system 62 in which both the physical address space and the logical address space are continuous.

  Here, two types of commands, ie, read and write, are defined, but in each command set, that is, the first command set that can be recognized by the first host system 62 and the second host system 62. There is no limit to the number of instructions defined by the second command set that can be recognized. That is, the number of instructions defined in each command set may be one or plural.

  Next, processing of the storage system 61 will be described with reference to the flowchart of FIG.

  In step S <b> 1, the storage system 61 receives a command supplied from the host system 62 via the storage I / F 63. The supplied command is written into the register 83 via the storage I / F bus 86.

  In step S2, the command acquisition unit 141 of the controller 81 reads the command written in the register 83 via the internal bus 82, and the command analysis unit 142 of the controller 81 interprets the command.

  In step S <b> 3, the command analysis unit 142 of the controller 81 determines whether the command written in the register 83 is a command related to data transfer (write or read).

  If it is determined in step S3 that the command is not a command related to data transfer, that is, if the command described with reference to FIG. 10 has been written to the register, the command execution of the controller 81 is performed in step S4. The unit 144 executes a process corresponding to the command, and the process ends.

  If it is determined in step S3 that the command is a command related to data transfer, in step S5, the command analysis unit 142 of the controller 81 determines whether the command written in the register is based on the type of command. The transfer mode is determined based on whether the command is described with reference to FIG. 6 or the command described with reference to FIG. Specifically, when the command written in the register is the command described with reference to FIG. 6, the command analysis unit 142 determines that the data transfer mode is the link list transfer mode, and uses FIG. If it is the described command, it is determined that the data transfer mode is the direct transfer mode.

  In step S6, the DMA controller setting processing unit 143 of the controller 81 sets the DMA controller 84 according to the transfer mode.

  In step S7, the command execution unit 144 and the DMA controller 84 of the controller 81 execute a data transfer process. Detailed processing in the link list transfer mode or direct transfer mode will be described later with reference to FIGS. 13 and 14.

  In step S8, the command execution unit 144 of the controller 81 determines whether or not the transfer process has been completed. If it is determined in step S8 that the transfer process has not ended, the process returns to step S7, and the subsequent processes are repeated. If it is determined in step S8 that the transfer process has been completed, the process ends.

  By such processing, the controller 81 of the storage system 61 can determine the data transfer mode based on the command supplied from the host system 62 and set the DMA controller 84 according to the data transfer mode. The storage system 61 is a case where the format of the host memory 92 of the host system 62 is different from the physical address space and the physical address space as described with reference to FIG. Even (even in the case of the first host system 62 described above), as described with reference to FIG. 2, even if both the physical address space and the logical address space are continuous ( Data transfer processing can be executed correspondingly to each of the above-described second host systems 62). It is.

  Next, processing of the host system 62 and the storage system 61 in the link list transfer mode will be described with reference to the flowchart of FIG.

  In step S41, the host CPU 91 of the host system 62 transmits a data transfer start command (here, any of the commands described with reference to FIG. 6) to the storage system 61 via the storage I / F 63.

  In step S <b> 42, the storage system 61 receives a command supplied from the host system 62 via the storage I / F 63. The supplied command is written to the register 83 via the storage I / F bus 86.

  In step S43, the command acquisition unit 141 of the controller 81 reads the command written in the register 83 via the internal bus 82, and the command analysis unit 142 of the controller 81 interprets the command.

  In step S44, the command analysis unit 142 of the controller 81 determines whether the command written in the register is the command described with reference to FIG. 6 based on the type of command, or with reference to FIG. The transfer mode is determined based on whether the command is described. Here, since the command written in the register is the command described with reference to FIG. 6, the command analysis unit 142 will be described as determining that the data transfer mode is the link list transfer mode.

  In step S45, the DMA controller setting processing unit 143 of the controller 81 sets the DMA controller 84 as the link list transfer mode.

  In step S46, the DMA controller 84 set in the link list transfer mode requests the host system 62 for one entry in the link list via the storage I / F 63.

  In step S 47, the host CPU 91 of the host system 62 receives a request for one entry in the link list and transmits one entry in the link list to the storage system 61 via the storage I / F 63.

  In step S <b> 48, the storage system 61 acquires an entry from the host system 62 via the storage I / F 63 and holds it in the register 83.

  In steps S49 and S50, the storage system 61 and the host system 62 execute a data transfer process.

  Specifically, since the host CPU 91 of the host system 62 writes the address described in the link list in the host memory 92 to the register 83, the DMA controller 83 refers to the register 83 and makes one entry from the host memory 92. The entries are read one by one, the data transfer process is executed based on the read entries, and the data transfer process is similarly executed for all the entries in the link list.

  For example, when data is written from the host system 62 to the storage system 61, the DMA controller 84 reads the data written in the storage memory 88 among the data recorded in the host memory 92, and the storage I / F 63 and the storage I The data is supplied to the buffer memory 85 via the / F bus 86 and buffered.

  The data stored in the buffer memory 85 is written into the storage memory 88 by the storage memory controller 87 starting from the time when the contents of the data stored in the buffer memory 85 become valid.

  In step S51, the command execution unit 144 of the controller 81 of the storage system 61 determines whether or not EOT is described in the entry acquired in step S48. If it is determined in step S51 that EOT is not described, the process returns to step S46, and the subsequent processes are repeated.

  If it is determined in step S51 that EOT has not been described, the command execution unit 144 of the controller 81 ends the process in step S52.

  By such processing, data transfer is executed in the link list transfer mode.

  Next, processing of the host system 62 and the storage system 61 in the direct transfer mode will be described with reference to the flowchart of FIG.

  In step S <b> 71, the host CPU 91 of the host system 62 transmits a data transfer start command (here, any command described with reference to FIG. 8) to the storage system 61 via the storage I / F 63.

  In step S72, the storage system 61 receives a command from the host system 62 via the storage I / F 63. The supplied command is written to the register 83 via the storage I / F bus 86.

  In step S73, the command acquisition unit 141 of the controller 81 reads the command written in the register 83 via the internal bus 82, and the command analysis unit 142 of the controller 81 interprets the command.

  In step S74, the command analysis unit 142 of the controller 81 determines whether the command written in the register is the command described with reference to FIG. 6 based on the type of command, or with reference to FIG. The transfer mode is determined based on whether the command is described. Here, since the command written in the register is the command described with reference to FIG. 8, the command analysis unit 142 will be described as determining that the data transfer mode is the direct transfer mode.

  In step S75, the DMA controller setting processing unit 143 of the controller 81 sets the DMA controller 84 as the direct transfer mode.

  In step S76, the host CPU 91 of the host system 62 transmits information related to transfer processing, such as the size and address of data to be transferred, to the storage system 61 via the storage I / F 63.

  In step S 77, the storage system 61 acquires information related to transfer processing from the host system 62 via the storage I / F 63 and holds it in the register 83.

  In steps S78 and S79, the storage system 61 and the host system 62 execute a data transfer process.

  Specifically, when the data transfer mode is the direct transfer mode, the host CPU 91 of the host system 62 directly writes data transfer information such as the data size and address in the register 83, so the DMA controller 83 sets the register 83 in the register 83. Refer to and execute the data transfer process.

  For example, when the host system 62 reads data from the storage system 61, the controller 81 causes the storage memory controller 87 to transfer the read data from the storage memory 88 to the buffer memory 85. The data stored in the buffer memory 85 is started by the DMA controller 84 via the storage I / F bus 86 and the storage I / F from the time when the contents of the data stored in the buffer memory 85 become valid. Transferred to the host memory 92.

  In step S80, the command execution unit 144 of the controller 81 of the storage system 61 ends the process.

  By such processing, data transfer is executed in the direct transfer mode.

  As explained above, the storage system has both link list transfer mode and direct transfer mode transfer methods, and two simple command sets to properly use them are prepared. Since data can be exchanged with a host system that has such a command set, appropriate data transfer can be performed regardless of the system configuration of the connected host device, and data transfer performance can be improved. (Throughput can be improved).

  Further, by adopting such a configuration, data transfer can be realized by using a widely used high-speed bus such as PCI Express without using a dedicated interface.

  Although the case where data transfer is executed in one of the two transfer modes has been described here, for example, three or more transfer modes are prepared in advance depending on the configuration and conditions of the master system. The present invention can also be applied to the case where data transfer is executed in such a transfer mode.

  The series of processes described above can also be executed by software. The software is a computer in which the program constituting the software is incorporated in dedicated hardware, or various functions can be executed by installing various programs, for example, a general-purpose personal computer For example, it is installed from a recording medium.

  As shown in FIG. 4, the recording medium is distributed to provide a program to the user separately from the computer, and includes a magnetic disk (including a flexible disk) on which the program is recorded, an optical disk (CD-ROM ( Removable media 101 including a compact disk-read only memory (DVD) (including digital versatile disk), a magneto-optical disk (including MD (mini-disk) (trademark)), or a semiconductor memory.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

  In the present specification, the term “system” represents the entire apparatus constituted by a plurality of apparatuses.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

  1 Information processing system, 11 TV, 12 Remote controller, 13 Contactless card, 14 Payment server, 21 Internet, 41 Antenna, 42 Antenna, 43 Photovoltaic panel, 51 CPU, 52 Contactless card reader / writer, 53 Key input Unit, 55 wireless communication control unit, 56 output power measurement unit, 57 storage battery

Claims (18)

First storage means;
First data transfer for analyzing a command supplied from an information processing apparatus having second storage means without request from another and directly specifying a physical address of the second storage means related to information exchange Command analysis means for determining which data transfer mode is the second data transfer mode for indirectly specifying the mode and the physical address of the second storage means involved in the exchange of information;
An information storage device comprising: an information transfer control unit configured to control transfer of information between the first storage unit and the second storage unit based on the data transfer mode determined by the command analysis unit. The second data transfer mode designates a physical address of the second storage unit in which a list composed of a plurality of descriptors including a physical address of the second storage unit involved in information exchange is stored. The information storage device according to claim 1, wherein the information storage mode is a data transfer mode. A first register;
A second register; and
The first data transfer mode is a data transfer mode in which the information processing apparatus sets a physical address of the second storage means related to information exchange in the first register, and the second data transfer mode The information storage device according to claim 2, wherein the information processing device is a data transfer mode in which a physical address of the second storage unit in which the list is stored is set in the second register. The first data transfer mode is used for exchanging information with the information processing apparatus in which a physical address space is continuously set in the second storage means, and the second data transfer mode is the second data transfer mode. The information storage device according to claim 1, wherein the information storage device is used for exchanging information with the information processing device in which a physical address space is set discontinuously in the storage unit. The command set that can be analyzed by the command analysis means includes a first command set including a command adapted to the first data transfer mode, and a second command set including a command adapted to the second data transfer mode. The information storage device according to claim 1. The information storage device according to claim 5, wherein the command adapted to the first data transfer mode and the command adapted to the second data transfer mode include different commands instructing similar processing. The information storage device according to claim 5, wherein a part of the first command set and a part of the second command set include the same command. An information storage device comprising a first storage means
Analyzing a command supplied from an information processing apparatus including the second storage means without request from another,
A first data transfer mode for directly specifying the physical address of the second storage means involved in the exchange of information, and a second for indirectly specifying the physical address of the second storage means involved in the exchange of information. Determine which data transfer mode is the data transfer mode,
An information transfer method including a step of controlling exchange of information between the first storage means and the second storage means based on the determined data transfer mode. In the computer of the information storage device comprising the first storage means,
Analyzing a command supplied from an information processing apparatus including the second storage means without request from another,
A first data transfer mode for directly specifying the physical address of the second storage means involved in the exchange of information, and a second for indirectly specifying the physical address of the second storage means involved in the exchange of information. Determine which data transfer mode is the data transfer mode,
A program for executing processing including a step of controlling transmission / reception of information between the first storage means and the second storage means based on the determined data transfer mode.   A computer-readable recording medium on which the program according to claim 9 is recorded. An information storage device;
The information storage device and an information processing device that exchanges information,
The information storage device includes:
First storage means;
A first data transfer mode for analyzing a command supplied from the information processing apparatus without request from others and directly specifying a physical address of a second storage unit of the information processing apparatus involved in information transmission and reception; And command analysis means for determining which data transfer mode is the second data transfer mode for indirectly specifying the physical address of the second storage means related to the exchange of information;
Information transfer control means for controlling transfer of information between the first storage means and the second storage means based on the data transfer mode determined by the command analysis means;
The information processing apparatus includes:
The second storage means;
An information transfer system comprising: command sending means for sending a command adapted to any one of the first data transfer mode and the second data transfer mode to the information storage device. First storage means;
A first data transfer mode for directly designating a physical address of the first storage means involved in the exchange of information, and a second for indirectly designating a physical address of the first storage means involved in the exchange of information A command adapted to any one of the data transfer modes is an information storage device comprising a second storage means, wherein the first storage is based on the data transfer mode indicated by the command. An information processing apparatus comprising: command sending means for sending information to and from the information storage device that controls transmission / reception of information between the second storage means and a request from others. The second data transfer mode designates a physical address of the first storage means in which a list composed of a plurality of descriptors including a physical address of the first storage means related to information exchange is stored. The information processing apparatus according to claim 12, wherein the information processing mode is a data transfer mode. The first data transfer mode is a data transfer mode in which the information processing apparatus sets a physical address of the first storage means related to information exchange in a register of the information storage apparatus, and the second data transfer mode The information processing apparatus according to claim 13, wherein the mode is a data transfer mode in which the information processing apparatus sets a physical address of the first storage unit in which the list is stored in a register of the information storage apparatus. The first data transfer mode is used when a physical address space is set continuously in the first storage means, and the second data transfer mode is used in a physical address space in the first storage means. The information processing apparatus according to claim 12, wherein the information processing apparatus is used when is set discontinuously. An information processing apparatus comprising a first storage means
A first data transfer mode for directly designating a physical address of the first storage means involved in the exchange of information, and a second for indirectly designating a physical address of the first storage means involved in the exchange of information A command adapted to any one of the data transfer modes is an information storage device comprising a second storage means, wherein the first storage is based on the data transfer mode indicated by the command. An information transfer method comprising a step of sending the information to the information storage device that controls transmission / reception of information between the second storage means and the second storage means without request from others. In the computer of the information processing apparatus comprising the first storage means,
A first data transfer mode for directly designating a physical address of the first storage means involved in the exchange of information, and a second for indirectly designating a physical address of the first storage means involved in the exchange of information A command adapted to any one of the data transfer modes is an information storage device comprising a second storage means, wherein the first storage is based on the data transfer mode indicated by the command. A program for executing a process including a step of sending to an information storage device that controls transmission / reception of information between the means and the second storage means without request from others.   The computer-readable recording medium which recorded the program of Claim 17.

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