JP2011096691A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device having a semiconductor layer epitaxially grown in a trench is provided.
A step of forming a silicon nitride film 31 on a main surface of a silicon substrate 11, a step of forming an opening 31a in the silicon nitride film 31 to expose the main surface of the silicon substrate 11, and a silicon substrate through the opening 31a. 11 is formed, and a trench 33 is formed. A silicon single crystal layer is selectively epitaxially grown on the inner surface of the trench 33, and the trench 33 is filled with the silicon single crystal layer 35c.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A method of manufacturing a semiconductor device is known in which a trench is formed on the surface of a semiconductor substrate, a semiconductor layer is selectively epitaxially grown on the inner surface of the trench, and the trench is filled with the semiconductor layer (see, for example, Patent Document 1). .

  In this method of manufacturing a semiconductor device, a mask forming step of forming a mask pattern of a desired shape on the surface of the semiconductor substrate, and etching the semiconductor substrate surface exposed from the mask pattern to form a concave groove structure, An isotropic etching process that leaves a mask eaves on the groove structure, and an epitaxial growth process that selectively forms an epitaxial growth layer on the surface of the semiconductor substrate exposed in the groove structure using the mask eaves as a stopper. Yes. As a result, a gate portion of a buried gate type static induction transistor (SIT) is formed.

  However, since this method of manufacturing a semiconductor device uses a silicon oxide film as a mask, the halogen compound, which is a process gas, reacts with the silicon oxide film. Therefore, facets are formed in the semiconductor layer grown on the side surfaces of the trench in the vicinity of the silicon oxide film, and the lateral growth rate in the vicinity of the facet in the upper portion of the trench is larger than the lateral growth rate in the lower portion of the trench.

  As a result, there is a problem that the upper part of the trench is closed first and a cavity is generated inside the semiconductor layer. The probability that this cavity is generated increases as the aspect ratio of the trench increases.

JP-A-5-234901

  The present invention provides a method for manufacturing a semiconductor device having a semiconductor layer epitaxially grown in a trench.

  A method of manufacturing a semiconductor device of one embodiment of the present invention includes a step of forming a silicon nitride film on a main surface of a silicon substrate, a step of forming an opening in the silicon nitride film, and exposing the main surface of the silicon substrate; Etching the silicon substrate through the opening to form a trench; and epitaxially growing a silicon single crystal layer on the inner surface of the trench and filling the trench with the silicon single crystal layer. It is a feature.

  According to the present invention, a method for manufacturing a semiconductor device having a semiconductor layer epitaxially grown in a trench can be obtained.

Sectional drawing which shows the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows the principal part of the manufacturing process of the semiconductor device which concerns on the Example of this invention in order. Sectional drawing which shows the principal part of the manufacturing process of the semiconductor device which concerns on the Example of this invention in order. Sectional drawing which shows the principal part of the manufacturing process of the semiconductor device which concerns on the Example of this invention in order. Sectional drawing which shows the principal part of the manufacturing process of the semiconductor device of the comparative example which concerns on the Example of this invention in order. The figure which shows the epitaxial growth characteristic in the trench based on the Example of this invention in contrast with a comparative example. Sectional drawing which shows the principal part of another manufacturing process of the semiconductor device which concerns on the Example of this invention in order. Sectional drawing which shows another mask which concerns on the Example of this invention. Sectional drawing which shows another mask which concerns on the Example of this invention. Sectional drawing which shows another mask which concerns on the Example of this invention. Sectional drawing which shows another mask which concerns on the Example of this invention. Sectional drawing which shows another mask which concerns on the Example of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  A method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a semiconductor device according to the present embodiment, and FIGS. 2 to 4 are cross-sectional views sequentially showing a main part of a manufacturing process of the semiconductor device.

  This embodiment is an example of manufacturing a semiconductor device having a power MOS transistor called a super junction structure in which a current path and a region for maintaining a breakdown voltage are separated.

  First, a semiconductor device will be described. As shown in FIG. 1, in the semiconductor device 10 of this embodiment, n-type semiconductor pillar layers serving as current paths and p-type semiconductor pillar layers serving as current partition regions are alternately arranged in the horizontal direction to form p-type semiconductor pillar layers. An n-type source region and a gate electrode are formed in a p-type semiconductor base layer formed on the upper surface.

  Specifically, an n-type semiconductor pillar layer 12 having a length L, a p-type semiconductor pillar layer 13 adjacent to the n-type semiconductor pillar layer 12, and a p-type semiconductor pillar layer 13 on the main surface of the n-type silicon substrate 11. An n-type semiconductor pillar layer 14 is formed adjacent to. Each pillar layer is formed in a stripe shape, for example, in a direction perpendicular to the paper surface.

  A p-type semiconductor base layer 15 is formed on the upper surface of the p-type semiconductor pillar layer 13. An n-type semiconductor source region 16 is formed on the surface of the p-type semiconductor base layer 15 on the n-type semiconductor pillar layer 12 side, and an n-type semiconductor source region 17 is formed on the n-type semiconductor pillar layer 14 side.

  Gates are formed on the p-type semiconductor base layer 15 between the n-type semiconductor source region 16 and the n-type semiconductor pillar layer 12 and on the p-type semiconductor base layer 15 between the n-type semiconductor source region 17 and the n-type semiconductor pillar layer 14. An insulating film 18 is formed, and a gate electrode 19 is formed on the gate insulating film 18.

  The surfaces of the n-type semiconductor pillar layers 12 and 14 and the p-type semiconductor pillar layer 13 and the gate electrode 19 are protected by an interlayer insulating film 20. A source electrode 21 is formed on the interlayer insulating film 20.

  The source electrode 21 is connected to the n-type source regions 16 and 17 and the p-type semiconductor base layer 15 through the opening of the interlayer insulating film 20. A drain electrode 22 is formed on the surface opposite to the main surface of the n-type silicon substrate 11.

  In order to obtain a high breakdown voltage and a low on-resistance at the same time, a narrow and long pillar layer is advantageous. For example, in order to obtain a withstand voltage of 900 V and an on-resistance of 150 mΩ, the length L of the n-type semiconductor pillar layers 12 and 14 and the p-type semiconductor pillar layer 13 is desirably about 90 μm, for example. Further, the width Wn of the n-type semiconductor pillar layers 12 and 14 and the width Wp of the p-type semiconductor pillar layer 13 are substantially equal to each other, for example, about 10 μm is desirable.

  Here, in order to form the p-type semiconductor pillar layer 13, a deep trench is formed in the n-type silicon substrate 11, a p-type silicon single crystal layer is selectively epitaxially grown on the inner surface of the trench, and the trench is formed into p-type silicon. In the case of embedding with a single crystal layer, the upper portion of the trench is blocked first, and a hollow embedding defect may occur.

  In this embodiment, a p-type semiconductor pillar layer having a uniform withstand voltage is obtained by using a silicon nitride film having ridges as a mask to prevent the occurrence of hollow filling defects.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 2 to 4 are cross-sectional views sequentially showing the main part of the manufacturing process of the semiconductor device.

  First, as shown in FIG. 2A, a silicon nitride film 31 is formed on an n-type silicon substrate 11 to a thickness of about 400 nm by, for example, a plasma CVD (Chemical Vapor Deposition) method.

  Next, a resist film (not shown) having an opening narrower than the width Wp of the p-type semiconductor pillar layer 13 is formed on the silicon nitride film 31 by photolithography, and the resist film is used as a mask, for example, a fluorine-based film. An opening 31a having a width W is formed in the silicon nitride film 31 by RIE (Reactive Ion Etching) using a gas. Thereby, the surface of the n-type silicon substrate 11 is exposed.

  Next, after removing the resist film, as shown in FIG. 2B, anisotropic etching is performed through the opening 31a by the RIE method using, for example, chlorine / fluorine gas, using the silicon nitride film 31 as a mask. The groove 32 having a depth of about 90 μm is formed.

  Next, as shown in FIG. 2C, isotropic etching is performed by CDE (Chemical Dry Etching) using, for example, chlorine / fluorine gas, and the inner side surface of the groove 32 is retracted. As a result, a trench 33 having a width Wp is formed, and a ridge 34 of the silicon nitride film 31 left on the opening surface of the trench 33 is formed.

Next, a silicon single crystal is selectively epitaxially grown on the inner surface of the trench 33 using the silicon nitride film 31 having the ridges 34 as a mask. The selective epitaxial growth is performed at a temperature of 1050 ° C. using, for example, hydrogen (H ₂ ) as a carrier gas and a mixed gas of dichlorosilane (SiH ₂ Cl ₂ ) and hydrochloric acid (HCl) as a process gas. Diborane (B ₂ H ₆ ) is used as the P-type dopant gas.

3A to 3C show a process in which a silicon single crystal layer is selectively epitaxially grown on the inner surface of the trench 33.
First, as shown in FIG. 3A, a silicon single crystal layer is epitaxially grown on the bottom surface and both side surfaces of the trench 33 at a growth rate corresponding to the respective plane orientations. The growth rate is usually the fastest in the (100) plane, followed by the (110) plane and the (111) plane.

  For example, when the surface orientation of the n-type silicon substrate 11 is (100) and the surface orientation of the side surface of the trench 33 is (110), the silicon single crystal layer has a growth rate on the bottom surface larger than the growth rate on the side surface. It grows like a silicon single crystal layer 35a.

  At this time, since silicon atoms adhering to the silicon nitride film 31 are not etched by HCl, nucleation occurs on a part of the silicon nitride film 31, and a silicon polycrystal 36a is formed.

  Next, as shown in FIG. 3B, when the silicon single crystal layer grown on the side surface of the trench 33 exceeds the tip of the ridge 34, the silicon single crystal layer grows upward along the side surface of the ridge 34. Then, it grows like a silicon single crystal layer 35b.

  Next, as shown in FIG. 3C, the silicon single crystals grown from both side surfaces of the trench 33 are united, and the trench 33 is filled with the silicon single crystal layer without generating a cavity.

  Furthermore, in order to completely fill the trench 33 in the surface of the n-type silicon substrate 11, when the overgrowth is about 1 to 2 μm, the silicon single crystal layer grown above the silicon nitride film 31 grows in the lateral direction, The silicon nitride film 31 is also extended. As a result, the silicon single crystal layer has an overgrowth portion 37 and grows like a silicon single crystal layer 35c.

  During this time, the silicon polycrystal 36a grows like the silicon polycrystal 36c from the silicon polycrystal 36b, but does not particularly affect the epitaxial growth of the silicon single crystal in the trench 33.

  Next, as shown in FIG. 4A, for example, by a CMP (Chemical Mechanical Polishing) method, the silicon polycrystal 36c formed on the silicon nitride film 31 and the overgrown portion 37 are formed using the silicon nitride film 31 as a stopper. Remove.

  Next, as shown in FIG. 4B, the silicon nitride film 31 is removed by wet etching using, for example, hot phosphoric acid.

  Next, as shown in FIG. 4C, the n-type silicon substrate 11 is mirror polished to flatten the surface. Thereby, the p-type semiconductor pillar layer 13 is formed.

  Next, a p-type semiconductor base layer 15 is formed on the upper surface of the p-type semiconductor pillar layer 13 by a known method, and an n-type semiconductor source region 16 and an n-type semiconductor source region are formed on the surface of the p-type semiconductor base layer 15. 17 is formed.

  Next, a gate insulating film 18 is formed on the p-type semiconductor base layer 15, a gate electrode 19 is formed on the gate insulating film 18, and the surfaces of the n-type semiconductor pillar layers 12 and 14, the p-type semiconductor pillar layer 13 and The gate electrode 19 is protected by the interlayer insulating film 20.

  Next, the source electrode 21 is formed on the interlayer insulating film 20, and the drain electrode 22 is formed on the surface opposite to the main surface of the n-type silicon substrate 11. Thereby, the semiconductor device 10 shown in FIG. 1 is obtained.

  FIG. 5 is a cross-sectional view sequentially showing the main part of the manufacturing process of the semiconductor device of the comparative example. Here, the comparative example is a method of manufacturing a semiconductor device including a step of epitaxially growing a silicon single crystal layer on the inner surface of a trench using a silicon oxide film as a mask and filling the trench with the silicon single crystal layer.

  FIGS. 5A to 5C show a process in which a silicon single crystal layer is selectively epitaxially grown on the inner surface of the trench in the comparative example.

First, as shown in FIG. 5A, a silicon single crystal layer is epitaxially grown on the bottom surface and both side surfaces of the trench 33 at a growth rate corresponding to the respective plane orientations. Here, the silicon epitaxially grown by the reaction between the silicon oxide film 51 and the process gas SiH ₂ Cl ₂ reacts with the silicon oxide film 51 at the interface and is eaten. As a result, the growth rate of the upper part of the trench 33 is reduced, and a (111) facet 52a is generated.

  Since silicon atoms that have not adhered to the (111) plane flow downward, the silicon single crystal layer has a particularly high growth rate near the inflection point with respect to (110), like the silicon single crystal layer 53a. grow up.

  Next, as shown in FIG. 5B, a large amount of process gas is consumed in the vicinity of the inflection point at the upper part of the trench, so that the concentration of the process gas at the lower part of the trench is reduced. The single crystal layer grows like the silicon single crystal layer 53b.

Next, as shown in FIG. 5C, the silicon single crystal layer that has abnormally grown from both side surfaces of the trench 33 is united first to block the opening of the trench 33. Growing like a single crystal layer 53 c, a cavity 54 is formed in the trench 33.

  As a result, the trench 33 is prevented from being normally filled with the silicon single crystal layer, and the uniform p-type semiconductor pillar layer 13 cannot be obtained.

  FIG. 6 is a diagram showing the epitaxial growth characteristics in the trench in comparison with the comparative example, and shows the growth rate of the silicon single crystal layer in the depth direction of the trench. In FIG. 6, the solid line shows the epitaxial growth characteristics of the present example, and the white circle connected by the broken line shows the epitaxial growth characteristics of the comparative example.

  As shown in FIG. 6, in the comparative example, since the facets were formed, the growth rate of the silicon single crystal layer on the side surface of the trench having a depth of about 1 to 5 μm and a depth of about 0 to 5 μm was abnormal. It was confirmed that it was getting bigger.

  On the other hand, in this example, it was confirmed that the growth rate of the silicon single crystal layer on the side surface of the trench was substantially uniform, and no facet as in the comparative example was formed.

  When the depth of the trench was about 5 μm or more, the film thickness on the side surface of the trench showed substantially the same tendency in this example and the comparative example.

  As described above, in the method of manufacturing the semiconductor device of this embodiment, the silicon single crystal layer is selectively epitaxially grown in the trench 33 using the silicon nitride film 31 having the ridge 34 as a mask.

  As a result, since the silicon nitride film 31 does not react with HCl in the process gas, generation of a facet on the (111) plane is prevented during epitaxial growth, and the trench 33 can be filled with the silicon single crystal layer 35c without a cavity. Therefore, a method for manufacturing a semiconductor device having a semiconductor layer epitaxially grown in the trench can be obtained.

  In this example, the trench 32 is formed by anisotropic etching, the width of the trench 32 is expanded by isotropic etching, and the ridge 34 is left on the opening surface, so that the trench 33 is formed. It can also be formed. FIG. 7 is a cross-sectional view sequentially showing another manufacturing process.

  As shown in FIG. 7A, a silicon nitride film 61 having an opening 61 a having a width Wp is formed on the main surface of the silicon substrate 11.

  Next, as shown in FIG. 7B, isotropic etching is performed by the CDE method using the silicon nitride film 61 as a mask to form a shallow groove 62. At this time, an undercut occurs and a ridge 63 is formed.

  Next, as shown in FIG. 7C, anisotropic etching is performed by the RIE method to form a trench 64 having a width Wp.

  Using the silicon nitride film 61 having the ridges 63 as a mask, a silicon single crystal layer having no cavities can be embedded in the trench 64 as in FIGS. 3A to 3C.

Although the case where SiH ₂ Cl ₂ is used as the process gas has been described, even if silane (SiH), trichlorosilane (SiHCl ₃ ), silicon tetrachloride (SiCl ₄ ), or the like is used, a silicon single crystal having no cavity in the trench Layers can be embedded.

  Although the case where the silicon nitride film 31 has the ridge 34 has been described, the ridge may be omitted. In that case, the width of the opening 31a is set to the width Wp in advance. Thereby, the CDE process of isotropic etching becomes unnecessary.

  However, in the step shown in FIG. 3A, there is no stopper for suppressing the upward growth of the silicon single crystal layer 35a. Therefore, in the step shown in FIG. Further overhangs. However, in the process shown in FIG. 4A, there is no particular problem as long as it is within a removable range.

  Although the case where the surface orientation of the inner side surface of the trench 33 is (110) has been described, it may be the (001) plane. In that case, since it is equivalent to the plane orientation (100) of the n-type silicon substrate 11, there is an advantage that the growth rate of the silicon single crystal layer on the bottom surface and both side surfaces of the trench 33 becomes substantially uniform.

  Although the case where the mask is a single layer film of a silicon nitride film has been described, a multi-layer film of a silicon nitride film and a silicon oxide film may be used.

  In the case of a two-layer mask having a structure in which a silicon oxide film is laminated on a silicon nitride film, nucleation on the silicon nitride film does not occur in the steps shown in FIGS. There is an advantage that generation of the crystal bodies 36a, 36b, and 36c can be prevented.

  8 to 10 are views showing a two-layer mask having a structure in which a silicon oxide film is laminated on a silicon nitride film. FIGS. 8 and 9 are cross-sectional views showing cases having a ridge of a silicon nitride film. FIG. It is sectional drawing which shows the case where it does not have the ridge of a silicon nitride film.

  As shown in FIG. 8, in the two-layer mask 70, a silicon oxide film 71 having an opening 71a having the same width W as the opening 31a is stacked on the silicon nitride film 31 having the flange 34.

  As shown in FIG. 9, in the two-layer mask 72, a silicon oxide film 73 having an opening 73a having the same width Wp as the opening 61a is laminated on the silicon nitride film 61 having the flange 63.

  As shown in FIG. 10, in the two-layer mask 74, a silicon oxide film 76 having an opening 76a having a width W2 larger than the width Wp of the opening 75a is laminated on the silicon nitride film 75 having no wrinkles. When there is no wrinkle of the silicon nitride film 75 on the opening surface of the trench 77, the silicon single crystal grown along the side surface of the silicon nitride film 75 and the silicon oxide film 76 come into contact with each other to form a facet on the upper portion of the trench. In order to prevent this from happening, it is desirable that the side surface of the silicon oxide film 76 be made to recede from the side surface of the silicon nitride film 75.

  Further, when the mask is a three-layer mask having a structure in which a silicon nitride film is sandwiched between silicon oxide films, in the steps shown in FIGS. 2 (b), 2 (c), 7 (b), and 7 (c). There is an advantage that etching of the silicon nitride film can be prevented.

  This is because the silicon nitride film is etched to some extent when the trench is formed by the RIE method and the CDE method, so that there is a risk that the thickness of the silicon nitride film is reduced and the function as a mask cannot be performed. This is to prevent it.

  11 is a cross-sectional view showing a three-layer mask having a structure in which a silicon nitride film is sandwiched between silicon oxide films. FIG. 11A is a cross-sectional view showing a state when a trench is formed, and FIG. It is sectional drawing which shows the state before growing a silicon single crystal selectively on the inner surface of a trench.

  As shown in FIG. 11A, in the three-layer mask 80, a silicon oxide film 81 (first silicon oxide film) is formed on the n-type silicon substrate 11, and a silicon nitride film is formed on the silicon oxide film 81. 82 is formed, and a silicon oxide film 83 (second silicon oxide film) is formed on the silicon nitride film 82. Openings having a width W are formed concentrically in the silicon oxide film 81, the silicon nitride film 82 and the silicon oxide film 83.

  Using the mask 80, a trench 84 is formed by the RIE method and the CDE method, similarly to the steps shown in FIGS. 2B and 2C. The silicon oxide film 83 prevents the upper surface of the silicon nitride film 82 from being etched, and the silicon oxide film 81 prevents the lower surface of the flange 85 of the silicon nitride film 82 from being etched.

  Next, as shown in FIG. 11B, the silicon oxide film 81 and the silicon oxide film 83 are formed by wet etching using a solution containing hydrofluoric acid before the silicon single crystal is selectively grown on the inner surface of the trench 84. It is desirable that the gap 86 is formed by retreating from both side walls of the trench 84.

  This is to prevent the silicon single crystal from contacting the silicon oxide film 81 and forming facets when the silicon single crystal is selectively grown on the inner surface of the trench 84.

  Accordingly, the silicon nitride film 82 does not need to be thickened in anticipation of being reduced by etching, and the silicon nitride film 82 can be easily formed.

  The silicon oxide film 83 can be prevented from retreating in order to prevent the silicon polycrystal from growing on the exposed silicon nitride film 82.

  12 is a cross-sectional view showing another three-layer mask having a structure in which a silicon nitride film is sandwiched between silicon oxide films. FIG. 12A is a cross-sectional view showing a state when a trench is formed, and FIG. ) Is a cross-sectional view showing a state before a silicon single crystal is selectively grown on the inner surface of the trench.

  12 (a) and 12 (b) are the same as FIGS. 11 (a) and 11 (b), and the description thereof is omitted. However, using a mask 90, FIGS. 7 (b) and 7 (b) are used. Similar to the process shown in (c), the trench 94 is formed by the RIE method and the CDE method.

  The silicon oxide film 93 (second silicon oxide film) prevents the upper surface of the silicon nitride film 92 from being etched, and the silicon oxide film 91 (first silicon oxide film) serves as a flange 95 of the silicon nitride film 92. This prevents the lower surface of the substrate from being etched.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 n-type silicon substrate 12, 14 n-type semiconductor pillar layer 13 p-type semiconductor pillar layer 15 p-type semiconductor base layer 16, 17 n-type semiconductor source region 18 gate insulating film 19 gate electrode 20 interlayer insulating film 21 source electrode 22 Drain electrodes 31, 61, 75, 82, 92 Silicon nitride films 31a, 61b, 73a, 75a, 76a Openings 32, 62 Grooves 33, 64, 77, 84, 94 Trench 34, 63, 85, 95 庇 35a, 35b , 35c, 53a, 53b, 53c Silicon single crystal layers 36a, 36b, 36c Silicon polycrystalline body 37 Overgrowth portions 51, 71, 73, 76, 81, 83, 91, 93 Silicon oxide films 52a, 52b, 52c Facet 54 Cavity 70, 72, 74, 80, 90 Mask 86, 96 Gap

Claims (5)

Forming a silicon nitride film on the main surface of the silicon substrate;
Forming an opening in the silicon nitride film and exposing a main surface of the silicon substrate;
Etching the silicon substrate through the opening to form a trench;
Selectively epitaxially growing a silicon single crystal layer on the inner surface of the trench and filling the trench with the silicon single crystal layer;
A method for manufacturing a semiconductor device, comprising:   The step of forming the trench is performed by forming a groove by anisotropic etching, and then retreating the inner surface of the groove by isotropic etching, and the silicon nitride film is formed on the opening surface of the trench. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is left as a bag.   The step of forming the trench is performed by forming a groove by isotropic etching and then deepening the groove by anisotropic etching, and leaving the silicon nitride film as a trough on the opening surface of the trench. The method of manufacturing a semiconductor device according to claim 1.   Following the step of forming the silicon nitride film on the main surface of the silicon substrate, a silicon oxide film is formed on the silicon nitride film, and the opening is formed in the silicon nitride film and the silicon oxide film. A method for manufacturing a semiconductor device according to claim 1.   Forming a first silicon oxide film on the silicon substrate; forming the silicon nitride film on the first silicon oxide film; forming a second silicon oxide film on the silicon nitride film; 4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed on the silicon nitride film, the first oxide film, and the second silicon oxide film. 5.

Images