JP2011087036A - Output buffer circuit and regulator circuit using the same - Google Patents

Abstract

A conventional output buffer circuit may generate a through current.
The present invention provides a first transistor and a second transistor that are connected in series and output an output signal from a common node, and the first transistor is turned on in response to an input signal and a first detection signal. Alternatively, a first drive circuit that drives in a non-conductive state, a second drive circuit that drives the second transistor in a conductive state or a non-conductive state according to the input signal and the second detection signal, and In response to the input signal and the first detection signal, the voltage of the common node (LX) when the first transistor is changed from the conductive state to the non-conductive state is detected, and the second transistor is detected according to the detection result. An output buffer circuit including: a detection circuit that switches the second transistor from a non-conductive state to a conductive state in response to the detection signal.
[Selection] Figure 1

Description

  The present invention relates to an output buffer circuit and a regulator circuit using the same.

  As a conventional switching regulator circuit, a technique as disclosed in Patent Document 1 is disclosed. FIG. 3 shows a configuration of the switching regulator circuit 1 using the output buffer circuit disclosed in Patent Document 1. As shown in FIG. 3, the switching regulator circuit 1 includes an output buffer circuit OB1, a Schottky diode SD1, an inductor L1, and a capacitor C1. The output buffer circuit OB1 includes a driver circuit 10, a PMOS transistor MP1, and an NMOS transistor MN2.

  The PMOS transistor MP1 is connected between the power supply voltage terminal VDD and the node LX. The NMOS transistor MN2 is connected between the node LX and the ground voltage terminal GND. The PMOS transistor MP1 and the NMOS transistor MN2 are power MOS transistors and constitute the output stage of the switching regulator circuit 1. The PMOS transistor MP1 and the NMOS transistor MN2 are driven by gate signals PGATE and NGATE output from the driver circuit 10, respectively.

  Schottky diode SD1 is connected between node LX and ground voltage terminal GND. The Schottky diode SD1 is used so that the voltage of the node LX does not fall below the ground voltage GND (for example, about GND-0.3V).

  The inductor L1 has one terminal connected to the node LX and the other terminal connected to the output terminal of the switching regulator circuit 1. The capacitor C1 has one terminal connected to the output terminal of the switching regulator circuit 1, and the other connected to the ground voltage terminal GND. Inductor L1 and capacitor C1 function as a low-pass filter for the signal output to node LX.

  The driver circuit 10 includes inverter circuits IV11 to IV13 and IV21 to IV25, a buffer circuit B11, a Schmitt buffer circuit SB11 and SB21, a NAND circuit NAND11, an AND circuit AND21, and output terminals POUT and NOUT.

  The inverter circuit IV11 inputs a PWM signal to the input terminal, and outputs a PPWM signal obtained by inverting the phase of the PWM signal from the output terminal. The NAND circuit NAND11 inputs the PPWM signal to one input terminal, inputs the PDLY signal to the other input terminal, and outputs the calculation result to the node N11. The inverter circuit IV12 inputs the signal output to the node N11 to the input terminal, and outputs a phase inverted signal from the output terminal. The inverter circuit IV13 inputs the output signal from the inverter circuit IV12 to the input terminal, and outputs a signal whose phase is inverted from the output terminal to the output terminal POUT. Therefore, the gate signal PGATE having the same phase as the signal of the node N11, which is current buffered by the inverter circuits IV12 and IV13, is output from the output terminal POUT.

  On the other hand, the gate signal PGATE is input to the Schmitt buffer circuit SB11. The Schmitt buffer circuit SB11 is connected between the output terminal POUT and the node N12. The buffer circuit B11 buffers the signal output to the node N12 and outputs it as an NDLY signal.

  The inverter circuit IV21 inputs a PWM signal to an input terminal and outputs a signal obtained by inverting the PWM signal from an output terminal. The inverter circuit IV22 inputs the signal output from the inverter circuit IV21 to an input terminal, and outputs a signal obtained by inverting the phase from the output terminal as an NPWM signal. The AND circuit AND21 inputs the NPWM signal to one input terminal, inputs the NDLY signal to the other input terminal, and outputs the calculation result to the node N21. The inverter circuit IV23 inputs the signal output to the node N21 to the input terminal, and outputs a phase-inverted signal from the output terminal. The inverter circuit IV24 inputs the output signal from the inverter circuit IV23 to the input terminal, and outputs a signal whose phase is inverted from the output terminal to the output terminal NOUT. Therefore, the gate signal NGATE having the same phase as the signal of the node N21, which is current buffered by the inverter circuits IV23 and IV24, is output from the output terminal NOUT.

  On the other hand, the gate signal NGATE is input to the Schmitt buffer circuit SB21. The Schmitt buffer circuit SB21 is connected between the output terminal NOUT and the node N22. The inverter circuit IV25 inputs a signal output to the node N22 to the input terminal, and outputs a signal whose phase is inverted from the output terminal as a PDLY signal.

  FIG. 4 shows a timing chart showing the operation of the switching regulator circuit 1 as described above. FIG. 5 is a graph showing the input / output characteristics of the Schmitt buffer circuits SB11 and B21.

  First, as shown in FIG. 4, the PWM signal rises to a high level at time t1, and the PPWM signal also falls to a low level almost simultaneously. At this time, since the PDLY signal is at a high level, the NAND circuit NAND11 outputs a high level signal as a calculation result. Therefore, the high level gate signal PGATE is output from the output terminal POUT.

  Here, it is assumed that the inverter circuit IV13 that outputs the gate signal PGATE to the output terminal POUT has a capability of sufficiently driving the PMOS transistor MP1. However, the PMOS transistor MP1 is assumed to be in the off state at time t3 after the off time TPoff from the rise of the gate signal PGATE due to the influence of the gate capacitance and the like.

  On the other hand, when it is detected that the voltage level of the rising gate signal PGATE is equal to or higher than the threshold voltage VH shown in FIG. 5, the Schmitt buffer circuit SB11 outputs a high level signal. Then, it passes through the buffer circuit B11 and is input to the other input terminal of the AND circuit AND21 as a high-level NDLY signal at time t2.

  Since the NPWM signal input to one input terminal is already at the high level at time t1, when the above-described high level NDLY signal is input to the other input terminal, the AND circuit AND21 outputs the high level as the operation result. Output a signal. Therefore, the high level gate signal NGATE is output from the output terminal NOUT.

  Here, it is assumed that the inverter circuit IV24 that outputs the gate signal NGATE to the output terminal NOUT has a capability of sufficiently driving the NMOS transistor MN2. However, the NMOS transistor MN2 is turned on at time t4 after the on-time TNon from the rising edge of the gate signal NGATE due to the influence of the gate capacitance and the like.

  Next, as shown in FIG. 4, the PWM signal falls to the low level at time t5, and the NPWM signal also falls to the low level almost simultaneously. At this time, since the NDLY signal is at a high level, the AND circuit AND21 outputs a low level signal as a calculation result. Therefore, the low-level gate signal NGATE is output from the output terminal NOUT. The NMOS transistor MN2 is turned off at time t7, which is after the off time TNoff from the fall of the gate signal NGATE.

  On the other hand, when it is detected that the voltage level of the falling gate signal NGATE is lower than the threshold voltage VL shown in FIG. 5, the Schmitt buffer circuit SB21 outputs a low level signal. Then, it passes through the inverter circuit IV25 and is input to the other input terminal of the NAND circuit NAND11 as a high-level PDLY signal at time t6.

  Since the PPWM signal input to one input terminal is already at a high level at time t5, when the above-described high level PDLY signal is input to the other input terminal, the NAND circuit NAND11 outputs a low level signal as a calculation result. Is output. Therefore, the low level gate signal PGATE is output from the output terminal POUT. Then, the PMOS transistor MP1 is turned on at time t8 after the on-time TPon from the fall of the gate signal PGATE.

  As described above, the regulator circuit 1 exclusively controls on / off of the PMOS transistor MP1 and the NMOS transistor MN2 in the output stage by the operation of the driver circuit 10. That is, as described above, the gate signal PGATE is raised and then the gate signal NGATE is raised, or the gate signal NGATE is lowered and then the gate signal PGATE is lowered. Such control prevents the PMOS transistor MP1 and the NMOS transistor MN2 of the regulator circuit 1 from being turned on at the same time, thereby preventing the occurrence of a through current.

JP 2009-71613 A

  However, in the regulator circuit 1, depending on the switching time of the PMOS transistor MP1 and the NMOS transistor MN2 in the output stage, that is, the conditions of the above-described on-time TPON, TNon, off-time TPoff, TNoff of the PMOS transistor MP1 and NMOS transistor MN2. There is a possibility that both the transistor MP1 and the NMOS transistor MN2 are turned on. For example, as shown in FIG. 6, when the off time TPoff of the PMOS transistor MP1 is longer than the on time TNon of the NMOS transistor MN2, or the off time TNoff of the NMOS transistor MN2 is longer than the on time TPon of the PMOS transistor MP1. In addition, both the PMOS transistor MP1 and the NMOS transistor MN2 are turned on, and a through current is generated. This through current causes problems such as an increase or destruction of heat generation of the PMOS transistor MP1 and the NMOS transistor MN2, a decrease in power supply efficiency, and an increase in power supply noise.

  According to the present invention, a first transistor and a second transistor that are connected in series and output an output signal from a common node, and the first transistor is in a conductive state or a non-conductive state according to an input signal and a first detection signal. A first drive circuit that drives the second transistor in a conductive state or a non-conductive state according to the input signal and the second detection signal, the input signal, In response to the first detection signal, the voltage of the common node (LX) when the first transistor is changed from the conductive state to the non-conductive state is detected, and the second detection signal is detected according to the detection result. And an output buffer circuit having a detection circuit that switches the second transistor from a non-conductive state to a conductive state.

  The output buffer circuit according to the present invention detects the voltage of the common node when the first transistor is changed from the conductive state to the non-conductive state, and the second detection signal according to the detection result according to the detection result. The transistor is turned from a non-conductive state to a conductive state. For this reason, it can be ensured that the first and second transistors are exclusively turned on.

  The output buffer circuit according to the present invention can prevent both of the output stage transistors from being turned on and generating a through current.

It is an example of the structure of the regulator circuit concerning embodiment. It is an example of the timing chart which shows operation | movement of the regulator circuit concerning embodiment. It is an example of a structure of the conventional regulator circuit. It is a timing chart which shows operation | movement of the conventional regulator circuit. It is a figure which shows the input / output characteristic of a Schmitt buffer circuit. It is a timing chart explaining the problem of the conventional regulator circuit.

  BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a switching regulator circuit.

  FIG. 1 shows an example of the configuration of the switching regulator circuit 100 according to the present embodiment. As shown in FIG. 1, the switching regulator circuit 100 includes an output buffer circuit OB101, a Schottky diode SD101, an inductor L101, and a capacitor C101. The output buffer circuit OB101 includes a driver circuit 110, a PMOS transistor MP101, and an NMOS transistor MN102.

  The PMOS transistor MP101 is connected between the power supply voltage terminal VDD and the node LX. The NMOS transistor MN102 is connected between the node LX and the ground voltage terminal GND. For convenience, the symbols “VDD” and “GND” indicate the terminal name and the power supply voltage VDD and the ground voltage GND, respectively.

  The PMOS transistor MP101 and the NMOS transistor MN102 are power MOS transistors and constitute an output stage of the switching regulator circuit 100. The PMOS transistor MP101 and the NMOS transistor MN102 are driven by gate signals PGATE and NGATE output from the driver circuit 110, respectively.

  Schottky diode SD101 is connected between node LX and ground voltage terminal GND. The Schottky diode SD101 is used so that the voltage of the node LX does not fall below the ground voltage GND (for example, about GND−0.3 VV).

  The inductor L101 has one terminal connected to the node LX and the other terminal connected to the output terminal of the driver circuit 110. Capacitor C101 has one terminal connected to the output terminal of switching regulator circuit 100 and the other connected to ground voltage terminal GND. Inductor L101 and capacitor C101 function as a low-pass filter for the signal output to node LX.

  The driver circuit 110 includes inverter circuits IV111 to IV113 and IV121 to IV125, a buffer circuit B111, a Schmitt buffer circuit SB111 and SB121, a NAND circuit NAND111, an AND circuit AND121, output terminals POUT and NOUT, and an input terminal LXIN. Have

  The inverter circuit IV111 inputs a PWM signal to the input terminal, and outputs a PPWM signal obtained by inverting the phase of the PWM signal from the output terminal. The NAND circuit NAND111 inputs the PPWM signal to one input terminal, inputs the PDLY signal to the other input terminal, and outputs the calculation result to the node N111. The inverter circuit IV112 inputs the signal output to the node N111 to the input terminal, and outputs a signal whose phase is inverted from the output terminal. The inverter circuit IV113 inputs the output signal from the inverter circuit IV112 to the input terminal, and outputs a signal whose phase is inverted from the output terminal to the output terminal POUT. Therefore, the gate signal PGATE having the same phase as the signal of the node N111, which is current buffered by the inverter circuits IV112 and IV113, is output from the output terminal POUT.

  The inverter circuit IV121 inputs a PWM signal to the input terminal and outputs a signal obtained by inverting the PWM signal from the output terminal. The inverter circuit IV122 inputs the signal output from the inverter circuit IV121 to the input terminal, and outputs a signal whose phase is inverted from the output terminal as an NPWM signal. The AND circuit AND121 inputs the NPWM signal to one input terminal, inputs the NDLY signal to the other input terminal, and outputs the calculation result to the node N121. The inverter circuit IV123 inputs the signal output to the node N121 to the input terminal, and outputs a phase-inverted signal from the output terminal. The inverter circuit IV124 inputs the output signal from the inverter circuit IV123 to the input terminal, and outputs a signal whose phase is inverted from the output terminal to the output terminal NOUT. Therefore, the gate signal NGATE having the same phase as the signal of the node N121, which is current buffered by the inverter circuits IV123 and IV124, is output from the output terminal NOUT.

  Input terminal LXIN is connected to node LX.

  The Schmitt buffer circuit SB111 is connected between the input terminal LXIN and the node N112. The Schmitt buffer circuit SB111 detects the voltage of the input terminal LXIN (node LX), and outputs a high level signal to the node N112 when the voltage of the input terminal LXIN exceeds a predetermined threshold value VH1 (> VDD / 2). When the voltage falls below a predetermined threshold VL1 (<VDD / 2), a low level signal is output to the node N112. Hereinafter, the threshold value VH1 is referred to as a high potential side threshold value and the threshold value VL1 is referred to as a low potential side threshold value. It is desirable that the threshold value VH1 be as close to the power supply voltage VDD as possible.

  The buffer circuit B111 buffers the signal output to the node N112 and outputs it as a PDLY signal.

  Schmitt buffer circuit SB121 is connected between input terminal LXIN and node N122. The Schmitt buffer circuit SB121 detects the voltage of the input terminal LXIN, and outputs a high level signal to the node N122 when the voltage of the input terminal LXIN exceeds a predetermined threshold value VH2 (> VDD / 2). When the voltage drops below the threshold value VL2 (<VDD / 2), a low level signal is output to the node N122. Hereinafter, the threshold value VH2 is referred to as a high potential side threshold value and the threshold value VL2 is referred to as a low potential side threshold value. It is desirable that threshold value VL2 be as close to ground voltage GND as possible.

  The relationship between the high potential side threshold values VH1 and VH2 and the low potential side threshold values VL1 and VL2 of the Schmitt buffer circuits SB111 and SB121 is VH1 ≧ VH2 and VL1 ≧ VL2. In other words, the logic threshold value of the Schmitt buffer circuit SB111 is higher on both the high potential side and the low potential side than the Schmitt buffer circuit SB121. Hereinafter, the Schmitt buffer circuit SB111 is expressed as having a high logic threshold, and the Schmitt buffer circuit SB121 is expressed as having a low logic threshold.

  Although details will be described later, the Schmitt buffer circuit SB111 detects the potential of the node LX as a high level, and the Schmitt buffer circuit SB121 functions as a detection circuit that detects the potential of the node LX as a low level. Have. Therefore, by setting the threshold value VH1 as close to the power supply voltage VDD as possible, the Schmitt buffer circuit SB111 can detect the potential of the node LX when the NMOS transistor MN102 is completely turned off. Further, by setting the threshold value VL2 as close to the ground voltage GND as possible, the Schmitt buffer circuit SB121 can detect the potential of the node LX when the PMOS transistor MP101 is turned off.

  A timing chart showing the operation of the switching regulator circuit 100 as described above is shown in FIG.

  First, as shown in FIG. 2, the PWM signal rises to a high level at time t1, and the PPWM signal also falls to a low level almost simultaneously. At this time, since the PDLY signal is at a high level, the NAND circuit NAND111 outputs a high level signal as a calculation result. The high-level gate signal PGATE buffered by the inverter circuits IV112 and IV113 is output from the output terminal POUT.

  Here, it is assumed that the inverter circuit IV113 that outputs the gate signal PGATE to the output terminal POUT has a capability of sufficiently driving the PMOS transistor MP101. Since the gate signal PGATE rises to a high level, the PMOS transistor MP101 is turned off. However, the PMOS transistor MP101 is turned off at time t2 after the off time TPoff from the rise of the gate signal PGATE due to the influence of the gate capacitance and the like.

  Since the PMOS transistor MP101 is turned off, the voltage of the node LX falls. The Schmitt buffer SB121 detects the voltage drop at the node LX via the input terminal LXIN. When the voltage at the node LX becomes equal to or lower than the threshold voltage VL2, a low level signal is output to the node N122. The Schmitt buffer circuit SB111 also naturally detects a voltage drop at the node LX and changes the PDLY signal to the low level via the buffer circuit B111, but the operation result output of the NAND circuit NAND111 does not change.

  Inverter circuit IV125 inverts the signal output to node N122 and outputs the inverted signal as a high-level NDLY signal.

  The AND circuit AND121 inputs the high level NDLY signal to the other input terminal. Since the NPWM signal input to one terminal is already at the high level at time t1, the AND circuit AND121 outputs a high level signal to the node N121 as a calculation result. Further, the signal output to the node N121 is buffered by the inverter circuits IV123 and IV124, and is output from the output terminal NOUT as the high level gate signal NGATE.

  Here, it is assumed that the inverter circuit IV124 that outputs the gate signal NGATE to the output terminal NOUT has a capability of sufficiently driving the NMOS transistor MN102. Since the gate signal NGATE rises to a high level, the NMOS transistor MN102 is turned on. However, the NMOS transistor MN102 is turned on at time t3 after the on time TNon from the rise of the gate signal NGATE due to the influence of the gate capacitance and the like.

  Next, as shown in FIG. 2, the PWM signal falls to the low level at time t4, and the NPWM signal also falls to the low level almost simultaneously. At this time, since the NDLY signal is at a high level, the AND circuit AND121 outputs a low-level signal to the node N121 as a calculation result. Further, the signal output to the node N121 is buffered by the inverter circuits IV123 and IV124, and is output from the output terminal NOUT as the low-level gate signal NGATE. Since the gate signal NGATE falls to the low level, the NMOS transistor MN102 is turned off. However, the NMOS transistor MN102 is assumed to be in the off state at time t5 after the off time TNoff from the fall of the gate signal NGATE due to the influence of the gate capacitance or the like.

  Since the NMOS transistor MN102 is turned off, the voltage of the node LX rises. The Schmitt buffer circuit SB111 detects the voltage rise at the node LX via the input terminal LXIN. When the voltage at the node LX becomes equal to or higher than the threshold voltage VH1, a high level signal is output to the node N112. The Schmitt buffer SB121 also naturally detects the voltage rise at the node LX and changes the NDLY signal to the low level via the inverter circuit IV125, but the operation result output of the AND circuit AND121 does not change.

  The buffer circuit B111 buffers the signal output to the node N112 and outputs it as a high-level PDLY signal.

  The NAND circuit NAND111 inputs the high-level PDLY signal to the other input terminal. Since the PPWM signal input to one terminal is already at the high level at time t4, the NAND circuit NAND111 outputs a low level signal to the node N111 as a calculation result. Further, the signal output to the node N111 is buffered by the inverter circuits IV112 and IV113, and output from the output terminal POUT as the low level gate signal PGATE.

  Since the gate signal PGATE falls to the low level, the PMOS transistor MP101 is turned on. However, it is assumed that the PMOS transistor MP101 is turned on at time t6 after the on time Tpon from the rise of the gate signal PGATE due to the influence of the gate capacitance and the like.

  Here, in the conventional regulator circuit 1, depending on the conditions of the switching time (off time TPoff, TNoff, on time TPon, TNon) of the PMOS transistor MP1 and NMOS transistor MN2 in the output stage, the PMOS transistor MP1 and NMOS transistor There was a possibility that both MN2 would be turned on. The switching time condition includes variations in the transistor sizes of the PMOS transistor MP1 and the NMOS transistor MN2 due to manufacturing variations, voltage fluctuations in the power supply voltage VDD, changes in ambient temperature, and the like.

  For example, as shown in FIG. 6, when the off time TPoff of the PMOS transistor MP1 is longer than the on time TNon of the NMOS transistor MN2, or the off time TNoff of the NMOS transistor MN2 is longer than the on time TPon of the PMOS transistor MP1. In addition, both the PMOS transistor MP1 and the NMOS transistor MN2 are turned on, and a through current is generated.

  The problem that this through current occurs is that when the regulator circuit 1 detects the rise of the gate signal PGATE, the gate signal NGATE is raised regardless of whether the PMOS transistor MP1 is turned off. Is attributed. Similarly, when the regulator circuit 1 detects the fall of the gate signal NGATE, the gate signal PGATE is lowered regardless of whether the NMOS transistor MN2 is turned off. Current was generated. The generation of the through current causes problems such as an increase or destruction of heat generation of the PMOS transistor MP1 and the NMOS transistor MN2, a decrease in power supply efficiency, and an increase in power supply noise.

  However, in the switching regulator circuit 100 of the present embodiment, the timing at which the PMOS transistor MP101 is turned off is detected from the falling of the potential of the node LX, and then the gate signal NGATE for turning on the NMOS transistor MN102 is output. Yes. Similarly, the timing at which the NMOS transistor MN102 is turned off is detected from the rise of the potential of the node LX, and then the gate signal PGATE for turning on the PMOS transistor MP101 is output. Such control ensures that the PMOS transistor MP101 and the NMOS transistor MN102 are exclusively turned on regardless of manufacturing variations in switching time of the PMOS transistor MP101 and the NMOS transistor MN102, and fluctuations in the power supply voltage and the ambient temperature. Is possible.

  Since the PMOS transistor MP101 and the NMOS transistor MN102 can be turned on exclusively with certainty, it is possible to prevent the occurrence of a through current that has been a problem in the regulator circuit 1. In addition, it is possible to prevent the occurrence of problems such as an increase or destruction of heat generation of the PMOS transistor MP101 and the NMOS transistor MN102, a decrease in power supply efficiency, and an increase in power supply noise due to the through current.

  Further, the switching regulator circuit 100 turns on the NMOS transistor MN102 after a minimum period during which no through current flows from the timing when the PMOS transistor MP101 turns off, and the through current flows from the timing when the NMOS transistor MN102 turns off. Since the PMOS transistor MP101 can be turned on after a certain minimum period, it is effective in improving the switching frequency and power supply efficiency.

  Furthermore, the switching regulator circuit 100 detects the falling of the potential of the node LX at a low level by the Schmitt buffer circuit SB121 having a low logic threshold value, and the Schmitt buffer circuit having the high potential of the node LX. A high level is detected at SB111. As a result, the potential can be detected in consideration of the rise and fall of the potential waveform of the node LX, and the on-timing of the PMOS transistor MP101 and the NMOS transistor MN102 can be adjusted appropriately.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

100 switching regulator 110 driver circuit MP101 PMOS transistor (power transistor)
MN102 NMOS transistor (power transistor)
SD101 Schottky diode L101 Inductor C101 Capacitors IV111 to IV113, IV121 to IV125 Inverter circuit B111 Buffer circuit SB111, SB121 Schmitt buffer circuit NAND111 NAND circuit AND121 AND circuit POUT, NOUT Output terminal LXIN Input terminal

Claims (6)

A first transistor and a second transistor connected in series and outputting an output signal from a common node (LX);
A first drive circuit for driving the first transistor to a conductive state or a non-conductive state according to an input signal and a first detection signal;
A second drive circuit that drives the second transistor to a conductive state or a non-conductive state in response to the input signal and the second detection signal;
According to the input signal and the first detection signal, a voltage of the common node when the first transistor is changed from a conductive state to a non-conductive state is detected, and the second detection is performed according to the detection result. An output buffer circuit comprising: a detection circuit configured to switch the second transistor from a non-conductive state to a conductive state by a signal. The detection circuit detects a voltage of the common node when the second transistor is changed from a conductive state to a non-conductive state according to the input signal and the second detection signal, and according to the detection result The output buffer circuit according to claim 1, wherein the first transistor is turned from a non-conductive state to a conductive state by the first detection signal. The first and second transistors are connected between a first power supply terminal that supplies a first power supply voltage and a second power supply terminal that supplies a second power supply voltage,
The detection circuit includes:
A first threshold voltage on the first voltage side from an intermediate potential between the first voltage and the second voltage, and a second threshold voltage on the second voltage side. A first Schmitt buffer circuit comprising:
A third threshold voltage on the first voltage side from an intermediate potential between the first voltage and the second voltage, and a fourth threshold voltage on the second voltage side. A second Schmitt buffer circuit having
The second Schmitt buffer circuit is configured to turn off the second transistor when the first transistor changes from a conductive state to a non-conductive state and the potential of the common node exceeds the fourth threshold voltage. Outputting the second detection signal for switching from the conductive state to the conductive state;
The first Schmitt buffer circuit disables the second transistor when the second transistor is changed from a conductive state to a non-conductive state and the potential of the common node exceeds the first threshold voltage. The output buffer circuit according to claim 2, wherein the second detection signal for switching from a conductive state to a conductive state is output. The first power supply voltage is a power supply voltage of an output buffer circuit, and the second power supply voltage is a ground voltage;
The first threshold voltage is higher than the third threshold voltage;
The output buffer circuit according to claim 3, wherein the fourth threshold voltage is lower than the second threshold voltage. The first driving circuit inputs a negative phase signal of the input signal to one input, the first detection signal to the other input, and outputs a result of the NAND operation thereof to a control terminal of the first transistor NAND circuit that outputs to
The second driving circuit inputs an in-phase signal of the input signal to one input, an anti-phase signal of the second detection signal to the other input, and outputs a logical product operation result to the second transistor. The output buffer circuit according to claim 1, further comprising an AND circuit that outputs to the control terminal. It has an output buffer circuit given in any 1 paragraph of Claims 1-5,
An inductor connected in series between the common node and the output terminal;
A capacitor having one terminal connected to the output terminal;
And a Schottky diode having a cathode connected to the common node.

Images