JP2011082766A - Amplification circuit and imaging system - Google Patents

Abstract

In an amplifier circuit, the accuracy of processing for canceling an offset of a differential amplifier is improved.
An amplifier circuit that performs a correction operation in a first period and performs an amplification operation in a second period following the first period, wherein the correction circuit performs the correction in the first period. As the operation, the voltage difference between both ends of the detection element detected by the detection circuit in a state where the voltage of the two input terminals is fixed to the reference voltage by the fixing unit is within an allowable value. A control value for performing a correction operation including at least one of an operation of supplying a first correction current to the first node and an operation of supplying a second correction current to the second node is determined and held. In the second period, a correction unit that performs the correction operation according to the control value held in the first period is provided.
[Selection] Figure 1

Description

  The present invention relates to an amplifier circuit and an imaging system.

  In an imaging system such as a digital camera, an imaging sensor captures an object to generate and output an analog image signal, an A / D converter converts the analog image signal into a digital image signal, and a digital image signal at a subsequent stage. Is subjected to predetermined signal processing. An imaging sensor in this imaging system has a pixel array in which a plurality of pixels are arrayed. In recent years, the number of pixels in the pixel array of the image sensor has been increasing, and in response to the demand for improvement in the image quality of images captured by the image sensor, A / D converters have high speed and high speed. Resolution characteristics are required. Further, along with the price reduction of products (imaging systems), cost reduction of A / D converters is required.

  As an A / D converter that satisfies the above requirements, a pipeline A / D converter manufactured by a CMOS process has been put into practical use. A pipelined A / D converter generally uses a switched capacitor circuit using a differential input / output amplifier. When using a differential input / output amplifier, the common mode voltage of the output is set to a predetermined voltage near the middle of the power supply voltage in order to ensure an output dynamic range.

  Patent Document 1 describes that in a fully differential amplifier 204, a positive-phase input node and a negative-phase input node are each connected to a predetermined reference voltage VCM when sampling an input signal (Patent Document 1). 1 (see FIG. 5). Thus, according to Patent Document 1, it is supposed that the common mode voltage of the differential outputs Vo1 and Vo2 of the fully differential amplifier 204 can be stabilized.

  Further, in Patent Document 1, in the fully differential amplifier 204, when sampling an input signal, a negative phase output node and a positive phase input node are short-circuited, and a positive phase output node and a negative phase input node are connected. Short circuit is described. Thus, according to Patent Document 1, self-bias is applied so as to apply negative feedback from the output side to each of the positive-phase input node and the negative-phase input node, so that the offset voltage of the fully differential amplifier 204 is canceled. It is supposed to be possible.

  Patent Document 2 describes a buffer circuit 41 with a correction function that includes a buffer unit 42, an offset cancel unit 43, and a common mode feedback circuit 44 (see FIG. 2 of Patent Document 2). That is, the differential outputs Voutn and Voutp of the buffer unit 42 are supplied to one end of the first resistor 71 and one end of the second resistor 72 in the offset canceling unit 43, respectively. Since the first resistor 71 and the second resistor 72 have the same resistance value, the differential outputs Voutn and Voutp are connected from the connection point between the other end of the first resistor 71 and the other end of the second resistor 72. The output common mode voltage Vcm, which is the midpoint voltage of, is output. The common mode feedback circuit 44 receives the output common mode voltage Vcm and the set common mode voltage Vcms, and supplies a signal corresponding to the difference between the two to the gates of the transistors 57 and 67. Thus, according to Patent Document 2, the common mode feedback circuit 44 can control the output common mode voltage Vcm to be the same as the set common mode voltage Vcms.

  Patent Document 2 describes an offset cancel circuit 21b including a comparator 25, a SAR (Successive Application Register Successive Register) 26, and a DAC 27 (see FIG. 2 of Patent Document 2). That is, the comparator 25 receives one differential output Voutn and the output common mode voltage Vcm in the differential output of the buffer unit 42, compares them, and supplies the comparison result to the SAR 26. The SAR 26 supplies an 8-bit signal corresponding to the received comparison result to the DAC 27. The DAC 27 performs DA conversion on the 8-bit signal, thereby generating an offset adjustment signal Va and supplying the offset adjustment signal Va to the gate of the third transistor 61 in the offset cancel unit 43. At this time, the fixed voltage Vs is input to the gate of the fourth transistor 62 in the offset canceling unit 43, and the drain current of the third transistor 61 and the drain current of the fourth transistor 62 are equal in a steady state. Become. Thus, according to Patent Document 2, since the difference between one differential output Voutn and the output common mode voltage Vcm is controlled to be zero, the DC offset between the differential outputs Voutn and Voutp of the buffer unit 42 is controlled. Can be controlled to be zero.

JP 2002-325038 A JP 2006-287819 A

  On the other hand, as MOS transistors manufactured by the CMOS process become finer, noise in a low frequency band called 1 / f noise becomes more prominent. The 1 / f noise includes a noise component that temporally varies in a low frequency band of several hundred Hz to several tens kHz.

  In a differential input / output amplifier manufactured by a CMOS process, an offset including a component that fluctuates in a low frequency band is generated due to 1 / f noise of a MOS transistor that is a constituent element. When such a differential input / output amplifier is used for the processing of the output signal of the image sensor by using the A / D converter in the above imaging system, a striped pattern is formed on the image obtained according to the processed signal. Noise is generated and easily visible. In order not to be visually recognized, the noise level in the low frequency band needs to be about 1/10 or less of the noise level in the high frequency band. That is, in the differential input / output amplifier (differential amplifier) used for the A / D converter of the imaging system, it is necessary to cancel not only the DC component in the offset but also the component that fluctuates in the low frequency band with high accuracy.

  In the circuit shown in FIG. 5 of Patent Document 1, it is considered that charges for canceling the offset voltage of the fully-differential amplifier 204 are charged in the capacitors Cp1, Cp2, Cn1, and Cn2 when sampling the input signal. At this time, the variation between the on-resistance of the switch for short-circuiting the negative-phase output node and the positive-phase input node and the on-resistance of the switch connecting the predetermined reference voltage VCM to the positive-phase input node is offset. Affects the accuracy of the process of canceling. In addition, the variation between the on-resistance of the switch for short-circuiting the positive-phase output node and the negative-phase input node and the on-resistance of the switch connecting the predetermined reference voltage VCM to the negative-phase input node may cause an offset. Affects the accuracy of the canceling process. Further, the input / output impedance of the fully-differential amplifier 204 also affects the accuracy of processing for canceling the offset. Due to these effects, with the configuration shown in FIG. 5 of Patent Document 1, it is difficult to accurately cancel a component that fluctuates in the low frequency band in the offset of the fully differential amplifier 204.

  The circuit shown in FIG. 2 of Patent Document 2 is a circuit that operates in a continuous time and cannot operate in a discrete time, and thus is not suitable for use in an A / D converter of an imaging system. The circuit shown in FIG. 2 of Patent Document 2 has a configuration for canceling the DC component in the offset, but has a configuration for canceling the component that fluctuates in the low frequency band in the offset. Not. Therefore, even if the circuit shown in FIG. 2 of Patent Document 2 is used, it is impossible to cancel a component that fluctuates in a low frequency band in the offset with high accuracy.

  The invention described in Patent Document 1 is essentially characterized by a circuit configuration devised to be configured with a small number of elements for the purpose of reducing the circuit size of the fully differential amplifier 204 and reducing the chip occupation area. It is said. Here, the offset cancel unit 43 and the offset cancel circuit 21b shown in FIG. 2 of Patent Document 2 have a very large circuit scale. Therefore, in the invention described in Patent Document 1, the circuit shown in FIG. 5 of Patent Document 1 is changed in design using the offset cancel unit 43 and the offset cancel circuit 21b shown in FIG. I can't do it.

  An object of the present invention is to improve the accuracy of processing for canceling an offset of a differential amplifier in an amplifier circuit.

  An amplifier circuit according to one aspect of the present invention includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and for correction in the first period. The amplifier circuit performs an amplification operation in a second period following the first period, and includes two input terminals respectively connected to the first input terminal and the second input terminal. A differential voltage is received, and a differential current corresponding to the differential voltage is supplied to a third output terminal connected to the first output terminal and a fourth output terminal connected to the second output terminal. And the two input terminals so that the voltage of the two input terminals is fixed to a reference voltage in the first period and the amplification operation is enabled in the second period. Including a fixing portion for releasing the fixing of the voltage of the terminal and the detection element, and in the first period. A detection circuit for detecting a voltage difference between both ends of the detection element by connecting one end of the detection element to the third output terminal and connecting the other end of the detection element to the fourth output terminal; In the first period, a voltage difference between both ends of the detection element detected by the detection circuit in a state where the voltages of the two input terminals are fixed to the reference voltage by the fixing unit is within an allowable value. As described above, the operation of supplying the first correction current to the first node between the third output terminal and the first output terminal, and the fourth output terminal and the second output terminal Determining and holding a control value for performing a correction operation including at least one of an operation of supplying a second correction current to a second node between the first node and the second period. A correction unit that performs the correction operation according to the held control value Characterized by comprising a.

  ADVANTAGE OF THE INVENTION According to this invention, the precision of the process which cancels the offset of a differential amplifier in an amplifier circuit can be improved.

The block diagram showing embodiment of the amplifier circuit of this invention. The figure showing embodiment of the offset cancellation part of this invention. The figure showing embodiment of the common mode detection and common mode voltage control part of this invention. The circuit diagram showing embodiment of the input terminal fixing | fixed part of this invention. FIG. 2 is a switched capacitor type sample hold circuit (a) using the amplifier circuit of the present invention and a drive timing chart (b). 4 is another timing chart for driving the sample hold circuit. 1 is a configuration diagram of an imaging system to which an amplifier circuit according to an embodiment is applied.

  The configuration of the amplifier circuit 100 according to the embodiment of the present invention will be described with reference to FIG.

  The amplifier circuit 100 has a first input terminal 2, a second input terminal 3, a first output terminal 4, and a second output terminal 5. The amplifier circuit 100 performs an operation for correction in the first period TP1 (see FIG. 5B), and performs an amplification operation in the second period TP2 (see FIG. 5B) following the first period TP1. I do. The amplifier circuit 100 includes a differential amplifier unit 1, an input terminal fixing unit 6, a common mode detection unit 8, a common mode voltage control unit 9, an offset cancel unit 20, and a timing circuit 16.

  The differential amplifier 1 includes, for example, a fully differential transconductance amplifier. The differential amplifying unit 1 includes two input terminals 11 and 12, a third output terminal 13, and a fourth output terminal 14. The input terminal 11 is connected to the first input terminal 2. The input terminal 12 is connected to the second input terminal 3. The third output terminal 13 is connected to the first output terminal 4. The fourth output terminal 14 is connected to the second output terminal 5. The differential amplifier 1 receives a differential voltage at the two input terminals 11 and 12 and outputs a differential current corresponding to the differential voltage from the third output terminal 13 and the fourth output terminal 14.

  The input terminal fixing unit 6 has an input reference voltage terminal 7. The input terminal fixing unit 6 receives the input reference voltage Vinf via the input reference voltage terminal 7. The input terminal fixing unit 6 fixes the voltages of the two input terminals 11 and 12 to the input reference voltage Vinf in the first period TP1 (see FIG. 5B). The input terminal fixing unit 6 releases the fixed voltages of the two input terminals 11 and 12 so that the amplification operation by the amplifier circuit 100 can be performed in the second period TP2 (see FIG. 5B).

  The common mode detection unit 8 detects an intermediate voltage between the voltage of the third output terminal 13 and the voltage of the fourth output terminal 14, that is, the common mode voltage, in the first period TP1 and the second period TP2. The common mode detection unit 8 supplies the detected common mode voltage to the common mode voltage control unit 9.

  The common mode voltage control unit 9 has an output reference voltage terminal 10. The common mode voltage control unit 9 receives an output reference voltage (second reference voltage) Vcmf via the output reference voltage terminal 10. The common mode voltage control unit 9 performs differential operation so that the common mode voltage detected by the common mode detection unit 8 matches (becomes equal to) the output reference voltage Vcmf in the first period TP1 and the second period TP2. The amplifying unit 1 is controlled.

  The offset canceling unit 20 outputs the current output from the first output terminal 4 and the second output terminal 5 in order to correct (cancel) the offset of the differential amplifying unit 1 in the first period TP1. The current is corrected to be equal.

  That is, the offset cancellation unit 20 includes a detection circuit 30 and a correction unit 40 as described later. The details of the internal configuration of the detection circuit 30 and the correction unit 40 will be described later.

  The detection circuit 30 includes an impedance element (detection element) 18. In the first period TP1, the detection circuit 30 connects one end T1 of the impedance element 18 to the first node N1, and connects the other end T2 of the impedance element 18 to the second node N2 (see FIG. 2). The first node N <b> 1 is a node between the third output terminal 13 and the first output terminal 4. The second node N <b> 2 is a node between the fourth output terminal 14 and the second output terminal 5. Then, the detection circuit 30 detects a voltage difference between both ends T1 and T2 of the impedance element 18. That is, the detection circuit 30 detects the voltage at one end T1 and the voltage at the other end T2 of the impedance element 18, respectively. The impedance element 18 cuts off the connection to the first output terminal of the one end T1 of the impedance element 18 in the second period TP2, and the second output terminal 5 of the other end T2 of the one end T1 of the impedance element 18. The connection to is blocked.

  The correction unit 40 has both ends of the impedance element 18 detected by the detection circuit 30 in a state where the voltages of the two input terminals 11 and 12 are fixed to the input reference voltage Vinf by the input terminal fixing unit 6 in the first period TP1. It operates so that the voltage difference between the two is within an allowable value. That is, the correction unit 40 performs a correction operation including at least one of an operation of supplying the first correction current Ic1 to the first node N1 and an operation of supplying the second correction current Ic2 to the second node N2. A control value is determined and held. That is, the correction unit 40 uses the control value held until the voltage difference between both ends of the impedance element 18 falls within the allowable value as an operation for correction in the first period TP1. The same operation as the above correction operation is repeated in a preliminary manner. Thereby, the control value for making the current output from the first output terminal 4 equal to the current output from the second output terminal 5 in the first period TP1 is determined and held. . In the second period TP2, the correction unit 40 performs the above correction operation according to the control value held in the first period TP1.

  The timing circuit 16 supplies control signals to the input terminal fixing unit 6, the common mode detection unit 8, and the offset cancellation unit 20, so that each of the input terminal fixing unit 6, the common mode detection unit 8, and the offset cancellation unit 20 is provided. Control the operation timing. For example, the timing circuit 16 controls the input terminal fixing unit 6 so that the two input terminals 11 and 12 are connected to the input reference voltage Vinf during the offset cancel operation (first period TP1). The timing circuit 16 detects a voltage difference generated at the third output terminal 13 and the fourth output terminal 14 due to the offset of the differential amplifying unit 1 during the first period TP1, and provides feedback in a direction to reduce the offset. The offset cancel unit 20 is controlled so as to be applied.

  Next, an example of the internal configuration of the offset cancel unit 20 will be described with reference to FIG.

  The offset cancel unit 20 is a detection circuit 30 and a correction unit 40. The detection circuit 30 includes the connection unit 17 and the impedance element 18. The correction unit 40 includes a comparator (voltage comparison unit) 42, a memory unit (control value holding unit) 43, and a current D / A converter 45.

  The connection unit 17 connects one end T1 of the impedance element 18 to the first node N1 and the other end T2 of the impedance element 18 to the second node N2 in the first period TP1 (see FIG. 5B). Connecting. The connection unit 17 interrupts the connection of the one end T1 of the impedance element 18 to the first node N1 during the second period TP2 and the third period TP3 (see FIG. 5B). The connection to the second node N2 at the end T2 is cut off. The connection unit 17 includes a switch S171 and a switch S172. The switches S171 and S172 are turned on when receiving an active level control signal φOD via the control input terminal 19 and turned off when receiving a non-active level control signal φOD.

  The comparator 42 compares the voltage at one end T1 of the impedance element 18 detected by the detection circuit 30 with the voltage at the other end T2, and outputs a voltage error signal VDS corresponding to the comparison result to the memory unit 43.

  The memory unit 43 has a clock input terminal 14. The memory unit 43 receives the clock signal φOCLK via the clock input terminal 14. The memory unit 43 determines the held digital control value according to the voltage error signal VDS output from the comparator 42 at a timing synchronized with the clock signal φOCLK. The memory unit 43 holds and outputs the determined digital control value.

  The memory unit 43 includes, for example, an up / down counter 431. The up / down counter 431 performs the following operation when the voltage error signal VDS indicates that the current output from the first output terminal 4 is larger than the current output from the second output terminal 5. The memory unit 43 performs a count-up operation for counting up the held digital control value. The up / down counter 431 performs the following operation when the voltage error signal VDS indicates that the current output from the first output terminal 4 is smaller than the current output from the second output terminal 5. The up / down counter 431 performs a countdown operation for counting down the held digital control value. The up / down counter 431 holds and outputs the count value as a digital control value.

  The current D / A converter 45 includes a D / A converter 451 and a current generator 452.

  The D / A conversion unit 451 generates an analog control value by D / A converting the digital control value after the change output from the memory unit 43. Specifically, when the D / A conversion unit 451 receives the counted-up digital control value from the memory unit 43, the D / A conversion unit 451 performs the D / A conversion on the counted-up digital control value, thereby counting up. An analog control value corresponding to the digital control value is generated. When the D / A conversion unit 451 receives the counted down digital control value from the memory unit 43, the D / A conversion unit 451 performs D / A conversion on the counted down digital control value to perform analog control according to the counted down digital control value. Generate a value. The D / A conversion unit 451 supplies the generated analog control value to the current generation unit 452.

  The current generator 452 receives the analog control value generated by the D / A converter 451 as an analog control value corresponding to the digital control value output from the up / down counter 431. The current generator 452 performs the correction operation according to the received analog control value. That is, the current generator 452 generates and outputs at least one of the first correction current Ic1 and the second correction current Ic2. Specifically, when the current generation unit 452 receives an analog control value corresponding to the counted-up digital control value, the current generation unit 452 decreases the first correction current Ic1 and increases the second correction current Ic2. And at least one of them. The current generator 452 performs at least one of an operation of increasing the first correction current Ic1 and an operation of decreasing the second correction current Ic2 when receiving an analog control value corresponding to the counted-down digital control value. . Then, the current generator 452 performs at least one of an operation of supplying the first correction current Ic1 to the first node N1 and an operation of supplying the second correction current Ic2 to the second node N2. As a result, the current output from the first output terminal 4 and the current output from the second output terminal 5 are corrected to be equal.

  As described above, the impedance element 18 has one end T1 connected to the first node N1 and the other end T2 connected to the second node N2 in the first period TP1. In the second period TP2, the impedance element 18 is in a state where the connection of the one end T1 to the first node N1 is cut off and the connection of the other end T2 to the second node N2 is cut off. .

  Here, when the current conversion gain of the differential amplifying unit (fully differential transconductance amplifier) 1 is Gm and the impedance value of the impedance element 18 is Z, a voltage (voltage difference) that is (Gm × Z) times the offset voltage. Is input to the comparator 42. It is necessary to determine the value of Z so that the input offset that fluctuates in the low frequency band of the comparator 42 does not become a problem with respect to the accuracy required in the process of canceling the offset. Further, the minimum resolution ΔI of the current D / A converter 45 needs to be set so that (ΔI / Gm) is smaller than the accuracy required in the process of canceling the offset.

  Next, an internal configuration example of the common mode detection unit 8 and a configuration example of the common mode voltage control unit 9 will be described with reference to FIG.

  The common mode detection unit 8 includes a detection unit 81 and a reset unit 82.

  The detection unit 81 includes a first detection capacitor C811 and a second detection capacitor C812. The first detection capacitor C811 is connected between the first node N1 and the third node N3. The second detection capacitor C812 is connected between the second node N2 and the third node N3. The capacitance value of the first detection capacitor C811 is substantially equal to the capacitance value of the second detection capacitor C812. As a result, the voltage at the third node N3 becomes an intermediate voltage between the voltage at the first node N1 and the voltage at the second node N2. That is, the detection unit 81 detects the voltage of the third node N3 as a common mode voltage with respect to the voltage of the first output terminal 4 and the voltage of the second output terminal 5.

  The reset unit 82 resets the first detection capacitor C811 and the second detection capacitor C812 in the third period TP3 (see FIG. 5B). That is, the reset unit 82 includes a switch S821 and a switch S822. The switch S821 is turned on when receiving an active level control signal φCM, thereby short-circuiting both ends of the first detection capacitor C811, thereby resetting the first detection capacitor C811. The switch S821 is turned off when receiving the non-active level control signal φCM, thereby completing the reset of the first detection capacitor C811.

  The switch S822 is turned on when receiving an active level control signal φCM, thereby short-circuiting both ends of the second detection capacitor C812 and resetting the second detection capacitor C812. Note that the first output terminal 4 and the second output terminal 5 are short-circuited when the switch S821 and the switch S822 are turned on. The switch S822 is turned off when receiving the non-active level control signal φCM, thereby completing the reset of the second detection capacitor C812.

  The common mode voltage control unit 9 includes, for example, a comparator 9i. The comparator 9 i receives the voltage of the third node N 3, that is, the common mode voltage detected by the detection unit 81. The comparator 9 i receives the output reference voltage (second reference voltage) Vcmf via the output reference voltage terminal 10. The comparator 9 i compares the output reference voltage Vcmf with the detected common mode voltage, and supplies a control signal corresponding to the comparison result to the differential amplifier 1. As a result, the comparator 9i performs differential operation so that the common mode voltage detected by the common mode detection unit 8 matches (becomes equal to) the output reference voltage Vcmf during the first period TP1 and the second period TP2. The amplifying unit 1 is controlled.

  Next, an example of the internal configuration of the input terminal fixing unit 6 will be described with reference to FIG.

  The input terminal fixing unit 6 includes, for example, a switch S61 and a switch S62.

  The switch S61 is turned on when receiving the control signal φS of the active level, thereby connecting the input terminal 11 (see FIG. 1) of the differential amplification unit 1 and the input reference voltage terminal 7. Thereby, the voltage of the input terminal 11 is fixed to the input reference voltage Vinf. The switch S61 cuts off the connection between the input terminal 11 and the input reference voltage terminal 7 by turning off when receiving the non-active level control signal φS. Thereby, the fixing of the voltage of the input terminal 11 is released.

  The switch S62 is turned on when receiving the control signal φS of the active level, thereby connecting the input terminal 12 (see FIG. 1) of the differential amplification unit 1 and the input reference voltage terminal 7. Thereby, the voltage of the input terminal 12 is fixed to the input reference voltage Vinf. The switch S62 is turned off when receiving the non-active level control signal φS, thereby disconnecting the connection between the input terminal 12 and the input reference voltage terminal 7. Thereby, the fixing of the voltage of the input terminal 12 is released.

  Next, an example of a sample and hold circuit to which the amplifier circuit 100 according to the embodiment of the present invention is applied will be described with reference to FIG.

  The sample and hold circuit 300 shown in FIG. 5A has input terminals T302 and T303 and output terminals T304 and T305. The sample hold circuit 300 includes a switched capacitor circuit (SC circuit) 200 and an amplifier circuit 100. The SC circuit 200 includes switches S201 to S205, a first input capacitor Cin1, a second input capacitor Cin2, a first output capacitor Cout1, and a second output capacitor Cout2.

  The first input capacitor Cin1 includes an electrode 231 and an electrode 232. The second input capacitor Cin2 includes an electrode 241 and an electrode 242. The first output capacitor Cout1 includes an electrode 251 and an electrode 252. The second output capacitor Cout2 includes an electrode 261 and an electrode 262.

  The switch S201 is turned on when receiving an active level control signal φS from the timing circuit 16, thereby connecting the input terminal T302 to the terminal 212 and the electrode 231 of the first input capacitor Cin1. The switch S201 is turned off when receiving the non-active level control signal φS from the timing circuit 16, thereby cutting off the connection from the input terminal T302 to the terminal 212 and the electrode 231.

  The switch S202 is turned on when receiving an active level control signal φS from the timing circuit 16, thereby connecting the input terminal T303 to the terminal 222 and the electrode 241 of the second input capacitor Cin2. The switch S202 is turned off when receiving the non-active level control signal φS from the timing circuit 16, thereby cutting off the connection from the input terminal T303 to the terminal 222 and the electrode 241.

  The switch S203 connects the electrode 211 of the first output capacitor Cout1 to the input terminal T302 via the switch S201 by connecting the terminal 211 to the terminal 212 when receiving the active level control signal φS from the timing circuit 16. . At this time, the connection from the electrode 251 of the first output capacitor Cout1 to the first output terminal 4 and the output terminal T304 is cut off. The switch S203 connects the terminal 211 to the terminal 213 when receiving the active level control signal φH from the timing circuit 16, thereby connecting the electrode 251 of the first output capacitor Cout1 to the first output terminal 4 and the output terminal T304. Connect to. At this time, the connection of the first output capacitor Cout1 from the electrode 251 to the input terminal T302 is cut off.

  The switch S204 connects the terminal 221 to the terminal 222 when receiving the active level control signal φS from the timing circuit 16, thereby connecting the electrode 261 of the second output capacitor Cout2 to the output terminal T303 via the switch S202. . At this time, the connection from the electrode 261 of the second output capacitor Cout2 to the second output terminal 5 and the output terminal T305 is cut off. The switch S204 connects the terminal 221 to the terminal 223 when receiving the active level control signal φH from the timing circuit 16, thereby connecting the electrode 261 of the second output capacitor Cout2 to the second output terminal 5 and the output terminal T305. Connect to. At this time, the connection from the electrode 261 of the second output capacitor Cout2 to the output terminal T303 is cut off.

  The switch S205 is turned on when the active level control signal φH is received from the timing circuit 16, thereby short-circuiting the electrode 231 of the first input capacitor Cin1 and the electrode 241 of the second input capacitor Cin2. The switch S205 is turned off when receiving the non-active level control signal φH from the timing circuit 16, thereby releasing the short circuit between the electrode 231 of the first input capacitor Cin1 and the electrode 241 of the second input capacitor Cin2. .

  It is assumed that the period during which the control signal φS is active level and the period during which the control signal φH is active level do not overlap.

  Next, the operation of the sample hold circuit 300 will be described in detail with reference to FIG.

  In the S1 period, when φS is at an active level (for example, H level), the voltage of the first input terminal 2 and the voltage of the second input terminal 3 in the input terminal pair ITP of the amplifier circuit 100 are respectively input reference voltages Fixed to Vinf. Accordingly, the potential of the electrode 232 of the first input capacitor Cin1, the potential of the electrode 242 of the second input capacitor Cin2, the potential of the electrode 252 of the first output capacitor Cout1, and the potential of the electrode 262 of the second output capacitor Cout2 However, both are fixed to the potential of the input reference voltage Vinf. The differential signal received by the sample hold circuit 300 at the input terminals T302 and T303 is based on the input reference voltage Vinf as a first input capacitor Cin1, a second input capacitor Cin2, a first output capacitor Cout1, and a second signal. Is sampled to the output capacitance Cout2.

  At this time (that is, the third period TP3), the control signal φCM also becomes an active level (for example, H level), the switches S821 and S822 in the common mode detection unit 8 become conductive, and the capacitors C811 and C812 of the common mode detection unit 8 Reset.

  In the H1 period, when φH is at an active level (eg, H level) (that is, the second period TP2), the electrode 251 of the first output capacitor Cout1 is connected to the output terminal T304 of the sample hold circuit 300. The electrode 261 of the second output capacitor Cout2 is connected to the output terminal T305 of the sample and hold circuit 300. At the same time, the charge sampled in the first input capacitor Cin1 is moved and held in the first output capacitor Cout1, and the charge sampled in the second input capacitor Cin2 is moved and held in the second output capacitor Cout2. The Here, when the capacitance values of the first input capacitor Cin1, the second input capacitor Cin2, the first output capacitor Cout1, and the second output capacitor Cout2 are all equal, a signal twice as large as the input differential signal is output. This is the difference signal to be performed.

  In the S2 period, the sampling operation is performed in the same manner as in the S1 period. In parallel with this, the control signal ΦOD becomes an active level (for example, H level), and both ends T1, T2 of the impedance element 18 are connected to the first node N1 and the second node N2 by the connection unit 17, respectively. (See FIG. 2). A voltage (Gm × Z) times the input offset voltage is input to the comparator 42 from the third output terminal 13 and the fourth output terminal 14 via the first node N1 and the second node N2. . Then (in the first period TP 1), the voltage error signal VDS is output from the comparator 42 to the memory unit 43. The memory unit 43 performs a count-up operation or a count-down operation according to the voltage error signal VDS in synchronization with the rising edge of the clock signal φOCLK, and determines and holds the count value as a digital control value.

  In the H2 period, the same operation as in the H1 period is performed.

  In this way, the timing circuit 16 performs only one of the operation for resetting the capacitance of the common mode detection unit 8 in the S1 period and the operation for canceling the offset of the differential amplification unit in the S2 period. Control the timing. When applied to the image sensor, the operation for determining the offset cancel control value is not performed during the horizontal line reading period, and the operation for determining the offset cancel control value is performed during the horizontal blanking period. . Thereby, the offset cancellation amount within one horizontal line can be kept constant.

  As described above, according to the present embodiment, the output common mode voltage of the differential input / output amplifier is set to a predetermined voltage and fluctuates with time in the low frequency band at the offset, which could not be canceled with high accuracy. Ingredients can be canceled. That is, according to the present embodiment, it is possible to improve the accuracy of processing for canceling the offset of the differential amplifier in the amplifier circuit.

  Further, when the amplifier circuit according to this embodiment is used for an A / D converter for signal processing of an image sensor or the like, it is possible to suppress striped image noise caused by 1 / f noise.

  In addition, this invention is not restrict | limited to said embodiment. For example, the memory unit in the offset canceling unit can be realized by a digital low-pass filter instead of the up / down counter. Further, the common mode detection unit and the common mode voltage control unit can also be realized in other forms such as a switched capacitor system.

  FIG. 6 shows another example of driving timing of the sample hold circuit. At this operation timing, the operation of resetting the capacitance of the common mode detection unit 8 is performed in the first half of all the sample periods (that is, the third period TP3a). On the other hand, the operation for determining the offset cancel control value is performed in the second half of the S2 period (that is, the first period TP1a). As described above, by causing the control signal φCM to fall to the non-active level sufficiently early with respect to the rising edge of the clock signal φOCLK, it is possible to reflect the offset cancellation error in the comparator output.

  Next, an example of an imaging system to which the sample hold circuit 300 is applied is shown in FIG. As shown in FIG. 7, the imaging system 90 mainly includes an optical system, an imaging sensor 86, and a signal processing unit. The optical system mainly includes a shutter 91, a lens 92, and a diaphragm 93. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the lens 92 on the optical path, and controls exposure. The lens 92 refracts the incident light and forms an image of the subject on the pixel array (imaging surface) of the imaging sensor 86. The diaphragm 93 is provided between the lens 92 and the image sensor 86 on the optical path, and adjusts the amount of light guided to the image sensor 86 after passing through the lens 92.

  The imaging sensor 86 converts the image of the subject formed in the pixel array into an image signal. The image sensor 86 reads out the image signal from the pixel array and outputs it.

  The imaging signal processing circuit 95 is connected to the imaging sensor 86 and processes the image signal output from the imaging sensor 86.

  The A / D converter 96 includes an amplifier circuit 100. The A / D converter 96 is connected to the imaging signal processing circuit 95, and the processed image signal (analog signal) output from the imaging signal processing circuit 95 is amplified by the amplification circuit 100 and the image signal (digital signal). ).

  The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

  The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97. The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generation unit 98 is connected to the imaging sensor 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the image sensor 86, the image signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging sensor 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal.

  The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole.

  The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  As described above, the amplification circuit 100 according to the present embodiment is mounted on the A / D converter 96 that converts the image signal (analog signal) of the imaging sensor 86 into an image signal (digital signal), thereby processing the processed image. It is possible to reduce low-frequency noise that degrades image quality. The A / D converter 96 may be configured as an LSI different from the semiconductor LSI configuring the image sensor 86 or may be configured as a so-called AD on-chip sensor bundled with the LSI configuring the image sensor 86. May be.

Claims (4)

It has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, performs an operation for correction in the first period, and continues to the first period An amplifier circuit that performs an amplification operation in a second period,
A differential voltage is received at two input terminals respectively connected to the first input terminal and the second input terminal, and a differential current corresponding to the differential voltage is connected to the first output terminal. A differential amplifier that outputs from a third output terminal and a fourth output terminal connected to the second output terminal;
A fixed voltage that fixes the voltages of the two input terminals to a reference voltage in the first period, and releases the fixed voltage of the two input terminals so that the amplification operation can be performed in the second period. And
Including a detection element, and in the first period, one end of the detection element is connected to a first node between the third output terminal and the first output terminal, and the other end of the detection element is connected to the first node. A detection circuit connected to a second node between a fourth output terminal and the second output terminal to detect a voltage difference between both ends of the detection element;
In the first period, as the operation for the correction, the voltage across the detection element detected by the detection circuit in a state where the voltages of the two input terminals are fixed to the reference voltage by the fixing unit. A correction operation including at least one of an operation of supplying a first correction current to the first node and an operation of supplying a second correction current to the second node so that the difference between the two is within an allowable value A correction unit that determines and holds a control value for performing the correction operation according to the control value held in the first period in the second period;
An amplifier circuit comprising: The correction unit is
A voltage comparison unit that compares the voltage at the one end of the detection element detected by the detection circuit with the voltage at the other end, and outputs a voltage error signal according to the comparison result;
A control value holding unit that determines and holds a digital control value according to a voltage error signal output from the voltage comparison unit;
A D / A converter that generates an analog control value by D / A converting the digital control value output from the control value holding unit;
A current generator that performs the correction operation according to the analog control value generated by the D / A converter;
The amplifier circuit according to claim 1, comprising: When the voltage error signal indicates that the current output from the first output terminal is greater than the current output from the second output terminal, the control value holding unit performs a count-up operation. When the voltage error signal indicates that the current output from the first output terminal is smaller than the current output from the second output terminal, a countdown operation is performed and the count value is converted to the digital value. Includes an up / down counter that outputs as a control value,
The amplifier circuit according to claim 2, wherein the current generation unit performs the correction operation according to an analog control value corresponding to a digital control value output from the up / down counter. An imaging sensor;
An optical system for forming an image on the imaging surface of the imaging sensor;
An A / D converter that includes the amplifier circuit according to any one of claims 1 to 3 and that performs A / D conversion on an image signal output from the imaging sensor;
An image signal processor that processes image signals A / D converted by the A / D converter to generate image data;
An imaging system comprising:

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