JP2011082391A - Solid-state imaging device and method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

A solid-state imaging device capable of reducing sensitivity nonuniformity and color nonuniformity and flattening a film formed on a multilayer wiring layer in an effective pixel region, and a manufacturing method thereof. provide.
In a solid-state imaging device in which a multilayer wiring layer (22b) in a peripheral circuit region (26) is formed higher than the multilayer wiring layer (22a) in a pixel region (25), a lateral groove (33) is formed on the side walls of the step portions of the multilayer wiring layers (22a, 22b). To do. As a result, in the step of forming the coating material on the multilayer wiring layers 22a and 22b, the coating material in the stepped portion is absorbed into the lateral groove 33. Thereby, the coating material formed on the multilayer wiring layer 22a in the pixel region 25 is formed flat.
[Selection] Figure 2

Description

  The present invention relates to a solid-state imaging device such as a CMOS image sensor or a CCD image sensor, a manufacturing method thereof, and an electronic apparatus.

  For example, in a solid-state imaging device such as a CMOS image sensor or a CCD image sensor, light is incident on a photodiode (photoelectric conversion unit) formed on the surface of a semiconductor substrate, and a video signal is generated by a signal charge generated by the photodiode. It is the composition which obtains.

  Conventionally, in such a solid-state imaging device, various proposals have been made in order to improve optical characteristics. A conventional solid-state imaging device will be described in detail below.

  FIG. 13 shows a schematic plan configuration of a solid-state imaging device 100 which is a conventional CMOS image sensor, and FIG. 14 shows a cross-sectional configuration along the line D-D.

  As shown in FIG. 13, a conventional solid-state imaging device 100 has a pixel region 103 and peripheral circuit regions such as a vertical drive circuit 104 and a horizontal drive circuit 105 on a substrate 101. In the pixel region 103, a plurality of pixels including a photodiode as a photoelectric conversion element and a pixel transistor (MOS transistor) are two-dimensionally arranged. Although not shown, the pixel area 103 is an effective pixel area for actually outputting a video signal, an invalid pixel area that does not output an actual video signal, and an optical for outputting a black level reference signal. It consists of a black area. The invalid pixel region and the optical black region are formed at desired positions around the effective pixel region.

  The cross-sectional configuration shown in FIG. 14 is a cross-sectional configuration between the pixel region 103, in particular, an effective pixel region 55 that outputs an actual video signal, and a peripheral circuit region 56 (the horizontal drive circuit 105 in this embodiment). is there. As shown in FIG. 14, in the effective pixel region 55, for example, a photodiode PD is formed on the surface of the silicon substrate 50. A multilayer wiring layer 52a in which three layers of wiring 1M, 2M, and 3M are formed via an interlayer insulating film 51 is formed on the silicon substrate 50, and a color filter 53 and an on-chip are formed on the multilayer wiring layer 52a. A lens 54 is configured.

  In the peripheral circuit region 56 (horizontal drive circuit 105), for example, a multilayer wiring layer 55b in which four layers of wirings 1M, 2M, 3M, and 4M are formed on the silicon substrate 50 via the interlayer insulating film 51 is configured. . Actually, in the effective pixel region 55, a plurality of pixel transistors are formed around the photodiode PD, but the illustration is omitted in FIG.

  In the effective pixel region 55, there is a demand for reducing the distance between the light irradiation position and the photodiode PD in order to efficiently irradiate the photodiode PD with a large amount of light. Further, in the peripheral circuit region 56, there is a demand for higher integration and higher functionality and downsizing by increasing the number of multilayer wiring layers 52b. For this reason, for example, the multilayer wiring layer 52a in the effective pixel region 55 is composed of three layers of wiring 1M, 2M, and 3M, and the multilayer wiring layer 52b in the peripheral circuit region 56 is composed of four layers of wiring 1M, 2M, 3M, Consists of 4M.

  In such a solid-state imaging device 100, the multilayer wiring layers 52a and 52b between the effective pixel region 55 and the peripheral circuit region 56 are different in the number of wirings stacked as shown in FIG. The resulting step is formed. As described above, when the color filter material 53a is applied to the entire upper layer in a state where there is a step between the effective pixel region 55 and the peripheral circuit region 56, the color filter material 53a is thickened on the step portion, and as a result, It is applied at an angle. The color filter 53 is formed at a desired position in the effective pixel region 55 by exposing and developing the color filter material 53a applied in an inclined manner. Since the applied color filter material 53a is applied with an inclination, the exposed and developed color filter 53 is also formed with an inclination.

  Further, after the color filter 53 is formed, the on-chip lens material 54a is applied to the entire surface. In this case as well, as in the case where the color filter material 53a is applied, the on-chip lens material 54a is thickened at the step portion, and as a result, is applied with an inclination. By patterning the inclined on-chip lens material 54 a, the on-chip lens 54 is formed on the effective pixel region 55. In this case, the on-chip lens 54 to be patterned is also formed to be inclined, which causes the condensing point to shift. In such a solid-state imaging device 100 in the conventional example, the light is not focused by the on-chip lens 54 at a desired position, and light does not enter the photodiode PD well, resulting in sensitivity unevenness and color unevenness.

  In the following Patent Document 1, in order to reduce the step between the effective pixel region and the peripheral circuit region as described above, a recess is provided in the insulating film in the multilayer wiring layer of the peripheral circuit region, and the wiring is fitted in the recess. The configuration to be included is described.

JP 2004-71931 A

  However, in the configuration of Patent Document 1, although the inclination of the on-chip lens or the like in the effective pixel region due to the step between the peripheral circuit region and the effective pixel region is reduced, it is not completely flattened. In addition, the configuration is not compatible until the number of wiring layers in the peripheral circuit portion increases.

  In view of the above-described points, the present invention flattens a film formed on a multilayer wiring layer in an effective pixel area, thereby reducing sensitivity unevenness and color unevenness and reducing the chip size. An apparatus and a manufacturing method thereof are provided. The present invention also provides an electronic apparatus using a solid-state imaging device with reduced sensitivity unevenness and color unevenness.

  In order to solve the above problems and achieve the object of the present invention, a solid-state imaging device of the present invention has the following configuration. First, a photoelectric conversion unit that is formed on a substrate and generates a signal charge corresponding to the amount of light, and a pixel region having pixels composed of a multilayer wiring layer formed on the substrate. Then, a multi-layer wiring layer formed around the pixel region and higher than the multi-layer wiring layer formed in the pixel region, and a lateral groove is formed on the side wall of the stepped portion between the multi-layer wiring layer formed in the pixel region. A peripheral circuit region having a multilayer wiring layer formed.

  In the solid-state imaging device of the present invention, in the configuration in which the multilayer wiring layer in the peripheral circuit region is formed higher than the multilayer wiring layer in the pixel region, the lateral groove is formed in the side wall of the step portion of the multilayer wiring layer. Thereby, in the step of forming the coating material on the upper part of the multilayer wiring layer, the coating material of the step portion is absorbed into the lateral groove. Thereby, the coating material formed on the multilayer wiring layer in the pixel region is formed flat.

  Moreover, the manufacturing method of the solid-state imaging device of this invention has the following processes. First, a photoelectric conversion unit that generates signal charges corresponding to the amount of light is formed on a substrate. Next, a multilayer wiring layer having a plurality of wirings is formed on a substrate including a pixel region in which the photoelectric conversion unit is formed and a peripheral circuit region formed around the pixel region. Next, the multilayer wiring layer in the pixel region is lowered, and a lateral groove is formed on the side wall of the step portion between the multilayer wiring layer in the pixel region and the multilayer wiring layer in the peripheral circuit region.

  In the method for manufacturing a solid-state imaging device according to the present invention, in the configuration in which the multilayer wiring layer in the peripheral circuit region is formed higher than the multilayer wiring layer in the pixel region, the lateral groove is formed on the side wall of the step portion of the multilayer wiring layer. Thus, when the coating material is formed on the multilayer wiring layer after the multilayer wiring layer is formed, the coating material at the step portion is absorbed into the lateral groove. Thereby, the coating material formed on the multilayer wiring layer in the pixel region can be formed flat.

  In addition, the electronic apparatus of the present invention includes an optical lens, a solid-state imaging device to which light collected by the optical lens is incident, and a signal processing circuit that processes an output signal of the solid-state imaging device. The solid-state imaging device has the above-described configuration of the present invention.

  According to the present invention, a solid-state imaging device with reduced sensitivity unevenness and color unevenness can be obtained without increasing the number of manufacturing steps, and an image quality can be improved in an electronic apparatus using the solid-state imaging device.

1 is an overall schematic plan configuration of a solid-state imaging device according to a first embodiment of the present invention. It is a schematic sectional block diagram which follows the AA line of FIG. FIGS. 3A and 3B are manufacturing process diagrams (part 1) illustrating a manufacturing method of the solid-state imaging device according to the first embodiment. FIGS. D and E are manufacturing process diagrams (part 2) illustrating the manufacturing method of the solid-state imaging device according to the first embodiment. FIGS. 8A and 8B are manufacturing process diagrams (part 3) illustrating the manufacturing method of the solid-state imaging device according to the first embodiment. It is an example which shows the formation area of a groove part. It is another example which shows the formation area of a groove part. FIGS. 9A and 9B are manufacturing process diagrams (part 1) illustrating a method for manufacturing a solid-state imaging device according to a second embodiment of the present invention. FIGS. C and D are manufacturing process diagrams (part 2) illustrating the manufacturing method of the solid-state imaging device according to the second embodiment of the present invention. E and F are manufacturing process diagrams (part 3) illustrating the manufacturing method of the solid-state imaging device according to the second embodiment of the present invention. A and B are manufacturing process diagrams illustrating a method for manufacturing a solid-state imaging device according to a third embodiment of the present invention. It is a schematic block diagram of the electronic device which concerns on the 4th Embodiment of this invention. It is a schematic plane block diagram of the conventional solid-state imaging device. FIG. 14 is a schematic cross-sectional configuration diagram along the line DD in FIG. 13.

Hereinafter, an example of a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus according to an embodiment of the present invention will be described with reference to FIGS. Embodiments of the present invention will be described in the following order. In addition, this invention is not limited to the following examples.
1. 1. First embodiment: Solid-state imaging device 1-1 Configuration of entire solid-state imaging device 1-2 Configuration of main part 1-3 Manufacturing method of solid-state imaging device 2. Second embodiment: solid-state imaging device Third Embodiment: Solid-state imaging device4. Fourth embodiment: electronic device

<1. First Embodiment: Solid-State Imaging Device>
[1-1 Overall Configuration of Solid-State Imaging Device]
FIG. 1 is a schematic plan configuration of a solid-state imaging device to which an embodiment of the present invention can be applied. The solid-state imaging device 1 of this embodiment is an example of a CMOS image sensor. For example, a pixel region 3 in which pixels 2 including a plurality of photodiodes are arranged in a two-dimensional array on a substrate 11 made of silicon, a vertical drive circuit 4 as a peripheral circuit thereof, a column signal processing circuit 5, It comprises a horizontal drive circuit 6, an output circuit 7, a control circuit 8 and the like.

  The pixel area 3 is composed of an effective pixel area that outputs an actual video signal, an invalid pixel area that is not used for actual video signal output, and an optical black pixel area that outputs a black level reference signal. The The invalid pixel region and the optical black pixel region are formed at desired positions around the effective pixel region, and the positions can be changed according to the characteristics of the device.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock To do. Then, the clock signal and control signal generated there are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6 and the like.

  The vertical drive circuit 4 is configured by a shift register, for example, and selectively scans each pixel 2 in the pixel region 3 in the vertical direction sequentially in units of rows. Then, a pixel signal based on the signal charge generated according to the amount of light received in the photodiode of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line 9.

  For example, the column signal processing circuit 5 is arranged for each column of the pixels 2, and an optical black pixel (not shown, but around the effective pixel region) Signal processing such as noise removal and signal amplification is performed by the signal from At the output stage of the column signal processing circuit 5, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.

The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.

In the following description, the control circuit 8, the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the output circuit are collectively referred to as a peripheral circuit region 26.
Moreover, the solid-state imaging device in 1st-2nd embodiment demonstrated below comprises the solid-state imaging device 1 in FIG. 1, and the cross-sectional structure differs. Since the configuration other than the cross-sectional configuration is the same as that of FIG. 1, in the first and second embodiments, only the cross-sectional configuration of the main part is shown, and the description of the other configuration is omitted.

[1-2 Configuration of main parts]
FIG. 2 shows a schematic cross-sectional configuration of the solid-state imaging device according to the first embodiment of the present invention. The cross-sectional configuration shown in FIG. 2 is, for example, a cross-sectional configuration along the line AA in FIG. 1, and the pixel region 3 (particularly the effective pixel region 25) and the peripheral circuit region 26 (in FIG. 1, the horizontal drive circuit 6). ) And a cross section taken on the line.

  As shown in FIG. 2, in the effective pixel region 25, for example, a photodiode PD serving as a photoelectric conversion unit is formed on the surface of the silicon substrate 20, and two layers of wirings 1 </ b> M and 2 </ b> M are interposed above the interlayer insulating film 21. Thus, the multilayer wiring layer 22a formed is formed. A color filter 23 and an on-chip lens 24 are formed on the multilayer wiring layer 22a. The wirings 1M and 2M of the multilayer wiring layer 22a in the effective pixel region 25 are formed at positions that do not block the light incident direction directly above the photodiode PD.

  In the peripheral circuit region 26 (horizontal drive circuit 6), similarly to the effective pixel region 25, a multilayer wiring layer in which four layers of wirings 1M, 2M, 3M, and 4M are formed on the silicon substrate 20 via the interlayer insulating film 21. 22b is configured.

  Actually, in the effective pixel region 25, a plurality of pixel transistors are formed around the photodiode PD, but the illustration is omitted in FIG.

  In the solid-state imaging device 1 according to the present embodiment, a bow-shaped lateral groove 33 is formed on the side wall of the step portion between the multilayer wiring layer 22 a in the effective pixel region 25 and the multilayer wiring layer 22 b in the peripheral circuit region 26. The lateral groove 33 formed on the side wall of the step portion is formed continuously or intermittently in the boundary region between the effective pixel region 25 and the peripheral circuit region 26. In addition, the lateral groove 33 is a step between the multilayer wiring layers 22a and 22b in the step of applying an organic material film constituting the color filter 23 and the on-chip lens 24 on the multilayer wiring layer 22a in the effective pixel region 25. The film is formed for the purpose of alleviating the film thickness unevenness caused by it.

[1-3 Manufacturing method]
Next, a method for manufacturing the solid-state imaging device 1 according to this embodiment shown in FIG. 2 will be described with reference to FIGS. 3 to 5, as in FIG. 2, the manufacturing method will be described by taking a cross section along the line AA in FIG. 1 as an example.

First, as shown in FIG. 3A, a photodiode PD serving as a photoelectric conversion unit is formed on the surface of the silicon substrate 20 in the effective pixel region 25, and multilayer wiring layers 22 a and 22 b are formed on the silicon substrate 20. The multilayer wiring layers 22a and 22b of the present embodiment can be formed by alternately forming the wirings 1M to 4M and the interlayer insulating film 21.
In the present embodiment, the multilayer wiring layer 22b in the peripheral circuit region 26 is composed of four layers of wiring 1M to 4M, and the multilayer wiring layer 22a in the effective pixel region 25 is composed of two layers of wiring 1M and 2M. The wirings 1M and 2M in the effective pixel region 25 and the wirings 1M to 4M in the peripheral circuit region 26 are formed in the same process and are formed in the same layer.

  In the present embodiment, the wirings 1M to 4M are made of copper, a wiring groove is formed in the interlayer insulating film 21, and copper is embedded through a barrier metal layer made of tantalum (not shown) having diffusion resistance. It is formed by the so-called damascene method. A diffusion prevention film 19 for preventing copper diffusion is formed on the upper part of the wiring made of copper. The diffusion prevention film 19 is made of, for example, silicon carbide, silicon nitride, or the like.

  In FIG. 3A, only the photodiode PD and the multilayer wiring layers 22a and 22b formed on the surface of the silicon substrate 20 are illustrated for simplicity, but actually, a plurality of pixel transistors (not illustrated) are configured.

  After the multilayer wiring layers 22a and 22b are formed, as shown in FIG. 3A, a resist film 27 having an effective pixel region 25 opened on the multilayer wiring layer 22b is formed by photolithography.

  Then, as shown in FIG. 3B, the interlayer insulating film 21 and the like formed on the wiring 2M is removed from the multilayer wiring layer 22a of the effective pixel region 25 by etching through the resist film 27, and effective. The multilayer wiring layer 22a in the pixel region 25 is lowered. In this etching process, the upper wiring 2M of the effective pixel region 25 is not exposed.

  Further, in this etching process, side etching is performed so as to enter the peripheral circuit region 26 side from the end of the resist film 27, and the boundary region between the effective pixel region 25 and the peripheral circuit region 26 is processed into a bow shape, thereby forming a lateral groove. 33 is formed. Etching for forming the lateral grooves 33 in such a bow shape can be easily performed by using, for example, a wet etching method using a hydrofluoric acid-based etching solution. Further, in addition to wet etching, a dry etching method may be used. By excessively diffusing active species generated by plasma discharge, the etching process proceeds in the lower region at the end of the resist film 27, resulting in a bowing shape. It is also possible to form the horizontal groove 33. The lateral grooves 33 are formed so as not to reach the wirings 1M to 4M formed in the multilayer wiring layer 22b in the peripheral circuit region 26.

  Then, as shown in FIG. 3B, multilayer wiring layers 22 a and 22 b having different heights are formed in the effective pixel region 25 and the peripheral circuit region 26 by such etching processing, and the multilayer wiring layers 22 a and 22 b are formed in the boundary region. Boeing lateral grooves 33 are formed on the side wall of the stepped portion. More specifically, the lateral groove 33 is a groove carved on the peripheral circuit region 26 side starting from a step at the boundary between the effective pixel region 25 and the peripheral circuit region 26. Further, the lateral groove 33 is preferably formed in a range of a lateral width of 20 nm to 100 μm and a height of 20 nm to 20 μm.

  Next, as shown in FIG. 3C, the resist film 27 is removed. In the present embodiment example, the multilayer wiring layers 22a and 22b having different heights are formed in the peripheral circuit region 26 and the effective pixel region 25 as described above. As a result, in the effective pixel region 25, the distance between the light incident surface and the photodiode PD is shortened as much as possible, so that the light collection characteristic is improved. Further, according to such a configuration, since the wirings 1M to 4M are more multilayered in the multilayer wiring layer 22b in the peripheral circuit region 26, integration is achieved.

  Next, as shown in FIG. 4D, a color filter material 28 is applied to the entire surface including the effective pixel region 25 and the peripheral circuit region 26 above the multilayer wiring layers 22a and 22b. The color filter material 28 is composed of, for example, a photosensitive resist mixed with a desired dye. In this embodiment, a lateral groove 33 is formed on the side walls of the stepped portions of the multilayer wiring layers 22 a and 22 b formed between the effective pixel region 25 and the peripheral circuit region 26. Thereby, when the color filter material 28 is applied to the whole, the color filter material 28 enters the lateral groove 33. As a result, the color filter material 28 that has been applied thickly in the effective pixel region 25 in the vicinity of the step portion is absorbed by the lateral groove 33. Thereby, the inclination of the color filter material 28 formed in the boundary region between the peripheral circuit region 26 and the effective pixel region 25 is reset by the lateral groove 33.

  That is, conventionally, as shown in FIG. 14, the color filter material 53a is thickly applied to the step portion, so that the color filter 53 to be formed is gently inclined from the peripheral circuit region 56 to the effective pixel region 55. The film was formed to have However, in this embodiment, the color filter material 28 at the step portion that has caused the inclination enters the lateral groove 33. Thereby, the inclination of the color filter material 28 does not shift into the effective pixel region 25. As a result, in the effective pixel region 25, the color filter material 28 applied on the multilayer wiring layer 22a is formed flat.

Next, as shown in FIG. 4E, the color filter 23 is formed at a desired position above the photodiode PD formed in the effective pixel region 25 by exposing and developing the color filter material 28. The color filter 23 is formed for each color. By repeating the steps of FIGS. 4D and 4E, for example, as shown in FIG. 5F, for example, red (R), blue (B), green (G) The color filter 23 is sequentially formed for each pixel.
At this time, since the color filter 23 is not necessary on the multilayer wiring layer 22b in the peripheral circuit region 26, the color filter material 28 is removed.

  Next, as shown in FIG. 5G, an on-chip lens material 29 is applied to the entire surface including the effective pixel region 25 and the peripheral circuit region 26. Also in this case, the on-chip lens material 29 is absorbed by the lateral grooves 33 because the lateral grooves 33 are formed on the side walls of the stepped portions of the multilayer wiring layers 22a and 22b. As a result, the inclination of the on-chip lens material 29 is reset in the lateral groove 33 in the boundary region between the peripheral circuit region 26 and the effective pixel region 25. For this reason, the on-chip lens material 29 applied to the upper portion of the multilayer wiring layer 22a in the effective pixel region 25 is formed flat.

  Thereafter, by patterning the on-chip lens material 29, the on-chip lens 24 is formed on the photodiode PD in the effective pixel region 25 as shown in FIG. Through the above steps, the solid-state imaging device 1 of the present embodiment example is completed.

  In the present embodiment example, as shown in FIG. 5G, in the effective pixel region 25, the on-chip lens material 29 is formed flat without being affected by the step portions with the multilayer wiring layers 22a and 22b. Thereby, the patterned on-chip lens 24 is formed on the color filter 23 without being inclined. Further, since the color filter 23 is also formed flat before the on-chip lens 24 is formed, there is no influence of the inclination of the color filter 23 that has occurred in the past. In the effective pixel region 25, the volume of the lateral groove 33 necessary for applying the coating material flatly varies depending on the height of the step and the distance between the peripheral circuit region 26 and the effective pixel region 25. In the present embodiment, for example, by forming the lateral groove 33 in the range of a lateral width of 20 nm to 100 μm and a height of 20 nm to 20 μm, the coating material accumulated in the stepped portion can be suitably absorbed, and the effective pixel region 25 The coating material can be applied flatly.

  As described above, in this embodiment, the bow-shaped lateral groove 33 is formed on the side walls of the stepped portions of the multilayer wiring layers 22 a and 22 b between the effective pixel region 25 and the peripheral circuit region 26. As a result, a coating material such as the color filter material 28 or the on-chip lens material 29 can be applied evenly on the multilayer wiring layer 22a in the effective pixel region 25 without any unevenness. Then, since the color filter 23 and the on-chip lens 24 in the effective pixel region 25 in the vicinity of the peripheral circuit region 26 are formed with high accuracy, it is possible to reduce the deviation of the light collection point of the on-chip lens 24.

  As described above, in the solid-state imaging device 1 according to the present embodiment, the sensitivity unevenness and the color unevenness are reduced and the image quality is improved in the pixels at the end of the pixel region 3, that is, the pixels 2 in the vicinity of the peripheral circuit region 26. You can plan.

  In an actual solid-state imaging device, an invalid pixel region that does not output an actual video signal is formed around the effective pixel region 25 as the pixel region 3. In order to prevent the ineffective pixel region from being affected by the coating unevenness caused by the step portions of the multilayer wiring layers 22a and 22b between the peripheral circuit region 26 and the pixel region 3 in the conventional art. It is provided. By providing the lateral groove 33 between the peripheral circuit region 26 and the pixel region 3, the film thickness of the film formed on the multilayer wiring layer 22 a in the pixel region 3 is made constant. As a result, a flat film can be formed on the multilayer wiring layer 22a in the pixel region 3 adjacent to the peripheral circuit region 26 without uneven coating, and the color filter 23, the on-chip lens 24, etc. can be formed with high accuracy. can do. Thereby, the invalid pixel area of the pixel area 3 adjacent to the peripheral circuit area 26 that could not be used conventionally can be reduced, and the chip size can be reduced. And since the chip size can be reduced, the yield is improved in the manufacturing process.

  Similarly, the distance between the pixel region 3 and the peripheral circuit region 26 can be shortened, and this also improves profitability by reducing the chip size.

  As described above, a groove is formed in the multilayer wiring layer 22a between the peripheral circuit region 26 and the pixel region 3 and closer to the pixel region 3 (effective pixel region 25) than the stepped portions of the multilayer wiring layers 22a and 22b. As a result, the chip size can be reduced and the yield can be improved. Thereby, cost reduction is achieved.

  Further, in the method for manufacturing the solid-state imaging device 1 according to the present embodiment, the lateral groove 33 can be formed in the step of etching and removing the multilayer wiring layer 22a in the effective pixel region 25, so that the lateral groove 33 is formed. There is no need to provide a separate process. For this reason, when forming the lateral grooves 33, it is not necessary to separately form a resist film, etch the lateral grooves 33, peel off the resist film, or the like in separate steps. For this reason, since the number of processes does not increase, the manufacturing cost is not different from the conventional method. That is, film thickness unevenness due to a step in the boundary region between the effective pixel region 25 and the peripheral circuit region 26 can be suppressed without an increase in manufacturing cost due to an increase in the number of processes.

  In this embodiment, the multilayer wiring layer 22b on the peripheral circuit region 26 side is configured by four layers of wiring 1M to 4M, and the multilayer wiring layer 22a on the pixel region 3 side is configured by two layers of wirings 1M and 2M. However, it is not limited to this configuration. The configuration of the present embodiment can be applied even when the number of wiring layers in the peripheral circuit region 26 is further increased, and can be applied regardless of the number of wiring layers.

Further, when the peripheral circuit region 26 is formed only in a region close to one side of the pixel region 3 like the solid-state imaging device 60 shown in FIG. The lateral groove 33 may be provided only between the pixel region 3 and the peripheral circuit region 26.
Further, as in the solid-state imaging device 61 shown in FIG. 7, for example, if the peripheral circuit region 26 is formed in a region close to the two sides of the pixel region 3, the peripheral circuit region 26 is formed close to the two sides. A lateral groove 33 may be formed between the peripheral circuit region 26 and the pixel region 3.

  As shown in FIG. 6 and FIG. 7, the layout that forms the lateral groove 33 is based on various configurations of the solid-state imaging device, and the multilayer wiring layers 22a, 22a, 22b in the peripheral circuit region 26 and the pixel region 3 are arranged. What is necessary is just to comprise the horizontal groove 33 in the area | region where a level | step difference arises between 22b.

  Further, as shown in FIGS. 6 and 7, even when the peripheral circuit region is formed only in part, the lateral groove 33 may be formed around the entire effective pixel region.

  In the present embodiment example, a configuration between the effective pixel region 25 of the pixel region 3 and the peripheral circuit region 26 is described. In FIGS. 6 and 7, a lateral groove is formed in the boundary region between the pixel region 3 and the peripheral circuit region 26. Although the example which comprises 33 is set, the position which forms the horizontal groove 33 is not restricted to this. By forming the lateral groove 33 in a portion where there is a step portion between the pixel region 3 and the pixel region 3, the same effect as in this embodiment can be obtained.

<2. Second Embodiment: Solid-State Imaging Device>
Next, a solid-state imaging device according to the second embodiment of the present invention will be described. 8 to 10 are manufacturing process diagrams of the solid-state imaging device according to this embodiment. 8 to 10, parts corresponding to those in FIGS. 3 to 5 are denoted by the same reference numerals, and redundant description is omitted.

  In this embodiment, after the multilayer wiring layers 22a and 22b are formed in the same manner as in the first embodiment, as shown in FIG. 8A, for example, silicon nitride (SiN) is formed on the entire surface of the multilayer wiring layers 22a and 22b. A stopper film 34 made of is formed. In this embodiment, silicon nitride is used as the stopper film 34, but silicon carbide (SiC) or the like can also be used.

  Next, as shown in FIG. 8B, a resist film 35 in which the effective pixel region 25 is opened is formed on the multilayer wiring layer 22b by photolithography.

  Next, as shown in FIG. 9C, the stopper film 34 in the effective pixel region 25 exposed by the resist film 35 is removed by dry etching.

  Next, as shown in FIG. 9D, wet etching is performed using the remaining stopper film 34 and resist film 35 as a mask. As a result, the interlayer insulating film 21 and the like formed on the wiring 2M is removed from the multilayer wiring layer 22b in the effective pixel region 25, and the multilayer wiring layer 22a in the effective pixel region 25 is lowered. Further, in this etching process, side etching is performed so as to enter the peripheral circuit region 26 side from the end of the resist film 35, and the boundary region between the effective pixel region 25 and the peripheral circuit region 26 is processed into a bow shape, thereby forming a lateral groove. 33 is formed.

  Next, as shown in FIG. 10E, only the resist film 35 is removed.

  Then, in the same process as in FIGS. 4D to 5G of the first embodiment, as shown in FIG. 10F, the color filter 23 and the on-chip lens 24 are formed on the multilayer wiring layer 22a in the effective pixel region 25. To do.

  According to this embodiment, the lateral groove 33 can be stably formed by performing a multi-stage etching process in which the stopper film is formed by dry etching and the lateral groove is formed by wet etching. In the example in which the stopper film is not formed as in the first embodiment, the film on the upper surface of the lateral groove 33 depends on the etching conditions (for example, the etching conditions for over-etching and the etching conditions for adding a lot of side etching). It may become too thin and problems with the robustness of the membrane structure may occur. In the present embodiment, by forming the stopper film 34, excessive side etching near the upper surface can be prevented, and the lateral groove 33 can be stably formed.

  In addition, the same effects as those of the first embodiment can be obtained.

<3. Third Embodiment: Solid-State Imaging Device>
Next, a solid-state imaging device according to the third embodiment of the present invention will be described. 11 and 12 are manufacturing process diagrams of the solid-state imaging device according to the present embodiment. 11 and 12, parts corresponding to those in FIG. 3 to FIG.

  In this embodiment, in the etching process of FIG. 3B, the diffusion prevention film 19 is further etched by using the etching rate difference between the interlayer insulation film 21 and the diffusion prevention film 19 formed between the interlayer insulation films 21. This is an example in which etching is performed under the conditions for removal. For this reason, as shown in FIG. 11A, in the lateral groove 33, the diffusion preventing film 19 is etched away to a deeper position on the peripheral circuit region 26 side than the interlayer insulating film 21.

  Also in the present embodiment example, after the etching process shown in FIG. 11A, in the same process as that in FIGS. 4D to 5G of the first embodiment, as shown in FIG. 11B, on the multilayer wiring layer 22a in the effective pixel region 25. The color filter 23 and the on-chip lens 24 are formed.

  According to the present embodiment, the cavity region can be increased by the diffusion prevention film 19 that has been etched away deeper in the lateral groove 33 formed on the side wall of the stepped portion. The increase in the hollow area of the lateral groove 33 increases the volume of the coating material absorbed in the lateral groove 33 when a resist film for forming a color filter or a coating material to be a planarizing film is applied. For this reason, when these coating materials are thermally contracted, the amount of contraction in the lateral grooves 33 is relatively increased, the flatness of the stepped portion can be improved, and the effect of suppressing film thickness unevenness can be enhanced. .

  In addition, the same effects as those of the first embodiment can be obtained.

  In the first to third embodiments described above, the case where the present invention is applied to a CMOS type solid-state imaging device in which unit pixels that detect signal charges corresponding to the amount of incident light as physical quantities are arranged in a matrix has been described as an example. . However, the present invention is not limited to application to a CMOS type solid-state imaging device. Further, the present invention is not limited to a column type solid-state imaging device in which column circuits are arranged for each pixel column of a pixel portion in which pixels are formed in a two-dimensional matrix.

  The present invention is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image, but is a solid that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. The present invention can also be applied to an imaging device. In a broad sense, the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as a fingerprint detection sensor that senses other physical quantity distributions such as pressure and capacitance and captures images as images.

Furthermore, the present invention is not limited to the solid-state imaging device that sequentially scans each unit pixel of the pixel unit in units of rows and reads a pixel signal from each unit pixel. The present invention is also applicable to an XY address type solid-state imaging device that selects an arbitrary pixel in pixel units and reads out signals from the selected pixels in pixel units.
Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which a pixel portion and a signal processing portion or an optical system are packaged together. Good.

  In addition, the present invention is not limited to application to a solid-state imaging device, but can also be applied to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

<4. Fourth Embodiment: Electronic Device>
Next, an electronic apparatus according to a fourth embodiment of the present invention will be described. FIG. 12 is a schematic configuration diagram of an electronic device 200 according to the third embodiment of the present invention.
An electronic apparatus 200 according to the present embodiment shows an embodiment when the solid-state imaging device 1 according to the first embodiment of the present invention described above is used in an electronic apparatus (camera).

  The electronic apparatus 200 according to the present embodiment includes the solid-state imaging device 1, an optical lens 210, a shutter device 211, a drive circuit 212, and a signal processing circuit 213.

The optical lens 210 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. As a result, the signal charge is accumulated in the solid-state imaging device 1 for a certain period.
The shutter device 211 controls a light irradiation period and a light shielding period for the solid-state imaging device 1.
The drive circuit 212 supplies drive signals that control the transfer operation of the solid-state imaging device 1 and the shutter operation of the shutter device 211. Signal transfer of the solid-state imaging device 1 is performed by a drive signal (timing signal) supplied from the drive circuit 212. The signal processing circuit 213 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  In the electronic apparatus 200 according to the present embodiment, since the sensitivity unevenness and the color unevenness are reduced in the solid-state imaging device 1, the image quality can be improved.

  The electronic device 200 to which the solid-state imaging device 1 can be applied is not limited to a camera, but can be applied to an imaging device such as a digital still camera and a camera module for mobile devices such as a mobile phone.

  In the present embodiment example, the solid-state imaging device 1 is configured to be used in an electronic device, but the solid-state imaging device manufactured in the second embodiment or the third embodiment described above can also be used.

DESCRIPTION OF SYMBOLS 1 .... Solid-state imaging device 2 .... Pixel 3 .... Pixel area 4 .... Vertical drive circuit 5 .... Column signal processing circuit 6 .... Horizontal drive circuit 7 .... Output circuit 8 .... Control circuit 9 .... Vertical signal line 10..Horizontal signal line 11..Substrate 19..Diffusion prevention film 20..Silicone substrate 21..Interlayer insulating film 22a..Multilayer wiring layer 22b..Multilayer wiring layer 23..Color filter 24..On-chip lens 25 .. Effective pixel area 26 .. Peripheral circuit area 27 .. Resist film 28 .. Color filter material 29 .. On-chip lens material 33 .. Lateral groove 34 .. Stopper film 35 .. Resist film

Claims (6)

A photoelectric conversion unit that is formed on the substrate and generates a signal charge according to the amount of light; and a pixel region having a pixel composed of a multilayer wiring layer formed on the substrate;
A multilayer wiring layer formed around the pixel region and higher than the multilayer wiring layer formed in the pixel region, wherein a lateral groove is formed on a side wall of a step portion between the multilayer wiring layer formed in the pixel region. A peripheral circuit region having a multilayer wiring layer formed;
A solid-state imaging device. The multilayer wiring layer has a configuration in which an interlayer insulating film and a wiring made of a metal material formed in a desired shape via a diffusion prevention film are alternately stacked on the interlayer insulating film. The solid-state imaging device according to claim 1, wherein the diffusion preventing film is etched away to a position deeper on the peripheral circuit region side than the interlayer insulating film. Forming a photoelectric conversion unit that generates a signal charge corresponding to the amount of light on the substrate;
Forming a multilayer wiring layer having a plurality of wirings on a substrate including a pixel region in which the photoelectric conversion unit is formed and a peripheral circuit region formed around the pixel region;
Lowering the multilayer wiring layer in the pixel region, and forming a lateral groove in the side wall of the step portion between the multilayer wiring layer in the pixel region and the multilayer wiring layer in the peripheral circuit region;
A method for manufacturing a solid-state imaging device. Before lowering the multilayer wiring layer in the pixel region, a stopper film is formed on the multilayer wiring layer formed in the peripheral circuit region, and a resist film is further formed on the stopper film.
4. The solid-state imaging device according to claim 3, wherein the step of lowering the multilayer wiring layer in the pixel region and the step of forming a lateral groove on the side wall of the stepped portion are performed by etching using the stopper film and a resist film as a mask. Production method. The multilayer wiring layer is formed by alternately laminating an interlayer insulating film and a wiring made of a metal material formed in a desired shape via a diffusion prevention film on the interlayer insulating film,
4. In the formation of the lateral groove, the diffusion prevention film is etched and removed to a deeper position on the peripheral circuit region side than the interlayer insulation film using a difference in etching rate between the diffusion prevention film and the interlayer insulation film. Or the manufacturing method of the solid-state imaging device of 4. An optical lens,
A solid-state imaging device on which light collected by the optical lens is incident, and formed from a photoelectric conversion unit that generates a signal charge according to the amount of light, and a multilayer wiring layer formed on the substrate A pixel region having a pixel and a multilayer wiring layer formed around the pixel region and higher than the multilayer wiring layer formed in the pixel region, wherein the multilayer wiring layer is formed in the pixel region. A solid-state imaging device having a peripheral circuit region having a multilayer wiring layer in which a lateral groove is formed on the side wall of the stepped portion therebetween,
A signal processing circuit for processing an output signal of the solid-state imaging device;
Electronic equipment comprising.

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