JP2011082360A - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device in which high-density carbon nanotubes can be easily used for wiring is provided.
A via hole is formed in an insulating film, and a catalyst portion is formed in the via hole and on the insulating film. The catalyst part 12 on the insulating film 7 is deactivated, and carbon nanotubes are grown in the via hole 9 starting from the catalyst part 12 in the via hole 9.
[Selection] Figure 1C

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, techniques using carbon nanotubes for wiring of large-scale integrated circuits (LSIs) have been proposed. For example, a technique has been proposed in which CMP is performed after carbon nanotubes are grown in the vertical direction in via holes and fixed with SOD (spin on dielectric) or the like. A technique for cutting carbon nanotubes by ion irradiation has also been proposed.

  However, with conventional techniques, it is difficult to use high-density carbon nanotubes for wiring. For example, in the technique using the SOD, when high-density carbon nanotubes are grown, uniform application of SOD becomes difficult. Moreover, the cost required for CMP is large.

JP 2007-26839 A JP 2000-22305 A JP 2008-41954 A JP 2008-258187 A

  An object of the present invention is to provide a method for manufacturing a semiconductor device in which high-density carbon nanotubes can be easily used for wiring.

  In one aspect of the method for manufacturing a semiconductor device, a via hole is formed in the insulating film, and a catalyst portion is formed in the via hole and on the insulating film. The catalyst part on the insulating film is deactivated, and carbon nanotubes are grown in the via hole starting from the catalyst part in the via hole.

  According to the semiconductor device manufacturing method and the like, the carbon nanotube can be easily formed in the via hole. Therefore, high-density carbon nanotubes can be easily used for wiring.

FIG. 6 is a cross-sectional view showing the manufacturing direction of the semiconductor device according to the first embodiment in the order of steps. FIG. 1B is a cross-sectional view illustrating the manufacturing direction of the semiconductor device in order of processes following FIG. 1A. FIG. 2B is a cross-sectional view illustrating the manufacturing direction of the semiconductor device in order of processes following FIG. 1B. FIG. 2C is a cross-sectional view illustrating the manufacturing direction of the semiconductor device in order of processes following FIG. 1C. FIG. 2D is a cross-sectional view illustrating the manufacturing direction of the semiconductor device in order of processes following FIG. 1D. It is sectional drawing which shows the manufacture direction of the semiconductor device which concerns on 2nd Embodiment in process order. It is sectional drawing which shows the manufacturing direction of the semiconductor device which concerns on 3rd Embodiment in order of a process. FIG. 3B is a cross-sectional view illustrating the manufacturing direction of the semiconductor device in order of processes following FIG. 3A. It is a figure which shows the scanning electron micrograph of the carbon nanotube before and behind ion milling.

  Hereinafter, embodiments will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. 1A to 1E are cross-sectional views illustrating the manufacturing direction of the semiconductor device according to the first embodiment in the order of steps.

  First, as shown in FIG. 1A, an element isolation insulating film 2 is formed on the surface of a substrate 1 such as a semiconductor substrate, and a semiconductor such as a transistor Tr is formed in an element active region defined by the element isolation insulating film 2. An element is formed. Next, an interlayer insulating film 3 that covers the transistor Tr and the like is formed on the substrate 1. As the interlayer insulating film 3, a silicon oxide film is formed by a chemical vapor deposition (CVD) method using, for example, a silane-based gas or a tetraethoxysilane (TEOS) gas. Thereafter, an opening reaching the source / drain of the transistor Tr is formed in the interlayer insulating film 3, and the conductive plug 4 is formed therein. Subsequently, a conductive film 5 a in contact with the conductive plug 4 is formed on the interlayer insulating film 3. In forming the conductive film 5a, for example, a tantalum (Ta) film and a copper (Cu) film are formed in this order by a sputtering method.

  Next, as shown in FIG. 1A (b), the conductive film 5a is patterned by, for example, a photolithography method, and the wiring 5 electrically connected to the conductive plug 4 is formed. The line width of the wiring 5 is, for example, several μm or less, for example, about 100 nm.

  Thereafter, as shown in FIG. 1A (c), a diffusion prevention film 6 covering the wiring 5 is formed on the interlayer insulating film 3. As the diffusion preventing film 6, for example, a silicon nitride film having a thickness of 50 nm to 100 nm is formed. Subsequently, an interlayer insulating film 7 is formed on the diffusion preventing film 6. As the interlayer insulating film 7, for example, a silicon oxide film is formed by plasma CVD using TEOS gas. The thickness of the interlayer insulating film 7 is about 200 nm, for example. Next, a resist pattern 8 having an opening 8 a that exposes a region in the interlayer insulating film 7 where a via hole is to be formed is formed on the interlayer insulating film 7.

  Thereafter, as shown in FIG. 1B (d), the interlayer insulating film 7 is etched using the resist pattern 8 as a mask, thereby forming an opening 7a in the interlayer insulating film 7. Examples of the etching method include dry etching such as a reactive ion etching method using a fluorine-based gas and a plasma etching method. Alternatively, wet etching using hydrofluoric acid may be performed.

  Subsequently, as shown in FIG. 1B (e), the resist pattern 8 is removed. Next, the diffusion preventing film 6 is etched using the interlayer insulating film 7 as a mask, thereby forming an opening 6 a in the diffusion preventing film 6. As a result, the via hole 9 including the openings 6a and 7a and exposing a part of the wiring 5 is formed. Examples of the etching method include a wet etching method using phosphoric acid or the like.

  Next, as shown in FIG. 1B (f), a barrier film 10 is formed on the upper surface of the interlayer insulating film 7 and the bottom surface of the via hole 9. As the barrier film 10, for example, a tantalum (Ta) film or a tantalum nitride (TaN) film is formed. Thereafter, a contact film 11 is formed on the barrier film 10. For example, titanium (Ti) or titanium nitride (TiN) is formed as the contact film 11. The barrier film 10 functions as a barrier against Cu diffusion in the wiring 5. The contact film 11 ensures good electrical and mechanical connection between a via formed later and the barrier film 10. Further, the barrier film 10 and the contact film 11 also function as a catalyst supporting film that supports catalyst particles to be formed later. The formation method of the barrier film 10 and the contact film 11 is not particularly limited. For example, the barrier film 10 and the contact film 11 are preferably formed by a method having high growth anisotropy in a direction perpendicular to the surface of the substrate 1. This is because the barrier film 10 and the contact film 11 may be formed also on the side surface of the via hole 9, but the barrier film 10 and the contact film 11 formed in this portion do not exhibit the above-described action. As such a method, there is an anisotropic long throw sputtering method in which constituent element particles are supplied by setting the distance between the target and the sample to be equal to or larger than the diameter of the target. Further, a collimator sputtering method, an ionized metal plasma (IMP) sputtering method, or the like may be employed.

  Subsequently, as shown in FIG. 1C (g), a plurality of catalyst particles 12 are formed on the upper surface of the contact film 11 while being dispersed. The material of the catalyst particles 12 is not particularly limited, and examples thereof include cobalt (Co), iron (Fe), and nickel (Ni). Moreover, you may use the alloy containing these 2 types or 3 types. Examples of such an alloy include intermetallic compounds such as TiCo. Examples of the method for forming the catalyst particles 12 include a laser ablation method, a sputtering method, and a vapor deposition method. Further, it is preferable that the catalyst particles 12 are not formed on the side surface of the via hole 9 as much as possible by using a differential exhaust mechanism in the vacuum chamber.

  Next, the catalyst particles 12 positioned above the upper surface of the interlayer insulating film 7 are deactivated. In the present embodiment, as shown in FIG. 1C (h), the upper surface of the interlayer insulating film 7 is obtained by performing ion milling that irradiates ions from the direction inclined from the direction perpendicular to the surfaces of the substrate 1 and the interlayer insulating film 7. Then, the catalyst particles 12 located above are removed. The direction of irradiating ions is not particularly limited as long as the ions do not irradiate the catalyst particles 12 on the bottom surface of the via hole 9. For example, irradiation is performed from a direction inclined by 85 ° from the direction perpendicular to the surfaces of the substrate 1 and the interlayer insulating film 7. To do. Although the direction of irradiating ions may be fixed, it is preferable to irradiate from all directions in a plane parallel to the surface of the substrate 1 by rotating the stage on which the substrate 1 is placed. This is for uniform irradiation.

  As a result of this processing, as shown in FIG. 1C (i), the barrier film 10, the contact film 11 and the catalyst particles 12 on the upper surface of the interlayer insulating film 7 are removed, and the barrier film 10 and the contact film 11 are only in the via hole 9. And catalyst particles 12 remain.

  Thereafter, as shown in FIG. 1D (j), the carbon nanotubes 13 are grown from the catalyst particles 12 to above the upper end of the via hole 9. The method for growing the carbon nanotubes 13 is not particularly limited. For example, CVD methods, such as a thermal CVD method, a hot filament CVD method, and a plasma CVD method, are mentioned. When the thermal CVD method is employed, for example, a mixed gas of acetylene and argon is introduced as a reaction gas into a vacuum chamber that is a growth atmosphere. Acetylene is diluted with, for example, 10% by flow of argon and introduced into the vacuum chamber. The flow rates of the acetin-containing gas and the argon gas are, for example, 0.5 sccm and 1000 sccm, respectively. Further, for example, the pressure in the vacuum chamber is set to 1 kPa, and the substrate temperature is set to 400 ° C. to 450 ° C. Under such conditions, the carbon nanotubes 13 grow at a rate of about 1 μm / hour, for example. Moreover, when employ | adopting a hot filament CVD method, the temperature of the hot filament for dissociating gas is set to 900 to 1800 degreeC, for example.

  Subsequently, as shown in FIG. 1D (k), by performing ion milling that irradiates ions from a direction inclined from a direction perpendicular to the surface of the substrate 1 and the interlayer insulating film 7, the upper end of the via hole 9 of the carbon nanotube 13 is obtained. The part which protrudes upward is removed. The direction of irradiation with ions is not particularly limited. For example, the irradiation is performed from a direction inclined by 85 ° from the direction perpendicular to the surfaces of the substrate 1 and the interlayer insulating film 7. Although the direction of irradiating ions may be fixed, it is preferable to irradiate from all directions in a plane parallel to the surface of the substrate 1 by rotating the stage on which the substrate 1 is placed. This is for uniform irradiation.

  As a result of this processing, the upper end of the carbon nanotube 13 is aligned with the upper surface of the interlayer insulating film 7 as shown in FIG. In addition, after the ion milling, a treatment for removing oxygen adsorbed on the carbon nanotubes 13 may be performed. As this treatment, for example, heat treatment in an inert gas may be performed, or degassing treatment in a vacuum may be performed.

  Next, as shown in FIG. 1E (m), a conductive film 14 a in contact with the carbon nanotubes 13 is formed on the interlayer insulating film 7. In forming the conductive film 14a, for example, a tantalum (Ta) film and a copper (Cu) film are formed in this order by a sputtering method.

  Thereafter, as shown in FIG. 1E (n), the conductive film 14a is patterned by, for example, a photolithography method, and the wiring 14 electrically connected to the carbon nanotubes 13 is formed. The line width of the wiring 14 is, for example, several μm or less, for example, about 100 nm.

  Thereafter, if necessary, the formation of the same interlayer insulating film, the formation of carbon nanotubes, the formation of wiring, and the like are repeated to complete the semiconductor device. In this semiconductor device, the carbon nanotubes 13 function as vias.

  According to the first embodiment, since the catalyst particles 12 existing in the portions where the growth of the carbon nanotubes 13 is unnecessary are inactivated before the growth of the carbon nanotubes 13, the catalyst particles 12 are later removed from the catalyst particles 12. It is not necessary to remove the grown carbon nanotubes 13. Further, since removal of the portion of the carbon nanotube 13 protruding above the upper end of the via hole 9 is performed by ion milling instead of CMP, fixing by SOD or the like becomes unnecessary. Therefore, the problems associated with the combination of densification of carbon nanotubes 13 and fixation by SOD can be solved. Further, the cost can be reduced as compared with CMP.

  Instead of the catalyst particles 12, a catalyst film or the like may be formed as the catalyst portion.

  Further, as described above, the direction of ion irradiation is not particularly limited. For example, if the ion is determined not to collide with the catalyst particles 12 located at the bottom of the via hole 9 according to the diameter and depth of the via hole 9. Good.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 2 is a cross-sectional view showing the manufacturing direction of the semiconductor device according to the second embodiment in the order of steps.

  First, similarly to the first embodiment, processing up to the growth of the carbon nanotubes 13 is performed (see FIG. 1D (j)). Next, as shown in FIG. 2A, a conductive film 14 a in contact with the carbon nanotubes 13 is formed on the interlayer insulating film 7. At this time, the thickness of the conductive film 14a is made larger than the length of the portion protruding upward from the upper end of the via hole 9 of the carbon nanotube 13. The conductive film 14 a also enters the gap between the carbon nanotubes 13 in the via hole 9. In forming the conductive film 14a, for example, a tantalum (Ta) film and a copper (Cu) film are formed in this order by a sputtering method.

  Thereafter, as shown in FIG. 2B, the conductive film 14a is patterned by, for example, a photolithography method, and the wiring 14 electrically connected to the carbon nanotubes 13 is formed.

  Subsequently, if necessary, the formation of a similar interlayer insulating film, the formation of carbon nanotubes, the formation of wiring, and the like are repeated to complete the semiconductor device. Also in this semiconductor device, the carbon nanotubes 13 function as vias.

  According to the second embodiment, as in the first embodiment, before the growth of the carbon nanotubes 13, the catalyst particles 12 present in the portions where the growth of the carbon nanotubes 13 is unnecessary are deactivated. Therefore, it is not necessary to remove the carbon nanotubes 13 grown later from these catalyst particles 12. In addition, as shown in FIG. 1D (k), the tip of the carbon nanotube 13 can be cut, but if the carbon nanotube 13 is not cut, it is manufactured in a shorter time and at a lower cost than in the first embodiment. can do. Note that it is preferable to adjust the growth time of the carbon nanotubes 13 in advance in consideration of the thickness of the conductive film 14a. On the other hand, the upper end of the carbon nanotube 13 may be positioned below the upper end of the via hole 9. This is because the conductive film 14 a enters the via hole 9.

(Third embodiment)
Next, a third embodiment will be described. 3A to 3B are cross-sectional views illustrating the manufacturing direction of the semiconductor device according to the third embodiment in the order of steps.

  First, similarly to 1st Embodiment, the process until formation of the catalyst particle 12 is performed (refer FIG.1C (g)). Next, the catalyst particles 12 positioned above the upper surface of the interlayer insulating film 7 are deactivated. In the present embodiment, as shown in FIG. 3A (a), an inactivating film 21 that covers the catalyst particles 12 positioned above the upper surface of the interlayer insulating film 7 is formed. The inactivating film 21 may be a conductive film or an insulating film, and for example, a Ta film or a Ti film is formed. If the resist film is formed in the via hole 9 before the formation of the inactivation film 21 and the resist film is removed after the formation of the inactivation film 21, the catalyst particles 12 on the bottom surface of the via hole 9 are deactivated. Not covered. Even if the inactive film 21 is formed from a direction inclined by about 85 ° from the direction perpendicular to the surface of the substrate 1 without forming and removing the resist film, the catalyst particles 12 are covered with the inactive film 21. It can be avoided.

  Thereafter, as shown in FIG. 3A (b), the carbon nanotubes 13 are grown from the catalyst particles 12 to above the upper surface of the inactivation film 21.

  Subsequently, as shown in FIG. 3B (c), a conductive film 14 a in contact with the carbon nanotubes 13 is formed on the inactivating film 21. At this time, the thickness of the conductive film 14a is made larger than the length of the portion protruding above the upper surface of the inactivation film 21 of the carbon nanotube 13. The conductive film 14 a also enters the gap between the carbon nanotubes 13 in the via hole 9.

  Thereafter, as shown in FIG. 3B (d), the conductive film 14a, the inactivated film 21, the layer of the catalyst particles 12, the contact film 11, and the barrier film 10 are patterned by, for example, photolithography, and the carbon nanotubes 13 are electrically connected. Wiring 14 connected to each other is formed.

  Subsequently, if necessary, the formation of a similar interlayer insulating film, the formation of carbon nanotubes, the formation of wiring, and the like are repeated to complete the semiconductor device. Also in this semiconductor device, the carbon nanotubes 13 function as vias.

  According to the third embodiment, as in the first embodiment, before the growth of the carbon nanotubes 13, the catalyst particles 12 existing in the portions where the growth of the carbon nanotubes 13 is unnecessary are deactivated. Therefore, it is not necessary to remove the carbon nanotubes 13 grown later from these catalyst particles 12. In addition, as shown in FIG. 1D (k), the tip of the carbon nanotube 13 can be cut, but if the carbon nanotube 13 is not cut, it is manufactured in a shorter time and at a lower cost than in the first embodiment. can do. Note that it is preferable to adjust the growth time of the carbon nanotubes 13 in advance in consideration of the thickness of the conductive film 14a. On the other hand, the upper end of the carbon nanotube 13 may be positioned below the upper surface of the inactivation film 21. This is because the conductive film 14 a enters the opening of the inactivating film 21 that matches the via hole 9.

  FIG. 4 shows a state before and after ion milling of carbon nanotubes in the first embodiment. FIG. 4A shows a state in which a part of the carbon nanotubes before ion milling protrudes from the via hole, and FIG. 4B shows a state after ion milling. Similarly to the first embodiment, the sample of the scanning electron micrograph shown in FIG. 4 was subjected to ion milling for catalyst particles and the like located above the upper surface of the interlayer insulating film. For this reason, as shown in FIG. 4A, there is no carbon nanotube around the via hole. Further, as shown in FIG. 4 (b), the portion protruding from the via hole of the carbon nanotube is cut and appropriately removed by subsequent ion milling on the carbon nanotube.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
Forming a via hole in the insulating film;
Forming a catalyst portion in the via hole and on the insulating film;
Inactivating the catalyst portion on the insulating film;
Growing carbon nanotubes in the via hole starting from the catalyst portion in the via hole;
A method for manufacturing a semiconductor device, comprising:

(Appendix 2)
The method for manufacturing a semiconductor device according to appendix 1, wherein the step of inactivating the catalyst portion includes a step of removing the catalyst portion on the insulating film.

(Appendix 3)
The method for manufacturing a semiconductor device according to appendix 2, wherein the catalyst portion is removed by ion milling.

(Appendix 4)
4. The method of manufacturing a semiconductor device according to claim 3, wherein, in ion milling of the catalyst part, ions collide with the catalyst part on the insulating film from a direction inclined from a direction perpendicular to the surface of the insulating film. .

(Appendix 5)
The method of manufacturing a semiconductor device according to appendix 1, wherein the step of inactivating the catalyst portion includes a step of forming an inactivation film that covers the catalyst portion on the insulating film.

(Appendix 6)
The semiconductor device manufacturing method according to any one of appendices 1 to 5, wherein a plurality of catalyst particles are formed as the catalyst portion.

(Appendix 7)
Removing the portion of the carbon nanotube protruding from the upper end of the via hole by ion milling;
Forming a wiring connected to the carbon nanotube on the insulating film;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein:

(Appendix 8)
8. The method of manufacturing a semiconductor device according to appendix 7, wherein in the ion milling of the carbon nanotube, ions collide with the carbon nanotube from a direction inclined from a direction perpendicular to the surface of the insulating film.

(Appendix 9)
Any one of appendices 1 to 5, further comprising a step of covering a portion of the carbon nanotube protruding from the upper end of the via hole and forming a wiring connected to the carbon nanotube on the insulating film. The manufacturing method of the semiconductor device of description.

(Appendix 10)
Before the step of forming the via hole,
Forming a conductive film;
Forming the insulating film on the conductive film;
10. The method for manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein:

5: Wiring 6: Diffusion prevention film 7: Interlayer insulating film 8: Resist pattern 9: Via hole 12: Catalyst particles 13: Carbon nanotubes 14: Wiring 21: Deactivation film

Claims (5)

Forming a via hole in the insulating film;
Forming a catalyst portion in the via hole and on the insulating film;
Inactivating the catalyst portion on the insulating film;
Growing carbon nanotubes in the via hole starting from the catalyst portion in the via hole;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the step of inactivating the catalyst portion includes a step of removing the catalyst portion on the insulating film.   The method for manufacturing a semiconductor device according to claim 2, wherein the catalyst portion is removed by ion milling.   The method for manufacturing a semiconductor device according to claim 1, wherein the step of inactivating the catalyst part includes a step of forming an inactivation film that covers the catalyst part on the insulating film.   The semiconductor device manufacturing method according to claim 1, wherein a plurality of catalyst particles are formed as the catalyst portion.

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