JP2011077361A - Solar battery system and method for manufacturing the same - Google Patents

Abstract

The present invention provides a solar cell system that can be mounted on various devices by reducing the thickness of the solar cell system and improving the efficiency of the space for mounting a solar cell unit such as an output circuit.
A power supply circuit system S comprises a flexible printed circuit board (FPC) 200 having an output circuit for controlling the output of the solar battery power supply voltage V _E generated by the unit 100 to support the solar cell unit 100 The upper wiring pattern 220 laminated on the upper surface of the base 210 of the FPC 200 and on the first substrate surface on which the solar cell unit 100 is laminated functions as one electrode layer of the solar cell unit 100.
[Selection] Figure 1

Description

  The present invention relates to a technology of a solar cell system in which a solar cell unit is mounted, and more particularly to a technology of disposing a solar cell unit on a flexible printed board.

  In recent years, there has been an increasing awareness of the importance of power supply through the effective use of natural energy such as sunlight. For example, for so-called solid pn junction solar cell units that use silicon crystals, amorphous silicon thin films, and non-silicon compound semiconductor multilayer thin films, active research and development to improve energy conversion efficiency and reduce costs Has been done. In particular, a solar cell that can be produced using a printing technique such as an organic thin film solar cell or a dye-sensitized solar cell has been proposed due to the ease of the manufacturing process, cost reduction, and energy efficiency.

  Recently, not only a solar cell but also a solar cell system that improves efficiency and costs by devising a method for extracting a voltage generated by the solar cell unit is known. For example, a solar cell (hereinafter referred to as “solar cell unit”) and a switching regulator provided with the solar cell unit are integrally mounted on the same substrate, and the voltage generated by the solar cell unit is electronic equipment. A solar cell system has been proposed (for example, Patent Document 1).

JP-A-11-65687

  However, in the solar cell system described in Patent Document 1 described above, only the electronic circuit such as a switching regulator is connected to the back electrode of the solar cell unit. There is a limit to space efficiency. In particular, Patent Document 1 has no description that the wiring pattern of the electronic circuit is formed by the back electrode of the solar cell unit, and the structure of the solar cell unit is made by sharing the wiring pattern with the back electrode. There is no mention of simplification. Therefore, in this solar cell unit, the thinning of the solar cell unit and the efficiency of the space of the system itself cannot be improved based on this viewpoint.

  The present invention has been made in order to solve the above-mentioned problems, and the object thereof is various by reducing the thickness of the solar cell system and improving the efficiency of the space where the solar cell unit such as an output circuit is mounted. An object of the present invention is to provide a solar cell system that can be mounted on various devices and a method for manufacturing the solar cell system.

  (1) In order to solve the above-described problem, the solar cell system of the present invention is stacked on the first electrode layer and the first electrode layer, and photoelectric conversion is performed to generate a voltage from the received light. A solar cell unit composed of a photoelectric conversion layer, a second electrode layer stacked on the photoelectric conversion layer, and having a structure for causing the photoelectric conversion layer to receive light, and generated by the photoelectric conversion An output circuit for outputting a voltage and a flexible printed circuit board on which a wiring pattern for connecting the solar cell unit is formed, wherein the wiring pattern serves as the first electrode layer, the flexible printed circuit board It has the structure currently formed on the base material to comprise.

  With this configuration, the solar cell system according to the present invention can share the wiring pattern of the flexible printed circuit board for connection with the output circuit with the electrode of the solar cell unit. The unit can be thinned.

  Accordingly, the solar cell system of the present invention can reduce the thickness of the space and the efficiency of the space where the solar cell unit such as the output circuit is mounted. A power supply system based on a solar cell can be mounted on various devices such as limited devices.

  (2) Moreover, the solar cell system of this invention has the structure by which the circuit pattern in which the output circuit comprised by an electronic circuit component is formed is contained in the said wiring pattern.

  With this configuration, the solar cell system of the present invention is a solar cell unit on a substrate on which a solar cell unit is formed by electronic circuit components such as a capacitor element, a coil element, a resistance element, a switch element, and an integrated circuit chip. Since an output circuit for outputting the generated voltage can also be formed, for example, a circuit for controlling or adjusting a voltage generated by a solar cell unit such as a regulator circuit or a booster circuit can be formed. The solar cell system can supply a stable voltage to other circuits.

  Therefore, the solar cell system of the present invention is reduced in thickness as a solar cell system including a solar cell unit including a circuit necessary for outputting a voltage generated based on the solar cell unit, and the space of the entire circuit. Therefore, power supply circuits based on solar cells can be mounted on various devices such as small electronic devices or devices in which the space of the power supply circuit is limited due to design restrictions.

  (3) Moreover, the solar cell system of this invention has the structure by which the said circuit pattern is used as at least one part for exhibiting the characteristic function of the said electronic circuit component.

  With this configuration, the solar cell system of the present invention has a function as a capacitance, a function as an inductance, a voltage or current amplification function, such as an electrode of a capacitor element, a coil winding or a film constituting a diode or a transistor. Since at least a part of the element for exhibiting the blocking function can be configured by the circuit pattern on the substrate on which the solar cell unit is formed, the efficiency of the space can be achieved also in the output circuit.

  (4) In the solar cell system of the present invention, the first circuit pattern is formed as the circuit pattern on the first substrate surface on the side where the solar cell unit of the base material is disposed. A second circuit pattern is formed as the circuit pattern on the second substrate surface opposite to the first substrate surface, and the electronic circuit component is configured by the first circuit pattern and the second circuit pattern. Have.

  With this configuration, the solar cell system of the present invention can form an electronic circuit component such as a capacitor element or a coil element by a laminated structure of circuit patterns formed on a flexible printed circuit board. It is possible to improve the space efficiency of the entire circuit by eliminating the wiring for forming the components, and to provide a circuit element that is thicker than when electronic circuit components are mounted only on one substrate surface by a chip or the like. The entire circuit can be made thinner without using it.

In addition, since it is usually necessary to secure a predetermined area from the viewpoint of capturing a large amount of light into the solar cell unit, the solar cell system of the present invention has an area of a circuit pattern for forming an electronic circuit component accordingly. For example, it is possible to form a capacitor having a large value such as a capacitance in a capacitor element or an inductance value in a coil, so that circuit characteristics can be improved.
(5) Moreover, the solar cell system of this invention has the structure by which the electronic circuit component which comprises the said output circuit is mounted in the said circuit pattern.

  With this configuration, the solar cell system of the present invention can mount electronic circuit components such as a capacitor element, a coil element, a switch element, or a diode element on the substrate on which the solar cell unit is formed. This circuit can be formed as an output circuit.

  (6) Moreover, the solar cell system of this invention has the structure by which the said circuit pattern is formed in the 1st board | substrate surface which is the side by which the said solar cell unit of the said base material is arrange | positioned.

  With this configuration, since the solar cell system of the present invention can form a circuit pattern on the same surface as the surface on which the solar cell unit is formed, the capacitor element in consideration of the location of the solar cell system, The output circuit can be formed by electronic circuit components such as a coil element or a switch element.

  (7) Moreover, the solar cell system of this invention is equipped with the same laminated structure as the said solar cell unit on the said circuit pattern, the said photoelectric conversion layer formed on the said circuit pattern and the said circuit pattern, and the said 2nd A semiconductor element as the electronic circuit component is formed by the electrode layer.

  With this configuration, in the solar cell system of the present invention, the solar cell unit and the electronic circuit component are formed with the same laminated structure on the same surface of the flexible printed circuit board, so that the efficiency of the space as a whole circuit is improved. In addition, the manufacturing process of the solar cell system can be simplified.

  (8) Further, in the solar cell system of the present invention, the circuit pattern is formed on the second substrate surface opposite to the first substrate surface on the side where the solar cell unit of the base material is disposed. It has a configuration.

  With this configuration, the solar cell system according to the present invention includes electronic circuit components such as a capacitor element and a coil element on the second substrate surface opposite to the first substrate surface on which the solar cell unit of the flexible printed circuit board is disposed. Since the output circuit can be formed, the output circuit can be formed in consideration of the arrangement position of the solar cell system.

  (9) Moreover, the solar cell system of this invention has the structure in which the said flexible printed circuit board is further provided with the electrode terminal for connecting with the electronic circuit driven with the said produced | generated voltage.

  With this configuration, the solar cell system of the present invention can easily and surely connect to other circuits by using electrode terminals that are generally used when connecting a flexible printed circuit board to another substrate or the like. Can do.

  (10) In the solar cell system of the present invention, the solar cell unit has a through-hole for connecting the second electrode layer and the output circuit while being insulated from the photoelectric conversion layer, and the wiring. The pattern has a land having a land joined to the through hole.

  With this configuration, the solar cell system of the present invention can connect the solar cell unit and the wiring pattern through the through hole and the land, so that the connection with the output circuit configured by being stacked on the solar cell unit is easy. Thus, the space of the entire circuit can be effectively utilized.

  (11) Moreover, the solar cell system of this invention has a shape for the land to function as an alignment mark used when positioning the position where the solar cell unit is disposed on the wiring pattern. The structure is

  With this configuration, the solar cell system of the present invention can effectively use the wasted space of the alignment mark provided on the wiring pattern, so that the maximum light receiving area of the solar cell unit can be reduced. A limited area can be used for the light receiving surface.

  (12) Further, the solar cell system of the present invention has a configuration in which the through hole and the land are formed in the vicinity of the center of the solar cell unit when the solar cell unit is mounted on the flexible printed board. is doing.

  With this configuration, the solar cell system of the present invention is equivalent to the resistance value from each position on the plane of the second electrode layer even when the resistivity accompanying the material of the second electrode layer such as ITO is high. Since the voltage can be lowered, a voltage efficiently generated from the solar cell unit can be output.

  (13) Moreover, the solar cell system of this invention has the structure by which the alignment mark which positions the position which arrange | positions the said solar cell unit in the said wiring pattern is formed.

  With this configuration, the solar cell system of the present invention can easily and accurately stack the solar cell unit on the flexible printed circuit board in the manufacturing process.

  (14) In order to solve the above-described problem, a method for manufacturing a solar cell system according to the present invention includes a solar cell unit and a flexible printed circuit board on which an output circuit that performs output control of a voltage generated by the solar cell unit is formed. A manufacturing method for manufacturing a solar cell system comprising: a preparation for preparing the flexible printed circuit board having a wiring pattern for connecting the solar cell unit and the output circuit, wherein the output circuit is formed A photoelectric conversion layer forming step of forming a photoelectric conversion layer in which a photoelectric conversion for generating a voltage from received light is performed on the wiring pattern; and the photoelectric conversion is laminated on the photoelectric conversion layer A surface electrode layer forming step of forming a surface electrode layer having a structure for causing the layer to receive light, and the wiring pattern Emissions is, has a configuration to be used as the back electrode layer of the solar cell unit.

  With this configuration, the manufacturing method of the present invention is capable of reducing the thickness of the circuit including the circuit necessary for outputting the voltage generated based on the solar cell unit and improving the efficiency of the space of the entire circuit. In the battery system, since the solar cell unit is formed on the flexible printed circuit board after the wiring pattern is formed on the flexible printed circuit board, without receiving pressure applied when the wiring pattern is bonded onto the flexible printed circuit board, A solar cell unit can be formed. Therefore, the manufacturing method of this invention can manufacture a solar cell system exactly and reliably, without damaging a solar cell unit.

  Since the present invention can improve the efficiency of the space where the solar cell unit such as a thin film and an output circuit is mounted, such as a small electronic device or a device in which the space of the power circuit is limited due to design restrictions, Various devices can be equipped with a power system based on solar cells.

  Moreover, this invention can manufacture the said solar cell system exactly and reliably, without damaging a solar cell unit in such a solar cell system.

1 is a structural diagram showing a structure in a first embodiment of a power supply circuit system according to the present invention. It is a figure for demonstrating the structure of the solar cell unit in 1st Embodiment. It is a figure for demonstrating the manufacturing method in the power supply circuit system of 1st Embodiment. It is the other example (I) of the structural diagram which shows the structure of the power supply circuit system in 1st Embodiment. It is the other example (II) of the structure figure which shows the structure of the power supply circuit system in 1st Embodiment. It is the other example (III) of the structure figure which shows the structure of the power supply circuit system in 1st Embodiment. It is the other example (IV) of the structure figure which shows the structure of the power supply circuit system in 1st Embodiment. It is a figure for demonstrating the other example of the manufacturing method in the power supply circuit system of 1st Embodiment. It is a structural diagram which shows the structure in 2nd Embodiment of the power supply circuit system which concerns on this invention. It is an equivalent circuit of the power supply circuit system in 2nd Embodiment. It is a structural diagram which shows the structure in 3rd Embodiment of the power supply circuit system which concerns on this invention. It is an equivalent circuit of the power supply circuit system in 3rd Embodiment. It is a modification of the equivalent circuit of the power supply circuit system in 3rd Embodiment. It is a structural diagram which shows the structure in 4th Embodiment of the power supply circuit system which concerns on this invention. It is a modification of the structure figure of the power supply circuit system in 4th Embodiment. It is a structural diagram which shows the structure in 5th Embodiment of the power supply circuit system which concerns on this invention.

  Hereinafter, each embodiment of the present application will be described with reference to the drawings. In each embodiment described below, a power circuit system (hereinafter simply referred to as “power circuit system”) having a solar cell unit mounted on a flexible printed board is applied to the solar cell system of the present invention. Embodiment.

[First embodiment]
First, a first embodiment of a power supply circuit system S according to the present invention will be described with reference to FIGS.

  First, the structure of the power supply circuit system S of the present embodiment will be described with reference to FIG. FIG. 1 is a structural diagram showing the structure of the power supply circuit system S in the present embodiment.

Power circuit system S of this embodiment, as shown in FIG. 1, a voltage (hereinafter, also referred to as "power supply voltage".) Based on the received light with the solar cell unit 100 to produce the V _E, the solar cell unit a flexible printed circuit board having an output circuit 10 for outputting control or adjustment of the solar cell module power supply voltage V _E generated by 100 to support the 100 (hereinafter, simply referred to as "FPC".) 200, is composed of The

The solar cell unit 100 has, for example, a Schottky type or heterojunction type (including bilayer type and bulk hetero type) organic thin film solar cell or dye-sensitized solar cell structure. Specifically, the solar cell unit 100 includes a photoelectric conversion layer 110 that performs photoelectric conversion to generate a power supply voltage V _E on the basis of the received light on one surface (light receiving surface), on the photoelectric conversion layer 110 An electrode layer (hereinafter referred to as “transparent electrode layer”) 120 formed of a transparent material for receiving light, and a laminate formed from one side of the FPC 200 (hereinafter referred to as “first substrate”). Surface "). The solar cell unit 100 uses the upper wiring pattern 220 of the FPC 200 described later as a back electrode, and outputs the generated voltage to the output circuit 10 formed on the FPC 200. .

  Further, the solar cell unit 100 is for electrically connecting to the output circuit 10 (that is, upper and lower wiring patterns 220 and 230 described later) while insulating the transparent electrode layer 120 and the photoelectric conversion layer 110. A through hole H is formed. In particular, the through hole H of the present embodiment is joined to a land M provided on an upper wiring pattern 220 described later. Further, the through hole H is formed in the vicinity of the center on the plane of the solar cell unit 100 and is transparent even when the resistivity accompanying the material of the transparent electrode layer 120 such as ITO is high. Since the resistance value from each position on the plane of the electrode layer 120 can be reduced equivalently, the voltage generated efficiently from the solar cell unit 100 can be output.

  In this embodiment, for example, when the solar cell unit 100 has the structure of a Schottky type or heterojunction type organic thin film solar cell, the photoelectric conversion efficiency is improved and the transparent electrode layer 120 and the photoelectric conversion are converted. The hole extraction layer 113 is provided to improve smoothness and adhesion at the interface with the layer 110. Moreover, the detail of the laminated structure of the solar cell unit 100 of this embodiment is mentioned later.

  The FPC 200 is a double-sided two-layer metal flexible printed circuit board on which metal wiring patterns are formed on both sides. As shown in FIG. 1, the FPC 200 includes a base 210 formed of polyimide or PET, and an upper surface of the base 210. A wiring pattern (hereinafter referred to as “upper wiring pattern”) 220 laminated on the first substrate surface on which the solar cell unit 100 is laminated, and a lower surface of the base 210 opposite to the first substrate surface (hereinafter referred to as “upper wiring pattern”). And a wiring pattern (hereinafter referred to as a “lower wiring pattern”) 230 laminated on the “second substrate surface”).

  The upper wiring pattern 220 has the solar cell unit 100 laminated on the upper surface, and functions as a back electrode of the solar cell unit 100. In addition to the portion functioning as the back electrode of the solar cell unit 100, the upper wiring pattern 220 is connected to the land M and the lower wiring pattern 230 that are joined to the through holes H formed in the solar cell unit 100. A connection pattern is formed. Specifically, the land M has a function as an alignment mark used for positioning when the solar cell unit 100 is stacked on the FPC 200. The land M is insulated and independent from the other wiring patterns of the upper wiring pattern 220 in order to connect the transparent electrode layer 120 to the lower wiring pattern 230 forming the output circuit 10. It is connected to the lower wiring pattern 230 through the provided through hole.

  The land M does not need to be circular with the through hole H as an alignment mark, and may have a shape capable of positioning the solar cell unit 100 and the FPC 200 vertically and horizontally such as a cross. Further, the upper wiring pattern 220 of the present embodiment may have other alignment marks in addition to the land M, and does not function as an alignment mark when other alignment marks are formed. The land M may be provided.

The upper wiring pattern 220 is driven by the output circuit 10 and a voltage (hereinafter referred to as “output voltage”) V _O generated based on the output circuit 10 and the solar cell unit 100 and controlled or adjusted by the output circuit 10. An electrode terminal of a type that fits into a socket for connecting to another circuit (hereinafter referred to as “external electronic circuit”), that is, a connector (details of the connector will be described in other embodiments described later). ) Is provided.

  The material for forming the upper wiring pattern 220 is not particularly limited as long as it has conductivity. However, as described above, an appropriate material is selected depending on the type of the solar cell. Or aluminum. The film thickness of the upper wiring pattern 220 is preferably 9 μm, for example.

The lower wiring pattern 230 is connected to the transparent electrode layer 120 through the through hole H and the land M. The lower wiring pattern 230 includes, for example, an electronic circuit element E such as a resistance element, a switch element, a capacitor element, or a coil element, or a regulator on a wiring pattern formed in accordance with the position where the through hole H is provided. An electronic circuit component of an integrated circuit chip (hereinafter simply referred to as “integrated circuit chip”) I for a power supply circuit system such as Then, the lower wiring pattern 230, together with these electronic circuit elements E and the integrated circuit chip I, so as to constitute an output circuit 10 for adjusting the power supply voltage V _E generated by the solar cell unit 100 Yes. The electronic circuit element E and the integrated circuit chip I are mounted on the lower wiring pattern 230 and then covered with a protective layer such as a resin, and the entire flexible FPC 200 is curved. Even implemented so as not to break.

  The material for forming the lower electrode pattern is not particularly limited as long as it has conductivity. For example, it is formed of copper (Cu). The film thickness of the lower electrode pattern is preferably 9 μm, for example.

  Note that the FPC 200 of this embodiment has a protective film (not shown) for preventing the wiring from being oxidized on the lower wiring pattern 230. However, no protective film is formed on the portion where the electronic circuit component is mounted. The base 210 of the present embodiment constitutes the base material of the present invention, the upper wiring pattern 220 constitutes the wiring pattern of the present invention, and the lower wiring pattern 230 of the present embodiment constitutes the wiring pattern of the present invention. And a circuit pattern.

  Next, the structure of the solar cell unit 100 in the present embodiment will be described with reference to FIG. In addition, FIG. 2 is a figure for demonstrating the structure of the solar cell unit 100 in this embodiment. Further, FIG. 2 shows the direction in which the photocurrent flows and the positive and negative polarities.

  For example, as shown in FIG. 2, the solar cell unit 100 of the present embodiment has P-type and N-type organic semiconductor layers 111 and 112, respectively, and performs charge separation using a PN junction formed at the interface between them. To a bulk that has a mixed layer 115 in which bi-layer type, N-type and P-type semiconductor materials are uniformly dispersed, and that generates charge separation using a PN junction formed in the mixed layer 115 Structure of a terror-type or Schottky-type organic thin-film solar cell that generates charge separation using a Schottky barrier formed at the interface between each electrode and the photoelectric conversion layer 110 (P-type semiconductor layer), or It has a structure of a dye-sensitized solar cell that performs charge separation based on an organic dye.

  The solar cell units 100 having the structure of a bilayer type, bulk hetero type, or Schottky type organic thin film solar cell are respectively referred to as “bilayer type organic thin film solar cell unit” and “bulk hetero type organic thin film solar cell”. The solar cell unit having the structure of a dye-sensitized solar cell is referred to as a “dye-sensitized solar cell unit”. Hereinafter, the structure of the solar cell unit 100 will be described for each type.

(1) Bilayer type organic thin film solar cell unit As shown in FIG. 2A, the bilayer type organic thin film solar cell unit 100 includes an N type organic semiconductor layer 111 and an upper wiring pattern 220 as a back electrode. A photoelectric conversion layer 110 made of a P-type organic semiconductor layer 112, a hole extraction layer 113, and a transparent electrode layer 120 are sequentially stacked.

(Photoelectric conversion layer (P-type organic semiconductor layer + N-type organic semiconductor layer))
The photoelectric conversion layer 110 contributes to charge separation in the organic thin-film solar cell unit 100 and has a function of transporting electrons and holes generated by light reception toward electrodes in opposite directions. The photoelectric conversion layer 110 includes an N-type organic semiconductor layer 111 (electron transport layer) that functions as an electron acceptor stacked on the upper wiring pattern 220, and an electron donation stacked on the N-type organic semiconductor layer 111. The P-type organic semiconductor layer 112 (hole transport layer) functioning as a body is provided separately, and charge separation is generated by using a PN junction formed at the interface between them to obtain a photocurrent. Yes.

  The material for forming the N-type organic semiconductor layer 111 is not particularly limited as long as it has a function as an electron acceptor. Specifically, the material for forming the N-type organic semiconductor layer 111 of this embodiment is CN-poly (phenylene-vinylene), MEH-CN-PPV, -CN group or -CF3 group-containing polymer, or -CF3 thereof. Substituted polymers, poly (fluorene) derivatives, fullerene derivatives such as C60, carbon nanotubes, perylene derivatives, polycyclic quinones, quinacridones, and the like have been used.

  The material for forming the P-type organic semiconductor layer 112 is not particularly limited as long as it has a function as an electron donor. Specifically, the material for forming the P-type organic semiconductor layer 112 of this embodiment includes polyphenylene and derivatives thereof, polyphenylene vinylene and derivatives thereof, polysilane and derivatives thereof, polyalkylthiophene and derivatives thereof, porphyrin derivatives, and phthalocyanine derivatives. Organic metal polymers have been used.

  The film thicknesses of the N-type organic semiconductor layer 111 and the P-type organic semiconductor layer 112 are not limited. For example, each film thickness may be in the range of 0.1 nm to 1500 nm, particularly in the range of 1 nm to 300 nm. preferable. When this film thickness is larger than the above range, the volume resistance in the N-type organic semiconductor layer 111 and the P-type organic semiconductor layer 112 may be increased, and when the film thickness is smaller than the above range, the upper wiring This is because a short circuit may occur between the pattern 220 and the transparent electrode layer 120.

  A method for forming the N-type organic semiconductor layer 111 and the P-type organic semiconductor layer 112 is not particularly limited as long as it can be uniformly formed to have a predetermined film thickness. Specifically, as a method of forming the N-type organic semiconductor layer 111 and the P-type organic semiconductor layer 112, a method of directly patterning the photoelectric conversion layer 110 on the upper wiring pattern 220 by printing, screen printing, or an inkjet method, spin coating For example, a method of forming a photoelectric conversion layer 110 on the upper wiring pattern 220 by providing a photosensitive resist film after coating, exposing, and developing is used.

(Hole extraction layer)
The hole extraction layer 113 is laminated on the P-type organic semiconductor layer 112, and as described above, the photoelectric conversion efficiency is improved and the smoothness and adhesion at the interface between the transparent electrode layer 120 and the photoelectric conversion layer 110 are improved. Is provided for.

  Specifically, the hole extraction layer 113 contains a conductive polymer material and an amphiphilic material. As the conductive polymer material in the hole extraction layer 113, those generally used for the hole extraction layer 113 are used. Specifically, doped polyaniline, polyphenylene vinylene, polythiophene are used. , Conductive organic compounds such as polypyrrole, polyparaphenylene, polyacetylene and triphenyldiamine, or electron donating compounds such as tetrathiofulvalene and tetramethylphenylenediamine, and electrons such as tetracyanoquinodimethane and tetracyanoethylene Organic materials that form charge transfer complexes composed of accepting compounds have been used. Further, as the amphiphilic material of the hole extraction layer 113, a general surfactant is used, and for example, a nonionic surfactant or a fluorine-based surfactant is used. It has become.

  The thickness of the hole extraction layer 113 varies depending on the type of the conductive polymer material, the amphiphilic material, and the like, and is appropriately adjusted in consideration of the above-described characteristics. Specifically, the thickness of the hole extraction layer 113 is preferably in the range of 0.01 nm to 3000 nm, more preferably in the range of 0.1 nm to 1500 nm, and most preferably in the range of 1 nm to 600 nm. It is. If this film thickness is too thick, the resistance value increases in proportion to the hole transfer path length, so holes may not be sufficiently extracted to the first electrode layer, and if the film thickness is too thin, The adhesion between the extraction layer 113 and the photoelectric conversion layer 110 is reduced, and the thickness of the photoelectric conversion layer 110 is relatively thin, so that the upper wiring pattern 220 and the transparent electrode layer 120 are in direct contact with each other due to the protrusion of the transparent electrode and short-circuited. Because there is a possibility of doing.

  The surface roughness Ra of the hole extraction layer 113 varies depending on the type of conductive polymer material, amphiphilic material, and the like, and is appropriately adjusted in consideration of the above-described characteristics and the like. Specifically, the surface roughness Ra of the hole extraction layer 113 is preferably 50 nm or less, more preferably 30 nm or less, and most preferably 10 nm or less. If the surface roughness is too large, the adhesion between the hole extraction layer 113 and the transparent electrode layer 120 or the photoelectric conversion layer 110 is lowered, or the thickness of the photoelectric conversion layer 110 is relatively thin, so the hole extraction layer 113 is relatively thin. This is because there is a possibility that the transparent electrode layer 120 and the upper wiring pattern 220 are in direct contact with each other and short-circuited due to the protrusions on the surface.

  The surface resistance value of the hole extraction layer 113 is preferably 300Ω / □ or less, more preferably 150Ω / □ or less, and most preferably 50Ω / □ or less. If the surface resistance value is too large, the holes generated in the photoelectric conversion layer 110 cannot be sufficiently transferred to the transparent electrode layer 120, or the influence of the barrier due to the smoothness and adhesion of the hole extraction layer 113 This is because the function as an organic thin film solar cell may be impaired due to the excessively large thickness.

  A method for forming the hole extraction layer 113 is not particularly limited as long as it can be uniformly formed to have a predetermined film thickness. Specifically, as a method of forming the hole extraction layer 113, a method of directly patterning the hole extraction layer 113 on the upper wiring pattern 220 by printing, screen printing, or an inkjet method, or photosensitivity after application by spin coating or the like. A method of forming a hole extraction layer 113 on the upper wiring pattern 220 by providing a conductive resist film, and exposing and developing is used.

(Transparent electrode layer)
The transparent electrode layer 120 is laminated on the hole extraction layer 113 and is formed of a transparent conductive material such as ITO (Indium Tin Oxide) or titanium oxide so that the photoelectric conversion layer 110 can receive light.

  The sheet resistance value of the transparent electrode layer 120 is preferably 20Ω / □ or less, more preferably 10Ω / □ or less, and particularly preferably 5Ω / □ or less. This is because if the sheet resistance value is larger than the above range, the generated charge may not be sufficiently transmitted to the output circuit 10. Further, the film thickness of such a transparent electrode is preferably in the range of 0.1 to 500 nm, and more preferably in the range of 1 nm to 300 nm. When the film thickness is smaller than the above range, the sheet resistance of the transparent electrode layer 120 becomes too large, and the generated charge may not be sufficiently transmitted to the external electronic circuit. This is because the total light transmittance is lowered and the photoelectric conversion efficiency may be lowered.

  As a method of forming the transparent electrode layer 120, a general method is used. Specifically, the transparent electrode layer 120 is formed by a PVD method such as a vacuum deposition method, a sputtering method, or an ion plating method, a dry coating method such as a CVD method, and a coating liquid containing ITO fine particles. A wet coating method in which a coating is applied is used. The patterning method for forming the transparent electrode layer 120 in a pattern is not particularly limited as long as it can accurately form the transparent electrode layer 120 in a desired pattern. Lithography is used.

(2) Bulk hetero type organic thin film solar cell unit As shown in FIG. 2B, the bulk hetero type organic thin film solar cell unit 100 includes N-type and P-type semiconductors on an upper wiring pattern 220 as a back electrode. A photoelectric conversion layer 110 composed of a mixed layer 115 in which materials are uniformly dispersed, a hole extraction layer 113, and a transparent electrode layer 120 are sequentially stacked. Except for the photoelectric conversion layer 110, the structure of the hole extraction layer 113 and the transparent electrode layer 120 is the same as that of the bilayer type organic thin film solar cell unit 100, and thus the description thereof is omitted.

(Photoelectric conversion layer (mixed layer))
The photoelectric conversion layer 110 contributes to charge separation in the organic thin-film solar cell unit 100 and has a function of transporting electrons and holes generated by light reception toward electrodes in opposite directions. The photoelectric conversion layer 110 forms a mixed layer 115 (electron hole transport layer) having the functions of both an electron acceptor and an electron donor stacked on the upper wiring pattern 220, The formed pn junction is used to cause charge separation to obtain a photocurrent.

  The material for forming the mixed layer 115 is not particularly limited as long as it is generally used in the structure of a bulk heterojunction organic thin film solar cell. Specifically, the material for forming the mixed layer 115 is a material in which both the electron-donating material and the electron-accepting material are uniformly dispersed, and both the electron-donating material and the electron-accepting material are used. The mixing ratio of the materials is appropriately adjusted to an optimum mixing ratio depending on the materials used.

  The electron-accepting material is not particularly limited as long as it has such a function. Specifically, CN-poly (phenylene-vinylene), MEH-CN-PPV, -CN group or -CF3 group-containing polymer, their -CF3 substituted polymer, poly (fluorene) derivative, C60 derivative, carbon nanotube, perylene Derivatives, polycyclic quinones, quinacridones and the like have been used. The electron donating material is not particularly limited as long as it has such a function. Specifically, polyphenylene and derivatives thereof, polyphenylene vinylene and derivatives thereof, polysilane and derivatives thereof, polyalkylthiophene and derivatives thereof, porphyrin derivatives, phthalocyanine derivatives, organometallic polymers, and the like are used.

  The film thickness of the mixed layer 115 is not particularly limited as long as it is a film thickness generally employed in a bulk heterojunction type. Specifically, the film thickness is within a range of 0.2 nm to 3000 nm, among which 1 nm to 600 nm. It is preferable to be within the range. When the film thickness is thicker than the above range, the volume resistance in the electron hole transport layer may be increased. On the other hand, when the film thickness is thinner than the above range, the transparent electrode layer 120 and the upper wiring pattern 220 are used. This is because there is a possibility of short circuit.

  A method for forming the mixed layer 115 is not particularly limited as long as it can be uniformly formed to have a predetermined film thickness. Specifically, as a method of forming the mixed layer 115, a method of directly patterning the photoelectric conversion layer 110 on the upper wiring pattern 220 by printing, screen printing, or an inkjet method, a photosensitive resist film is provided after coating by spin coating or the like. A method of forming the photoelectric conversion layer 110 on the upper wiring pattern 220 by exposure and development is used.

(2) Schottky type organic solar cell unit As shown in FIG. 2 (c), the Schottky type organic thin film solar cell unit 100 has a P type (or N type) on the upper wiring pattern 220 as a back electrode. A photoelectric conversion layer 110 made of a P-type organic semiconductor layer 112 (or an N-type organic semiconductor layer) in which a semiconductor material is uniformly dispersed, a hole extraction layer 113, and a transparent electrode layer 120 are sequentially stacked. Except for the photoelectric conversion layer 110, the structure of the hole extraction layer 113 and the transparent electrode layer 120 is the same as that of the bilayer type organic thin film solar cell unit 100, and thus the description thereof is omitted.

(Photoelectric conversion layer (P-type organic semiconductor layer or N-type organic semiconductor layer))
The photoelectric conversion layer 110 contributes to charge separation in the organic thin-film solar cell unit 100 and has a function of transporting holes or electrons generated by light reception toward a predetermined electrode. The photoelectric conversion layer 110 is a layer having an electron accepting or electron donating function laminated on the upper wiring pattern 220, that is, a P-type organic semiconductor layer as a hole transporting layer or an electron transporting layer. By using an N-type organic semiconductor layer, a photocurrent is obtained using a Schottky barrier formed at the interface between the photoelectric conversion layer 110 and the electrode.

  The photoelectric conversion layer 110 in the Schottky type organic thin film solar cell unit 100 is formed using an electron accepting or electron donating material. For example, since a Schottky barrier is formed at the interface between the transparent electrode and the upper wiring pattern 220 having the lower work function (the electrode having the higher work function), a photocurrent may be generated at the interface. It can be done.

  A material for forming the photoelectric conversion layer 110 is not particularly limited as long as the material has an electron accepting property or an electron accepting property. Specifically, conductive polymers such as organic single crystals such as pentacene, poly-3-methylthiophene, polyacetylene, polyphenylene and derivatives thereof, polyphenylene vinylene and derivatives thereof, polysilane and derivatives thereof, polyalkylthiophene and derivatives thereof, and the like Such derivatives, porphyrin derivatives, phthalocyanine derivatives, merocyanine derivatives, synthetic pigments such as chlorophyll, organometallic polymers, and the like have been used.

  The film thickness of the photoelectric conversion layer 110 is preferably in the range of 0.1 nm to 1500 nm, and more preferably in the range of 1 nm to 300 nm. When the film thickness is larger than the above range, the volume resistance of the photoelectric conversion layer 110 may be increased. On the other hand, when the film thickness is smaller than the above range, the transparent electrode layer 120 and the upper wiring pattern 220 are short-circuited. This is because there is a possibility of occurrence.

  A method for forming the photoelectric conversion layer 110 is not particularly limited as long as it can be uniformly formed to have a predetermined film thickness. Specifically, as a method of forming the photoelectric conversion layer 110, a method of directly patterning the photoelectric conversion layer 110 on the upper wiring pattern 220 by printing, screen printing, or an ink jet method, a photosensitive resist film is applied after spin coating or the like. A method of forming the photoelectric conversion layer 110 on the upper wiring pattern 220 by providing, exposing and developing is used.

(4) Dye-sensitized solar cell unit As shown in FIG. 2D, the dye-sensitized solar cell unit 100 is an oxide containing a dye sensitizer on the upper wiring pattern 220 as a back electrode. A photoelectric conversion layer 110 made of a semiconductor layer 117 and a transparent electrode layer 120 are sequentially stacked. The transparent electrode layer 120 is the same as the bilayer type organic thin film solar cell unit 100 and other solar cell units 100 described above, and therefore the description thereof is omitted.

(Photoelectric conversion layer (oxide semiconductor layer))
The photoelectric conversion layer 110 includes metal oxide semiconductor particles and a dye sensitizer that can absorb light and generate electromotive force and adsorbed on the surface of the metal oxide semiconductor particles. The In the photoelectric conversion layer 110, the dye sensitizer adsorbed on the surface of the metal oxide semiconductor fine particles is excited by receiving light, and the excited electrons are conducted to the upper wiring pattern 220 and pass through the through holes H. While being conducted to the transparent electrode layer 120, the photocurrent is obtained by returning the electrons to the ground level of the dye sensitizer through the redox pair.

The metal oxide semiconductor fine particle is not particularly limited as long as it is made of a metal oxide having semiconductor characteristics. For example, TiO ₂ , ZnO, SnO ₂ , ITO, ZrO ₂ , MgO, Al ₂ O _{3, CeO 2, Bi 2 O} 3, Mn 3 O 4, Y 2 O 3, WO 3, Ta 2 O 5, Nb 2 O 5, La 2 O 3 and the like are increasingly used.

  The particle size of the metal oxide semiconductor fine particles is not particularly limited as long as the surface area of the oxide semiconductor layer 117 can be within a desired range, but usually within the range of 1 nm to 10 μm, In particular, it is preferably within the range of 10 nm to 1000 nm.

  The dye sensitizer is not particularly limited as long as it can absorb light and generate an electromotive force. As such a dye sensitizer, an organic dye or a metal complex dye is used.

  The thickness of the photoelectric conversion layer 110 can be appropriately determined and is not particularly limited, but it is usually preferably in the range of 1 μm to 100 μm, and particularly preferably in the range of 5 μm to 30 μm. This is because when the thickness of the photoelectric conversion layer 110 is larger than the above range, the oxide semiconductor layer 117 itself is likely to cohesively break down, which may easily cause film resistance. In addition, when the thickness is smaller than the above range, it is difficult to form the oxide semiconductor layer 117 having a uniform thickness. For example, when a dye-sensitized solar cell is manufactured using the oxide semiconductor electrode laminate. This is because the oxide semiconductor layer 117 containing a dye sensitizer cannot sufficiently absorb sunlight and the like, which may cause poor performance.

  A method for forming the photoelectric conversion layer 110 is not particularly limited as long as it can be uniformly formed to have a predetermined film thickness. Specifically, as a method of forming the photoelectric conversion layer 110, a method of applying and baking a coating liquid for forming the photoelectric conversion layer 110 on the upper wiring pattern 220 by die coating or screen printing (rotary type). Is being used.

  Next, the manufacturing method of the power supply circuit system S of this embodiment is demonstrated using FIG. FIG. 3 is a diagram for explaining the manufacturing method of the present embodiment.

  In the manufacturing method of the present embodiment, the solar cell unit 100 is formed on the FPC 200 that already has the predetermined upper wiring pattern 220 and the lower wiring pattern 230, and after the solar cell unit 100 is formed, the FPC 200 is electronically connected. This is a method of forming the circuit element E and the integrated circuit chip I. Moreover, in this manufacturing method, it demonstrates using the manufacturing method in the case of forming the bilayer type organic thin film solar cell unit 100. FIG.

  First, as shown in FIG. 3A, for an FPC 200 in which an upper wiring pattern 220 having lands M constituting an alignment mark and a lower wiring pattern 230 on which a wiring pattern for the output circuit 10 is formed are already bonded. As shown in FIG. 3B, a hole (hereinafter referred to as “through-hole hole”) O and a land M (alignment mark) are aligned with a portion that becomes the through-hole H, and the through-hole hole O is formed. The photoelectric conversion layer 110 is formed on the upper wiring pattern 220 while being formed. For example, in the case of the bilayer type organic thin film solar cell unit 100, a method of directly patterning the photoelectric conversion layer 110 on the upper wiring pattern 220 by printing, screen printing, or an ink jet method, or applying a photosensitive resist film after spin coating or the like. The photoelectric conversion layer 110 is formed on the upper wiring pattern 220 by providing, exposing and developing. Even in the case of a bulk hetero type organic thin film solar cell unit, a Schottky type organic thin film solar cell unit, or a dye-sensitized solar cell unit, the photoelectric conversion layer 110 is formed as in the bilayer type solar cell unit.

  Next, as illustrated in FIG. 3C, the hole extraction layer 113 is formed on the photoelectric conversion layer 110 while maintaining the through-hole hole O while aligning with the land M (alignment mark). For example, in the case of the bilayer type organic thin film solar cell unit 100, as with the photoelectric conversion layer 110, a method of directly patterning the photoelectric conversion layer 110 on the upper wiring pattern 220 by printing, screen printing, or inkjet method, spin coating, etc. After the coating, a photosensitive resist film is provided, exposed and developed, whereby the photoelectric conversion layer 110 is formed on the upper wiring pattern 220.

  Next, as shown in FIG. 3D, the transparent electrode is formed while forming the through hole H on the hole extraction layer 113. For example, in the case of the bilayer type organic thin film solar cell unit 100, a PVD method such as a vacuum deposition method, a sputtering method, an ion plating method, a dry coating method such as a CVD method, and a coating solution containing ITO fine particles. Etc. are applied and formed.

  Finally, as shown in FIG. 3E, a power supply circuit system S in which the electronic circuit element E and the integrated circuit chip I are mounted and the solar cell unit 100 is formed on the FPC 200 is generated.

  As described above, the power supply circuit system S of the present embodiment can share the upper wiring pattern 220 of the FPC 200 with the electrode of the solar cell unit 100, so that flexibility is ensured and the solar cell unit 100 is thinned. In addition, the output circuit 10 can be directly formed on the substrate on which the solar cell unit 100 is formed. Therefore, this power supply circuit system S is intended to reduce the thickness of the power supply circuit system S including the circuits necessary for outputting the voltage generated based on the solar cell unit 100 and to improve the efficiency of the space of the entire circuit. Therefore, it is highly versatile and can be mounted as a power supply circuit system S for various devices.

In addition, the power supply circuit system S of the present embodiment includes, for example, an electronic circuit element E such as a capacitor element, a coil element, a switch element, or a diode element, and an integrated circuit chip I such as a regulator, on the FPC 200 in which the solar cell unit 100 is formed. Therefore, for example, various circuits such as a circuit for controlling or adjusting a voltage generated by the solar cell unit 100 such as a regulator circuit or a booster circuit can be formed as the output circuit 10. Therefore, the power supply circuit system S can be properly controlled or adjusted the power supply voltage V _E in conjunction with an external electronic circuit that drives based on the power supply voltage V _E generated in the solar cell unit 100.

  In addition, the power supply circuit system S of the present embodiment can easily and accurately stack the solar cell unit 100 on the flexible printed circuit board in the manufacturing process by the alignment mark and the through hole H, and can output the transparent electrode layer 120 and the output. The lower wiring pattern 230 in which the circuit 10 is formed can be easily and accurately connected.

  Moreover, since the power supply circuit system S of this embodiment can connect the solar cell unit 100 and the lower wiring pattern 230 through the through hole H and the land M, the output configured to be stacked on the solar cell unit 100. Connection with the circuit 10 can be facilitated, and the space of the entire circuit can be effectively utilized. In particular, since the power supply circuit system S can effectively use the useless space of the alignment marks provided on the wiring pattern, the maximum power can be obtained without reducing the light receiving area of the solar cell unit 100. The area can be used for the light receiving surface.

  Further, the power supply circuit system S of the present embodiment can equivalently determine the resistance value from each position on the plane of the transparent electrode layer 120 even when the resistivity accompanying the material of the transparent electrode layer 120 such as ITO is high. Since the voltage can be lowered, the voltage efficiently generated from the solar cell unit 100 can be output.

  Next, a modified example of the power supply circuit system S according to the present embodiment will be described with reference to FIGS. 4 to 7 are other examples (I) to (IV) of the structure diagram showing the structure of the power supply circuit system S in the present embodiment.

  The first modification of the power supply circuit system S of the present embodiment is different from the above-described embodiment in that the electronic circuit element E and the integrated circuit chip I are mounted on the lower wiring pattern 230. The upper wiring pattern 220 formed on the surface on which the battery unit 100 is stacked is characterized in that the electronic circuit element E and the integrated circuit chip I are mounted, and other configurations are the same as those in the above-described embodiment. .

In the first modification, as shown in FIG. 4, the upper wiring pattern 220 is provided in parallel with the electrode portion, and the wiring pattern portion 222 on which the electronic circuit element and the integrated circuit chip I are mounted. And an integrated circuit chip I formed by combining a plurality of electronic circuit elements E such as a resistance element, a switch element, a capacitor element, or a coil element, and the electronic circuit element E is mounted on the wiring pattern portion. Then, the wiring pattern portion, with the electronic circuit elements E and the integrated circuit chip I, so as to constitute an output circuit 10 for controlling or adjusting the power source voltage V _E generated by the solar cell unit 100 .

  With this configuration, the power supply circuit system S of the first modified example can appropriately mount the electronic circuit element E or the integrated circuit chip I such as a capacitor element, a coil element, a switch element or a diode element on the upper wiring pattern 220. The output circuit 10 can be formed in consideration of the arrangement position of the power supply circuit system S.

  The second modification of the power supply circuit system S of the present embodiment uses a film in which a conductive material is formed in a mesh shape instead of the transparent electrode layer 120 in the solar cell unit 100 in the above-described embodiment. The other features are the same as those of the above-described embodiment.

  As shown in FIG. 5, a mesh-like electrode layer (hereinafter referred to as “mesh electrode layer”) 130 used for the electrode of the second modification has fine conductive particles such as silver on a predetermined transparent film. It is formed by pattern printing in a simple mesh shape so that it can be bent and any pattern can be formed.

  With this configuration, the power supply circuit system S according to the second modified example can reduce cost, has good compatibility with organic materials, and has high flexibility compared to the transparent electrode layer 120 using ITO, for example. Therefore, it is highly versatile and can be mounted as a power supply circuit system S for various devices.

  In the third modification of the power supply circuit system S of the present embodiment, a thin film transistor T10 is mounted instead of the electronic circuit element E and the integrated circuit chip I mounted on the lower wiring pattern 230 in the above-described embodiment. The other features are the same as those of the above-described embodiment.

  In the third modified example, as shown in FIG. 6, the lower pattern is formed with the output circuit 10 having the thin film transistor T10 attached to the base 210 in addition to the wiring portion. The wiring pattern 230 is connected to the solar cell unit 100 and is connected to an external electronic circuit (not shown) connected to the outside. With this configuration, the power supply circuit system S of the third modified example can also use the thin film transistor T10 for the output circuit 10.

  The fourth modification of the power supply circuit system S of the present embodiment is different from the above-described embodiment in that the electronic circuit element E and the integrated circuit chip I are mounted on the lower wiring pattern 230, and the The thin film diode D10 having the same stacked structure as the battery unit 100 is formed, and other configurations are the same as those of the above-described embodiment.

  In the fourth modification example, as shown in FIG. 7, the thin film diode D <b> 10 including the photoelectric conversion layer 110 and the transparent electrode layer 120 is formed on the upper wiring pattern 220 by the same process as the formation process of the solar cell unit 100. It is formed. The thin-film diode D10 has a stacked structure with the solar cell unit 100, that is, the upper wiring pattern 220 that forms the solar cell unit 100 in the upper wiring pattern 220, the photoelectric conversion layer 110, and the transparent electrode layer 120. The photoelectric conversion layer 110 and the transparent electrode layer 120 are insulated from each other, and a plurality of contact holes (through holes) 20A and 20B for connecting to the lower wiring pattern 230 are formed in a part where the thin film diode D10 is formed. Has been. The thin film diode D10 has a current characteristic in a direction as shown in FIG. A part of the upper wiring pattern 220 functions as one electrode of the diode D10, and is used as a part for exhibiting the characteristic function of the diode D10.

  In order to operate the thin film diode D10 accurately, a light shielding layer such as aluminum, silver paste or photosensitive resist may be provided on the transparent electrode layer 120 of the thin film diode D10. In addition to the through hole H, the solar cell unit 100 has a contact hole 20C for connecting to the lower electrode pattern.

  With this configuration, in the power supply circuit system S of the fourth modified example, when the output circuit 10 includes the thin film diode D10, the power supply circuit system S can be easily manufactured, and the upper wiring pattern 220 includes the diode D10. Is used as a part for demonstrating the characteristic function of the diode D10 that cuts off the current, so that the space of the output circuit 10 can be improved.

  Next, a modification of the method for manufacturing the power supply circuit system S of the present embodiment will be described with reference to FIG. In addition, FIG. 8 is a figure for demonstrating the other example of the manufacturing method of the power supply circuit system S in this embodiment.

  In the manufacturing method of the modified example of the present embodiment, a solar cell is already formed on the FPC 200 having the predetermined upper wiring pattern 220 and lower wiring pattern 230 and the electronic circuit element E and the integrated circuit chip I on the lower wiring pattern 230. This is a method of forming the unit 100. Moreover, in this manufacturing method, it demonstrates using the manufacturing method in the case of forming the bilayer type organic thin film solar cell unit 100. FIG.

  First, as shown in FIG. 8A, the upper wiring pattern 220 having the land M constituting the alignment mark and the wiring pattern for the output circuit 10 were formed, and the circuit element and the integrated circuit chip I were already mounted. As shown in FIG. 8B, the jig J is fitted into the FPC 200 so that the electronic circuit and the integrated circuit chip I do not contact the jig J with respect to the FPC 200 in which the lower wiring pattern 230 is formed.

  Next, as shown in FIG. 8C, the through-hole hole O to be the through-hole H and the land M (alignment mark) are aligned, and photoelectric conversion is performed on the upper wiring pattern 220 while forming the through-hole hole O. Layer 110 is formed. For example, in the case of the bilayer type organic thin film solar cell unit 100, a method of directly patterning the photoelectric conversion layer 110 on the upper wiring pattern 220 by printing, screen printing, or an ink jet method, or applying a photosensitive resist film after spin coating or the like. The photoelectric conversion layer 110 is formed on the upper wiring pattern 220 by providing, exposing and developing. Even in the case of a bulk hetero type organic thin film solar cell unit, a Schottky type organic thin film solar cell unit, or a dye-sensitized solar cell unit, the photoelectric conversion layer 110 is formed as in the bilayer type solar cell unit.

  Next, as illustrated in FIG. 8D, the hole extraction layer 113 is formed on the photoelectric conversion layer 110 while maintaining the through-hole hole O while matching the land M (alignment mark). For example, in the case of the bilayer type organic thin film solar cell unit 100, as in the photoelectric conversion layer, a method of directly patterning the photoelectric conversion layer 110 on the upper wiring pattern 220 by printing, screen printing, or inkjet method, spin coating, etc. A photoelectric resist layer 110 is formed on the upper wiring pattern 220 by providing a photosensitive resist film after coating, exposing and developing.

  Next, as illustrated in FIG. 8E, a power supply circuit system S including the solar cell unit 100 in which a transparent electrode is formed on the hole extraction layer 113 is generated. For example, in the case of the bilayer type organic thin film solar cell unit 100, a PVD method such as a vacuum deposition method, a sputtering method, an ion plating method, a dry coating method such as a CVD method, and a coating containing ITO fine particles. It is formed by applying a working fluid or the like.

  Finally, as shown in FIG. 8F, the jig J is removed from the FPC 200, and the power supply circuit system S in which the solar cell unit 100 is formed on the FPC 200 is generated.

[Second Embodiment]
Next, a second embodiment of the power supply circuit system S according to the present invention will be described with reference to FIGS. 9 and 10.

  The power supply circuit system S of this embodiment uses capacitor elements C10 and C20 formed by a circuit pattern and a regulator R as an integrated circuit chip I in the output circuit 10 of the first embodiment (see FIG. 9 and FIG. The other components are the same as those in the first embodiment, and the same members are denoted by the same reference numerals and description thereof is omitted.

  First, the structure of the power supply circuit system S of this embodiment and its equivalent circuit will be described with reference to FIGS. 9 and 10. FIG. 9 is a structural diagram showing the structure of the power supply circuit system S in the present embodiment, and FIG. 10 is an equivalent circuit of the power supply circuit system S in the present embodiment.

Power circuit system S of this embodiment, as shown in FIG. 9, the solar cell unit 100 to produce a supply voltage _{V E,} the upper wiring pattern 220, the regulator R, the first capacitor C10 and the second capacitor C20 is formed FPC 200 including the lower wiring pattern 230 that is formed. In particular, the upper wiring pattern 220 of the present embodiment, the lower wiring pattern 230, the regulator R, the first capacitor C10 and the second capacitor C10 is a regulator circuit for stabilizing the power supply voltage _{V E} generated in the solar cell unit 100 Configure.

  In the lower wiring pattern 230, a first capacitor C10 and a second capacitor C20 formed by a part of the pattern, and an integrated circuit chip I including a regulator R are formed. In particular, the first capacitor C10 and the second capacitor C20 are formed by a part of the corresponding lower wiring pattern 230 and a part of the upper wiring pattern 220 formed to face each other with the base 210 interposed therebetween. That is, the first capacitor C10 and the second capacitor C20 include a planar electrode formed of a lower wiring pattern 230 formed at a predetermined position and an upper wiring pattern formed at a position corresponding to the position of the lower wiring pattern 230. And a planar electrode made of 220.

  Thus, in this embodiment, the upper wiring pattern 220 and the lower wiring pattern 230 are used as a part for constituting the electrode of the capacitor element and exhibiting the characteristic function of capacitance. In the upper wiring pattern 220, a connection pattern for grounding is formed for the pattern efficiency of the lower wiring pattern 230.

The power supply circuit system S of the present embodiment forms an equivalent circuit as shown in FIG. 10, and constitutes a regulator circuit. Specifically, in the power supply circuit system S, the first capacitor C10 is connected in parallel to the solar cell unit 100 and is connected to one end of the regulator R. In particular, the first capacitor C10 is inputted to the regulator R, is adapted to smooth the generated power source voltage V _E in the solar cell unit 100. The second capacitor C20 is connected between the ground of the regulator at the other end and the output terminal 30, an output terminal 30 as an output voltage V _O of the voltage output from the regulator R is smoothed, i.e., an external electronic not shown Output to the circuit.

  As described above, in addition to the effects of the first embodiment, the power supply circuit system S of the present embodiment can form the capacitor element by the laminated structure of the patterns formed on the FPC 200, so that only the lower wiring pattern 230 is formed. The thickness can be reduced without using an element having a thickness such as a lead-type or chip-type capacitor element mounted on the output circuit 10, and the space of the output circuit 10 can be improved.

  Further, the power supply circuit system S can improve the space efficiency of the entire circuit by eliminating the wiring for mounting the capacitor element on the FPC 200, and the electronic circuit element E is formed together with the solar cell unit 100. Therefore, it is possible to mount a capacitor element having a large capacitance and improve circuit characteristics.

  In the power supply circuit system S of the present embodiment, a coil element that is a planar coil is disposed at the same position on the upper wiring pattern 220 and the lower wiring pattern 230, respectively, instead of the first capacitor C10 and the second capacitor C20. Mutual inductance can be generated.

[Third embodiment]
Next, a third embodiment of the power supply circuit system S according to the present invention will be described with reference to FIGS.

  The power supply circuit system S of the present embodiment is characterized in that instead of the output circuit 10 configuring a regulator circuit in the second embodiment, a booster circuit is configured (see FIGS. 11 and 12 described later). Other configurations are the same as those of the first embodiment, and the same members are denoted by the same reference numerals and the description thereof is omitted. In particular, the present embodiment is characterized in that the lower wiring pattern 230 is provided with a planar coil L, a regulator R that controls the transistor T20, a diode D20, and a transistor T20.

  First, the structure of the power supply circuit system S of this embodiment and its equivalent circuit will be described with reference to FIGS. 11 and 12. FIG. 11 is a structural diagram showing the structure of the power supply circuit system S in the present embodiment, and FIG. 12 is an equivalent circuit of the power supply circuit system S in the present embodiment.

Power circuit system S of this embodiment, as shown in FIG. 11, a solar cell unit 100 to produce a supply voltage V _E, the regulator R, the diode D20 and the transistor with the planar coil L and the second capacitor C20 is formed The FPC 200 includes a lower wiring pattern 230 on which T20 is mounted and an upper wiring pattern 220 that connects them.

In the lower wiring pattern 230, along with the formed circuit pattern, a second capacitor C20 and a planar coil L are formed, and a diode D20 and a transistor T20 are mounted. Further, this lower wiring pattern 230, the regulator R that controls the switching of the transistor T20 are implemented as an integrated circuit chip I with stabilizing the power supply voltage V _E generated by the solar cell unit 100.

  As described above, in the present embodiment, as in the second embodiment, the upper wiring pattern 220 and the lower wiring pattern 230 constitute electrodes of the capacitor element and are used as a part for exhibiting the characteristic function of capacitance. It is used. Furthermore, the lower wiring pattern 230 functions as a portion that constitutes the planar coil L and exhibits a characteristic function of inductance.

  Note that the second capacitor C20 of this embodiment includes a part of the corresponding lower wiring pattern 230 and a part of the upper wiring pattern 220 formed to face each other via the base 210, as in the above-described embodiment. , Formed by. Further, in the upper wiring pattern 220 of the present embodiment, a connection pattern related to grounding is formed in addition to the portion functioning as the back electrode of the solar cell unit 100, as in the second embodiment.

The power supply circuit system S of this embodiment forms an equivalent circuit as a booster circuit as shown in FIG. The regulator R controls an LBI (Low Battery Input) terminal to which a voltage is input, a _VOUT terminal that outputs a voltage, an EXT (Exit) terminal that controls driving of the transistor T20, and a voltage to be stabilized. A VFB (Feedback Voltage) terminal to be grounded and a ground terminal to be grounded.

The planar coil L is connected between the power supply voltage V _E (solar cell unit 100), the diode D20, and the drain of the transistor T20, and accumulates a voltage based on the power supply voltage V _E at a predetermined timing. Are output from the output terminal 30 to an external electronic circuit connected to the outside together with the voltage stored in the second capacitor C20.

The diode D20 is connected between the planar coil L and the output terminal 30 and the _VOUT terminal of the regulator R, and allows a current to flow from the planar coil L to the output terminal 30, but is planar from the _VOUT terminal or the output terminal 30 of the regulator R. The current flow to the coil L is prohibited.

The second capacitor C20 serves to accumulate a predetermined voltage based on the power supply voltage V _E at a predetermined timing, the external electronic circuit (not shown) with the stored voltage to the accumulated planar coil voltage L from the output terminal 30 It has a function to output.

  The transistor T20 operates as a switching transistor and outputs the voltage accumulated in the planar coil L based on the output of the EXT terminal of the regulator R from the output terminal 30 to the external electronic circuit. Specifically, the transistor T20 is connected between the drain and the source without switching driving based on the control of the regulator R when the voltage is accumulated in the second capacitor C20 and when the voltage is output to the outside. In addition to being insulated, when the voltage is accumulated in the planar coil L, it is driven based on the control of the regulator R and the drain-source is energized.

  As described above, the power supply circuit system S of the present embodiment can form a booster circuit as the output circuit 10 in addition to the same effects as those of the second embodiment. Even when only a voltage smaller than the voltage required for driving can be generated, it can be used for driving the external electronic circuit.

  As shown in FIG. 13, in the lower wiring pattern 230 of the power supply circuit system S of the present embodiment, a switch SW may be formed between the second capacitor C20 and the output terminal 30. In this case, as shown in FIG. 11, the power supply circuit system S forms a switch SW in series between one end on the output terminal 30 side and one end of the second capacitor C20, and operates accurately as a booster circuit. You may do it.

That is, the switch SW is turned off when the voltage is accumulated in the planar coil L and when the voltage is accumulated in the second capacitor C20, and the voltage accumulated in the planar coil L and the second capacitor C20 is externally applied. It turned on when outputting to the electronic circuit, and is capable of outputting accurately a voltage higher than the power supply voltage V _E generated in the solar cell unit 100. FIG. 13 is a modification of the equivalent circuit of the power supply circuit system S in the present embodiment.

[Fourth embodiment]
Next, a fourth embodiment of the power supply circuit system S according to the present invention will be described with reference to FIGS.

  The power supply circuit system S of the present embodiment is characterized in that, in the third embodiment, a plurality of solar cell units 100 are provided and connected in parallel (see FIG. 14 described later). Is the same as that of the third embodiment (including the first and second embodiments), and the same members are denoted by the same reference numerals and description thereof is omitted.

  First, the structure of the power supply circuit system S of the present embodiment will be described with reference to FIG. FIG. 14 is a structural diagram showing the structure of the power supply circuit system S in the present embodiment.

Power circuit system S of this embodiment, as shown in FIG. 14, a solar cell unit 100 to produce a supply voltage V _E of the plurality of (eight), to form a step-up circuit as in the third embodiment each The FPC 200 includes an upper wiring pattern 220 and a lower wiring pattern 230 for connecting the solar cell units 100 in parallel.

  Each solar cell unit 100 of the present embodiment is arranged in parallel on the upper wiring pattern 220 and is connected in parallel with other solar cell units 100 through through holes H formed in each solar cell unit 100. Yes. One solar cell unit 100 is connected to the planar coil L by the lower wiring pattern 230.

As described above, the power supply circuit system S of the present embodiment can increase the current generated from the solar cell unit 100 a plurality of times and stably generate, in addition to the same effects as those of the first embodiment. can output the power supply voltage V _E.

  In addition, the portable power circuit system S of the present embodiment can output a stable and constant voltage even when light does not strike a part of the solar cell unit 100 due to dirt or shade.

  In addition, although the power supply circuit system S of this embodiment has the eight solar cell units 100, you may have the solar cell unit 100 of the number below this or more.

  In the power supply circuit system S of the present embodiment, an electrode terminal of a type that fits into a socket for connecting the output circuit 10 and an external electronic circuit may be provided in the lower wiring pattern 230 of the FPC 200.

For example, as shown in FIG. 15, the FPC 200 according to the present embodiment includes a connector portion 250 that extends from a part of the base 210 to the base 210, and is formed at a predetermined pitch on the connector portion 250. The plurality of electrode terminals 251 formed integrally with the wiring pattern 230, the back surface thereof, that is, the reinforcing plate 252 formed on the surface of the base 210 on the upper wiring pattern 220 side, and a portion other than the tip of the electrode terminal are protected. And a protective film 253. The connector portion 250 is connected to the FPC socket 310 of the external electronic circuit 300 and outputs the adjusted power supply voltage _VE to the external electronic circuit 300. FIG. 15 is a modification of the structural diagram of the power supply circuit system S in the present embodiment.

[Fifth Embodiment]
Next, a fifth embodiment of the power supply circuit system S according to the present invention will be described with reference to FIG.

  The power supply circuit system S of this embodiment replaces the point where the plurality of solar cell units 100 are connected in parallel in the fourth embodiment, and is a point where the plurality of solar cell units 100 are connected in series (described later). The other features are the same as in the fourth embodiment (including the first, second, and third embodiments), and the same members are denoted by the same reference numerals. Therefore, the description is omitted.

  The structure of the power supply circuit system S of this embodiment will be described with reference to FIG. FIG. 16 is a structural diagram showing the structure of the power supply circuit system S in the present embodiment.

Power circuit system S of this embodiment, as shown in FIG. 16, a solar cell unit 100 to produce a supply voltage V _E of the plurality of (eight), to form a step-up circuit as in the third embodiment each The FPC 200 includes an upper wiring pattern 220 and a lower wiring pattern 230 for connecting the solar cell units 100 in series.

  Each solar cell unit 100 of the present embodiment is arranged in parallel on the upper wiring pattern 220 and is connected in series with the adjacent solar cell units 100 through through holes H formed in each solar cell unit 100. Yes. One solar cell unit 100 is connected to the output circuit 10 by the lower wiring pattern 230. Note that, unlike the fourth embodiment, the output circuit 10 of the present embodiment is appropriately mounted with a predetermined electronic circuit element E and the like.

  As described above, the power supply circuit system S of the present embodiment can multiply the voltage generated from the solar cell unit 100 by a plurality of times in addition to the same effects as those of the first embodiment.

  In addition, although the power supply circuit system S of this embodiment has the eight solar cell units 100, you may have the solar cell unit 100 of the number below this or more.

C10: first capacitor C20: second capacitor D10, D20: diode T10, T20 ... transistor E ... electronic circuit element H ... through hole I ... integrated circuit chip J ... jig L ... planar coil M ... land O ... for through hole Hole R ... Regulator S ... Power supply circuit system 10 ... Output circuit 20 ... Contact hole 30 ... Output terminal 100 ... Solar cell unit 110 ... Photoelectric conversion layer 111 ... N-type organic semiconductor layer 112 ... P-type organic semiconductor layer 113 ... Hole extraction Layer 115 ... Mixed layer 117 ... Oxide semiconductor layer 120 ... Transparent electrode layer 130 ... Mesh electrode layer 200 ... FPC
210 ... Base 220 ... Upper wiring pattern 230 ... Lower wiring pattern 250 ... Connector portion 251 ... Electrode terminal 252 ... Reinforcing plate 253 ... Protective film 300 ... External electronic circuit 310 ... Socket

Claims (14)

A first electrode layer, a photoelectric conversion layer that is stacked on the first electrode layer and performs photoelectric conversion for generating a voltage from received light, and is stacked on the photoelectric conversion layer, the photoelectric conversion layer A second electrode layer having a structure for receiving light in the solar cell unit,
An output circuit for outputting the voltage generated by the photoelectric conversion and a flexible printed circuit board on which a wiring pattern for connecting the solar cell unit is formed;
With
The said wiring pattern is formed on the base material which comprises the said flexible printed circuit board as a said 1st electrode layer, The solar cell system characterized by the above-mentioned. The solar cell system according to claim 1,
The solar cell system, wherein the wiring pattern includes a circuit pattern in which an output circuit constituted by electronic circuit components is formed. The solar cell system according to claim 2, wherein
The solar cell system, wherein the circuit pattern is used as at least a part for exhibiting a characteristic function of the electronic circuit component. In the solar cell system according to claim 3,
A first circuit pattern is formed as the circuit pattern on the first substrate surface on which the solar cell unit of the base material is disposed, and a second substrate surface opposite to the first substrate surface. In addition, a second circuit pattern is formed as the circuit pattern,
The electronic circuit component is configured by the first circuit pattern and the second circuit pattern. In the solar cell system according to any one of claims 2 to 4,
An electronic circuit component that constitutes the output circuit is mounted on the circuit pattern. In the solar cell system according to claim 2 or 3,
The solar cell system, wherein the circuit pattern is formed on a first substrate surface on a side of the base material on which the solar cell unit is disposed. The solar cell system according to claim 6, wherein
The electronic circuit component is formed on the circuit pattern by including the same laminated structure as the solar cell unit, and the photoelectric conversion layer and the second electrode layer formed on the circuit pattern and the circuit pattern. A solar cell system characterized by that. In the solar cell system according to claim 2 or 3,
The solar cell system, wherein the circuit pattern is formed on a second substrate surface opposite to the first substrate surface on which the solar cell unit is disposed on the base material. In the solar cell system according to any one of claims 1 to 8,
The solar cell system, wherein the flexible printed circuit board further includes an electrode terminal for connecting to an electronic circuit driven by the generated voltage. In the solar cell system according to any one of claims 1 to 9,
While the solar cell unit has a through hole for connecting the second electrode layer and the output circuit while being insulated from the photoelectric conversion layer,
The solar cell system, wherein the wiring pattern has a land joined to the through hole. The solar cell system according to claim 10, wherein
The solar cell system, wherein the land has a shape for functioning as an alignment mark used when positioning the solar cell unit on the wiring pattern. The solar cell system according to claim 10, wherein
The solar cell system, wherein the through hole and the land are formed in the vicinity of the center of the solar cell unit when the solar cell unit is mounted on the flexible printed board. The solar cell system according to any one of claims 1 to 9,
An alignment mark for positioning a position where the solar cell unit is disposed is formed on the wiring pattern. A manufacturing method for manufacturing a solar cell system comprising a solar cell unit and a flexible printed circuit board on which an output circuit that performs output control of the voltage generated by the solar cell unit is formed,
A preparation step of preparing the flexible printed circuit board having a wiring pattern for connecting the solar cell unit and the output circuit and having the output circuit formed thereon;
A photoelectric conversion layer forming step for forming a photoelectric conversion layer on which photoelectric conversion for generating a voltage from received light is performed on the wiring pattern;
A surface electrode layer forming step of forming a surface electrode layer laminated on the photoelectric conversion layer and having a structure for allowing the photoelectric conversion layer to receive light;
Including
The solar cell system, wherein the wiring pattern is used as a back electrode layer of the solar cell unit.

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