JP2011077169A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device capable of preventing electrical short-circuiting between wires by preventing contact between wires that occurs when a liquid resin is poured.
A rectangular main surface of a semiconductor chip CH includes first and second sides connecting the first and second vertices A1 and A2 on the diagonal line and the first and second vertices A1 and A2. L1 and L2. A wire WR is formed between the electrode IL and the pad PD of the semiconductor chip CH. The wire WR is accommodated in the cavity CV of the mold ML. The liquid resin is poured into the cavity CV from the first vertex A1 toward the second vertex A2 along the first and second sides L1, L2. The resin portion is formed by curing the liquid resin. Formation of the wire WR is performed by forming the wire WR so as to pass through a side far from the first vertex A1 with respect to a straight line connecting the pad PD and the electrode IL in plan view.
[Selection] Figure 14

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a resin portion for sealing a wire.

  When the semiconductor package is viewed from a sealing structure, it can be divided into two, an airtight sealed package and a non-airtight sealed package. Among non-hermetic sealed packages, transfer mold type plastic packages are currently the mainstream.

  The technology of the transfer mold type plastic package is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-314003 (Patent Document 1). According to this technique, the method for manufacturing a semiconductor device includes the following steps.

  An IC chip is fixed on the resin frame by a die bond material. The bonding pad on the IC chip and the land of the resin frame are electrically connected by wire bonding. By performing transfer molding using a mold, the IC chip is resin-sealed.

JP 2002-314003 A

  When a chip having a large number of dense bonding pads such as SoC (System on Chip) is used, wires connected to the bonding pads are also formed densely. These wires are pushed to some extent in the flow direction by the molding resin that is a fluid in the transfer molding process. At this time, there is a problem that an electrical short circuit between the wires is caused when the specific wire is swept away particularly greatly and comes into contact with the wire on the downstream side.

  This invention is made | formed in view of said subject, The objective can prevent the electrical short circuit between wires by preventing the contact between the wires which arises in the case of pouring of liquid resin. A method for manufacturing a semiconductor device is provided.

  A method of manufacturing a semiconductor device according to an embodiment of the present invention includes a rectangular shape having first and second vertices that are diagonal to each other and first and second sides that connect the first and second vertices. And a semiconductor chip including a first pad on the main surface, an electrode, a wire connecting the first pad and the electrode, and a resin portion for sealing the wire A method for manufacturing an apparatus, which includes the following steps.

  A wire is formed between the first pad and the electrode. A wire is contained in the cavity of the mold. Liquid resin is poured into the cavity from the first vertex toward the second vertex along the first and second sides. The resin portion is formed by curing the liquid resin. The wire is formed by forming the wire so as to pass through a side far from the first vertex with respect to a straight line connecting the first pad and the electrode in plan view.

  A method of manufacturing a semiconductor device according to another embodiment of the present invention includes a first main surface having a rectangular main surface having first and second sides sharing a vertex, and a pad group on the main surface. The semiconductor device manufacturing method includes the semiconductor chip, the electrode group, the wire group that connects the pad group and the electrode group, and the resin portion that seals the wire group, and includes the following steps. A wire group is formed between the pad group and the electrode group. The step of forming the wire group includes a first wire belonging to the wire group and intersecting the second side in plan view between the first pad belonging to the pad group and the first electrode belonging to the electrode group. Forming a step. A group of wires is contained in the cavity of the mold. Liquid resin is poured into the cavity. The step of pouring the liquid resin is performed such that the liquid resin flows to the position along the second side through the position along the first side and the position around the apex in order. The resin portion is formed by curing the liquid resin. The step of forming the first wire is performed by forming the first wire so as to pass through the side closer to the apex with respect to the straight line connecting the first pad and the first electrode in plan view. .

  According to the method of manufacturing a semiconductor device of the above embodiment, the side far from the first apex of the semiconductor chip, that is, the downstream side of the flow of the liquid resin with respect to the straight line connecting the first pad and the electrode. A wire is formed to pass through. Thereby, the dispersion | variation between wires of the grade by which a wire is pushed away from the upstream to the downstream by liquid resin is suppressed. Therefore, it is possible to prevent a specific wire from being greatly swept away and contact with another wire, so that an electrical short circuit between the wires can be prevented.

  According to the method of manufacturing the semiconductor device of the other embodiment, the side near the first apex of the semiconductor chip, that is, the flow of the liquid resin with respect to the straight line connecting the first pad and the first electrode. A first wire is formed so as to pass upstream of the first wire. Thereby, since the space | interval of a 1st wire and the wire located in the downstream of the flow of liquid resin with respect to this 1st wire can be enlarged, the electrical short circuit between wires can be prevented. it can.

1 is a perspective view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic sectional drawing in alignment with line II-II of FIG. It is a top view which shows schematically the structure in the inside of the resin part of FIG. It is a top view for demonstrating arrangement | positioning of what was connected to the outer periphery bonding pad of the semiconductor chip among the bonding wires of FIG. It is a top view for demonstrating arrangement | positioning of what was connected to the inner periphery bonding pad of the semiconductor chip among the bonding wires of FIG. It is a fragmentary sectional view which shows schematically the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic fragmentary sectional view for demonstrating the shape of the bonding wire of FIG. FIG. 8 is a schematic cross-sectional view for explaining the height of the bonding wire in FIG. 7. FIG. 8 is a schematic partial cross-sectional view taken along line IX-IX in FIG. 7. FIG. 8 is a schematic partial plan view seen from an arrow X in FIG. 7. It is the schematic partial perspective view seen from the arrow XI of FIG. It is a fragmentary top view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. FIG. 13 is a schematic partial sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a schematic partial cross-sectional view taken along line XIV-XIV in FIG. 13. It is a fragmentary sectional view which shows roughly the 1st process of the manufacturing method of the semiconductor device in a comparative example, and is a figure corresponding to FIG. 9 of this Embodiment. It is a fragmentary sectional view which shows roughly the 1st process of the manufacturing method of the semiconductor device in a comparative example, and is a figure corresponding to FIG. 14 of this Embodiment. It is a fragmentary top view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in a comparative example. It is a fragmentary sectional view showing roughly the 2nd process of a manufacturing method of a semiconductor device in a comparative example. It is sectional drawing which shows roughly 1 process of the manufacturing method of the semiconductor device in the modification of Embodiment 1 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is a top view which shows schematically the structure in the inside of the resin part of FIG. It is a schematic enlarged view of the broken line part XXII of FIG. It is sectional drawing which shows roughly 1 process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows roughly 1 process of the manufacturing method of the semiconductor device in the modification of Embodiment 2 of this invention. It is a top view which shows roughly the 1st process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. FIG. 26 is a partially enlarged view of FIG. 25. It is sectional drawing which shows schematically the upper metal mold | die used in the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows schematically the lower metal mold | die used in the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic diagram which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. FIG. 30 is a partially enlarged view of FIG. 29.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
Referring to FIG. 1, the semiconductor device of the present embodiment is a transfer mold type plastic package QP, for example, a QFP (Quad Flat Package). This type of package QP has an outer lead portion OL protruding from each of the four outer peripheral sides of the resin portion MR that seals the semiconductor chip CH. The semiconductor chip CH has a rectangular main surface (the upper surface in the drawing). The main surface has first and second vertices A1 and A2, and first and second sides L1 and L2. The first and second vertices A1 and A2 are located diagonally to each other. The first and second sides L1 and L2 connect the first and second vertices A1 and A2.

  2-5, the above-described semiconductor chip CH, lead frame LF, and bonding wire WR are arranged inside the resin portion MR.

  The semiconductor chip CH has a bonding pad PD on the main surface. Bonding pad PD has an inner peripheral bonding pad PD1 (first pad) located on the inner peripheral side of the main surface and an outer peripheral bonding pad PD2 (second pad) located on the outer peripheral side of the main surface. . The distance between the outer edge of the main surface and the outer peripheral bonding pad PD2 is smaller than the distance between the outer edge and the inner peripheral bonding pad PD1.

  The bonding wire WR has an inner peripheral bonding wire WR1 and an outer peripheral bonding wire WR2. The inner peripheral bonding wire WR1 connects the inner peripheral bonding pad PD1 and the lead frame LF. The outer peripheral bonding wire WR2 connects the outer peripheral bonding pad PD2 and the lead frame LF. As shown in FIG. 2, the inner peripheral bonding wire WR1 is provided so as to jump over the outer peripheral bonding wire WR2. For this reason, the height of the inner peripheral bonding wire WR1 is set higher than the height of the outer peripheral bonding wire WR2.

  The lead frame LF includes a die pad DP, a plurality of inner lead portions IL (electrodes), a bus bar BB, a grounding ring GR, a connection portion CP, and a suspension lead SL inside the resin portion MR. The outer lead part OL (electrode) is provided outside the resin part MR.

  The die pad DP is located approximately at the center of the lead frame LF. A semiconductor chip CH is mounted on the die pad DP via an adhesive.

  The plurality of inner lead portions IL are portions that exchange input / output signals with the semiconductor chip CH, and are arranged in a radial pattern with the semiconductor chip CH at the center, for example. The tips of the plurality of inner lead portions IL are located on the outer peripheral side of the outer edges of the die pad DP and the semiconductor chip CH in plan view.

  The bus bar BB is for supplying a power supply potential to the semiconductor chip CH, for example. The bus bar BB has a bent portion ST.

  The ground ring GR is for supplying a ground potential to the semiconductor chip CH. The ground ring GR is located on the outer peripheral side with respect to the outer edge of the die pad DP in a plan view, and is located on the inner peripheral side with respect to the protruding portion of the bus bar BB. The ground ring GR is disposed so as to surround the entire outer periphery of the die pad DP. In addition, a bent portion ST1 is formed between the ground ring GR and the die pad DP, which is bent so that the upper surface of the die pad DP is lower than the upper surface of the ground ring GR. In addition, a bent portion ST2 is formed between the ground ring GR and the suspension lead SL, which is bent so that the upper surface of the ground ring GR is lower than the upper surface of the suspension lead SL.

  The connecting portion CP is for connecting the die pad DP and the ground ring GR, and is provided, for example, two on each side of the die pad DP in plan view. The suspension lead SL is connected to each of the four corners of the ground ring GR, and extends from the connection portion with the ground ring GR to the outer peripheral side.

  Some of the outer peripheral bonding pads PD2 are electrically connected to the protruding portion of the bus bar BB by an outer peripheral bonding wire WR2. The remaining some of the outer peripheral bonding pads PD2 are electrically connected to the ground ring GR by outer peripheral bonding wires WR2.

  Some of the inner peripheral bonding pads PD1 are electrically connected to the inner lead portion IL by an inner peripheral bonding wire WR1. For example, one of the inner peripheral bonding pads PD1 is electrically connected to the parallel running portion of the bus bar BB by an inner peripheral bonding wire WR1.

  Referring mainly to FIGS. 6 to 11, first, a lead frame LF is prepared. Next, the semiconductor chip CH is bonded onto the die pad DP of the lead frame LF via an adhesive or the like.

  Next, a bonding wire WR is formed from the bonding pad PD to the lead frame LF, whereby wire bonding between the bonding pad PD and the lead frame LF is performed. More specifically, the outer peripheral bonding wire WR2 is first formed from the outer peripheral bonding pad PD2 to the lead frame LF, and then the inner peripheral bonding wire WR1 is formed from the inner peripheral bonding pad PD1 to the lead frame LF.

  The bonding wire WR is formed on the side (in the drawing) farther from the first vertex A1 (FIG. 1) than the straight line (broken line in FIGS. 10 and 11) connecting the bonding pad PD and the lead frame LF in plan view. The bonding wire WR is formed so as to pass through (the side to which the arrow M is directed). This arrow M corresponds to the flow direction of the liquid resin described later.

  The bonding wire WR has portions Wa to Wc. The portion Wa rises substantially vertically from the bonding pad PD. The part Wb connects the part Wa and the part Wc. The portion Wc connects the portion Wb and the lead frame LF such as the inner lead portion IL. A bending point F is formed between the part Wb and the part Wc during wire bonding.

  The shape change in the height direction of the bonding wire WR will be described in more detail. As shown in FIG. 8, the bonding wire WR is bent between the bonding pad PD and the inner lead part IL, at bending points G1, G2, and F in order. Of the bonding wire WR, the portion from the bonding pad PD to the bending point G1 corresponds to the portion Wa, the portion from the bending point G1 to the bending point F via the bending point G2 corresponds to the portion Wb, and the bending point F To the inner lead portion IL corresponds to the portion Wc.

  Each of the bending points G1, G2, and F (FIG. 8) has heights HG1, HG2, and HF as heights from the surface of the semiconductor chip CH. The heights HG1, HG2, and HF of the bonding wire WR are, for example, 80 μm, 195 μm, and 175 μm.

  The bending point F is a side farther from the first vertex A1 (FIG. 1) than the straight line (dashed line in FIGS. 10 and 11) connecting the bonding pad PD and the lead frame LF in plan view (upper side in FIG. 10). , Right side of FIG. 11). As shown in FIG. 9, the bonding wire WR extends along a plane inclined by an angle TH with respect to the normal line of the main surface of the semiconductor chip CH in the vicinity of the bending point F. The angle TH is, for example, 20 degrees.

  12 to 14, a mold ML for transfer molding is prepared. The mold ML has an upper mold MLa and a lower mold MLb. The upper mold MLa and the lower mold MLb have such a shape that the cavity CV is formed by facing each other.

  Next, the outer lead part OL is sandwiched between the upper mold MLa and the lower mold MLb. As a result, the bonding wire WR is accommodated in the cavity CV.

  Next, as shown by an arrow M (FIGS. 12 and 14), from the first vertex A1 (FIG. 14) to the second vertex A2 along the first and second sides L1 and L2, Liquid resin is poured into the cavity CV. By flowing the liquid resin, the angle TH (FIG. 9) is increased from 20 degrees to 10 ± 5 degrees, for example, to 30 ± 5 degrees. That is, the degree of increase in the angle TH has a variation of about ± 5 degrees between the bonding wires WR.

  Referring to FIG. 8, the heights HG2 and HF of bonding wire WR are reduced by the above-described pouring of the liquid resin. For example, the height HG2 decreases from 195 μm to 170 μm, and the height HF decreases from 175 μm to 165 μm.

  The liquid resin is cured to form a resin portion MR (FIG. 1). Next, the outer lead OL (FIG. 1) is cut and bent. Thereby, the semiconductor device of the present embodiment is manufactured.

Next, a comparative example of the present embodiment will be described.
Referring to FIGS. 15 and 16, bonding wire WZ of this comparative example is inclined with respect to the main surface of semiconductor chip CH before the liquid resin is poured, unlike bonding wire WR (FIG. 9) of the present embodiment. (Inclination shown at an angle TH in FIG. 9). Thereby, the bonding wire WZ has a linear shape in plan view as shown in FIG. The heights HG1, HG2, and HF (FIG. 8) of the bonding wire WZ are, for example, 80 μm, 200 μm, and 200 μm.

  Referring to FIGS. 17 and 18, when the liquid resin is poured into bonding wire WZ in the direction of arrow M, bonding wire WZ is bent in the direction of arrow M in plan view as shown in FIG. To be washed away. As a result, the bonding wire WZ has a shape close to the shape shown in FIG. 9, but the variation in the angle TH (FIG. 9) between the bonding wires WZ is larger than that in the present embodiment. That is, the angle TH (FIG. 9) of the bonding wire WZ after the liquid resin is poured becomes, for example, 30 ± 20 degrees, and the variation in the angle TH is smaller than the angle TH = 30 ± 5 degrees in the present embodiment. growing.

  As described above, since the variation to the extent that the bonding wire WZ is pushed into the liquid resin is large, a short circuit SC due to contact between the bonding wires WZ is likely to occur as shown in FIG. This short circuit SC causes a failure of the semiconductor device.

  Referring to FIG. 8, the heights HG2 and HF of bonding wires WZ are reduced by the above-described pouring of the liquid resin. For example, the height HG2 decreases from 200 μm to 170 μm, and the height HF decreases from 200 μm to 165 μm. In other words, when the pouring of the liquid resin is completed, the height of the bonding wire WZ of the comparative example and the height of the bonding wire WR of the present embodiment are on the same order on average. The reason for this is presumed that when the height of the bonding wire is lowered to some extent, the displacement of the bonding wire stops due to the balance between the force caused by the flow of the liquid resin and the tension of the bonding wire.

  Further, the final angle TH (FIG. 9) of the bonding wire WR of the present embodiment and the final angle TH of the bonding wire WZ of the comparative example are both about the same, for example, 30 ° as an average value. . As described above, the reason why the angle TH is approximately the same between the present embodiment and the comparative example is that, as described above, the bonding wire is stopped to a certain extent by the height of the bonding wire being lowered to some extent, Further, it is presumed that bending at the bending point F (FIG. 9) is acting. Specifically, it is estimated as follows.

  Assuming a virtual plane including a bonding wire bent near the bending point F, as the angle TH (FIG. 9) increases due to the flow of the liquid resin, the flow direction of the liquid resin is the in-plane direction of the virtual plane. Approaching. As a result, the bent portion at the bending point F acts more strongly as a portion that resists the flow of the liquid resin. Therefore, when the angle TH is increased to a certain extent, the bent portion at the bending point F is not deformed against the flow of the liquid resin, and as a result, it is estimated that the increase in the angle TH stops at a specific value (for example, about 30 °). The

  According to the manufacturing method of the semiconductor device of the present embodiment, the semiconductor chip CH is formed on a straight line (broken line in FIGS. 10 and 11) connecting the bonding pad PD and, for example, the inner lead portion IL of the lead frame LF. The bonding wire WR is formed so as to pass through the side far from the first vertex A1, that is, the downstream side of the flow of liquid resin (arrow M). Thereby, the variation between the bonding wires WR to the extent that the bonding wires WR are swept away from the upstream side by the liquid resin is suppressed. Therefore, the specific bonding wire WR is prevented from being largely swept away and coming into contact with other bonding wires WR, so that an electrical short circuit SC (FIG. 18) between the bonding wires WR can be prevented.

  Further, according to the present embodiment, the inner peripheral bonding wire WR1 higher than the height of the outer peripheral bonding wire WR2 is formed. The short circuit of the inner peripheral bonding wire WR1 that is easy to be washed away by the liquid resin due to such a high height can be prevented by the present embodiment.

  Further, according to the present embodiment, as shown in FIG. 5, some inner peripheral bonding wires WR1 are provided over a length that can exceed the ground ring GR. In this way, short-circuiting of the inner peripheral bonding wire WR1 that is easy to be washed away by the liquid resin due to the long length can be prevented by the present embodiment.

  Further, according to the present embodiment, as shown in FIG. 5, some of the inner peripheral bonding wires WR1 are provided over a length that can exceed the bus bar BB. In this way, short-circuiting of the inner peripheral bonding wire WR1 that is easy to be washed away by the liquid resin due to the long length can be prevented by the present embodiment.

  According to the present embodiment, the lead frame LF has the outer lead portion OL. Thereby, a package having an external electrode protruding from the resin portion MR, such as QFP, can be formed.

Next, a modification of the present embodiment will be described.
Referring to FIG. 19, the semiconductor device according to the present modification is substantially the same as in the first embodiment. Semiconductor chip CH, a plurality of inner lead portions IL (electrode group), and a plurality of bonding wires WR (wire group) And a resin portion MR (not shown in FIG. 19). Semiconductor chip CH has, for example, a rectangular main surface such as a rectangular shape, and a plurality of bonding pads PD (pad group) provided on the main surface. The bonding wire WR connects the bonding pad PD and the inner lead part IL. Resin portion MR seals bonding wire WR.

  The plurality of bonding pads PD have at least one specific pad PDf (first pad) and a standard pad PDs (third pad). The specific pad PDf is included in the plurality of bonding pads PD that are arranged along the second side L2 on the main surface of the semiconductor chip CH, and is close to the first vertex A1, that is, the second It is arrange | positioned in the position far from the vertex A2. The standard pads PDs are those other than the specific pad PDf among the plurality of bonding pads PD.

  The plurality of inner lead portions IL have at least one specific lead portion ILf (first electrode) and a standard lead portion ILs (second electrode). The specific lead portion ILf is included in the plurality of inner lead portions IL arranged along the second side L2, and is close to the first vertex A1, that is, far from the second vertex A2. , Have been arranged. The standard lead portion ILs is a portion other than the specific lead portion ILf among the plurality of inner lead portions IL.

  The plurality of bonding wires WR includes at least one specific wire WRf (first wire) and a standard wire WRs (second wire). The specific wire WRf is included in a plurality of bonding wires WR that intersect the second side L2 in a plan view (field of view in FIG. 19) and is close to the first vertex A1, that is, the second vertex. It is arranged at a position far from A2. The standard wire WRs is a wire other than the specific wire WRf among the plurality of bonding wires WR.

Next, a method for manufacturing the semiconductor device according to this modification will be described.
First, a wire bonding process is performed. That is, the bonding wires WR are formed between the plurality of bonding pads PD and the plurality of inner lead portions IL. That is, a step of forming the standard wire WRs between the standard pad PDs and the standard lead portion ILs and a step of forming the specific wire WRf between the specific pad PDf and the specific lead portion ILf are performed.

  Of the bonding wires WR, the specific wire WRf is bonded in the same manner as the bonding wire WR (FIG. 10) of the present embodiment described above. That is, in plan view, the first wire passes through the side far from the first vertex A1 (that is, the side closer to the second vertex A2) with respect to the straight line connecting the specific pad PDf and the specific lead portion ILf. Is formed.

  On the other hand, of the bonding wires WR, the standard wires WRs are bonded in the same manner as the bonding wires WZ (FIG. 15) of the comparative example described above. That is, the standard wire WRs does not have an inclination with respect to the main surface of the semiconductor chip CH before the liquid resin is poured, and thus the standard wire WRs is linear in a plan view as shown in FIG. Have a different shape.

  Next, as in the above-described embodiment, the liquid resin is poured and cured, whereby the semiconductor device of the present modification is obtained.

Next, the effect of this modification is demonstrated.
As shown in the white arrow M of FIG. 19 bent at a right angle, the liquid resin immediately after changing the direction from the direction along the first side L1 to the direction along the second side L2 The momentum increases. According to this modification, the specific wire WRf having the same shape as that of the present embodiment described above is formed at the position exposed to the liquid resin with increased momentum. Therefore, the contact between the bonding wires WR caused by the liquid resin having increased momentum can be prevented in the same manner as in the above-described embodiment.

  On the other hand, standard wires WRs, that is, wires having a more general shape, can be used at positions exposed to a relatively gentle liquid resin.

(Embodiment 2)
20 to 22, the semiconductor device of the present embodiment is a BGA (Ball Grid Array) type plastic package BP. The package BP has an electrode EL, a circuit board CB, and a solder ball BL instead of the lead frame LF (Embodiment 1). Moreover, it has resin part MRb instead of resin part MR (Embodiment 1).

  The electrode EL is connected to the semiconductor chip CH by a bonding wire WR. Each of the semiconductor chip CH and the electrode EL is supported by the circuit board CB. Resin portion MRb seals bonding wire WR and semiconductor chip CH.

  Referring to FIG. 23, also in the method of manufacturing the semiconductor device of the present embodiment, the formation of bonding wire WR and the pouring of liquid resin (arrow M) are performed as in the first embodiment.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

Also in the present embodiment, the same effect as in the first embodiment can be obtained.
Further, according to the present embodiment, the package BP includes the circuit board CB that supports each of the semiconductor chip CH and the electrode EL. Thereby, a BGA package having the circuit board CB can be formed.

Next, a modification of the present embodiment will be described.
Referring to FIG. 24, the plurality of bonding pads PD includes at least one specific pad PDf (first pad) and standard pad PDs (third pad) as in the modification of the first embodiment (FIG. 19). Pad).

  The plurality of electrodes EL (electrode group) includes at least one specific electrode ELf (first electrode) and a standard electrode ELs (second electrode). The specific electrode ELf is included in the plurality of electrodes EL arranged along the second side L2, and is arranged at a position close to the first vertex A1, that is, a position far from the second vertex A2. Has been. The standard electrode ELs is other than the specific electrode ELf among the plurality of electrodes EL.

  The plurality of bonding wires WR includes at least one specific wire WRf (first wire) and a standard wire WRs (second wire). The specific wire WRf is included in a plurality of bonding wires WR that intersect the second side L2 in a plan view (field of view in FIG. 19) and is close to the first vertex A1, that is, the second vertex. It is arranged at a position far from A2. The standard wire WRs is a wire other than the specific wire WRf among the plurality of bonding wires WR.

  According to this modification, when the semiconductor device is a BGA type plastic package BP, the same effect as that of the modification of the first embodiment can be obtained.

(Embodiment 3)
In the present embodiment, another manufacturing method for manufacturing a semiconductor device (FIGS. 20 to 22) substantially similar to the second embodiment will be described.

  Referring to FIGS. 25 and 26, first, a substrate CBA is prepared. The substrate CBA is obtained by integrating a plurality of circuit substrates CB (FIGS. 20 to 22). Therefore, a plurality of semiconductor devices each having the circuit board CB can be obtained by cutting the substrate CBA after resin sealing described later. A plurality of electrodes EL are provided on each of the portions of the substrate CBA to be the circuit substrate CB. A positioning hole 15 and a taper pin hole 16 are provided on the upstream side of the substrate CBA when a liquid resin to be described later is poured, and a groove 31 serving as an air vent is provided on the downstream side.

  A plurality of semiconductor chips CH are prepared. In the following, for convenience of explanation, of the plurality of semiconductor chips CH, the semiconductor chip CH1 (first semiconductor chip) and the semiconductor chip CH2 (first semiconductor chip CH2) positioned upstream of the semiconductor chip CH1 when the liquid resin is poured. 2 semiconductor chip) will be described in detail.

  The semiconductor chip CH1 has a rectangular main surface, and the main surface has a first side L6a, a second side L7, a third side L6b, and a fourth side L5. The first side L6a and the second side L7 share the vertex A6a. The second side L7 and the third side L6b share the vertex A6b. The third side L6b and the fourth side L5 share the vertex A5b. The fourth side L5 and the first side L6a share the vertex A5a.

  A plurality of bonding pads PD (pad group) are provided on the main surface. The plurality of bonding pads PD have at least one specific pad PDr (first pad) and a standard pad PDs (third pad). The specific pad PDr is included in the plurality of bonding pads PD arranged along the second side L7 on the main surface of the semiconductor chip CH1 and is close to the portion L7a (that is, far from the vertex A6b). Part). The standard pads PDs are those other than the specific pad PDr among the plurality of bonding pads PD.

  Although the semiconductor chip CH2 has the same configuration as the semiconductor chip CH1, for convenience of explanation, among the sides of the main surface of the semiconductor chip CH2, the side corresponding to the first side L6a of the semiconductor chip CH1 is the fifth side. Called L9.

  Next, a plurality of semiconductor chips CH are attached on the substrate CBA via an adhesive layer. This attachment is performed so that the semiconductor chips CH1 and CH2 are aligned, and the first side L6a of the semiconductor chip CH1 and the fifth side L9 of the semiconductor chip CH2 are aligned.

  Next, a bonding wire WR is formed between the bonding pad PD and the electrode EL. Thereby, a specific wire WRr belonging to the bonding wire WR is formed between the specific pad PDr of the semiconductor chip CH1 and the specific electrode ELr. Also, standard wires WRs belonging to the bonding wires WR are formed between the standard pads PDs of the semiconductor chip CH1 and the standard electrodes ELs.

  The specific wire WRr intersects the second side L7 in plan view, and particularly intersects the portion L7a of the second side L7 that is close to the vertex A6a. The specific wire WRr has a convex shape toward the vertex A6a in plan view. That is, the specific wire WRr passes the side closer to the vertex A6a with respect to the straight line connecting the specific pad PDr and the specific electrode ELr.

  On the other hand, the standard wires WRs have a linear shape in plan view as in the modification of the second embodiment.

  As described above, as a result of giving different shapes to the specific wire WRr and the standard wire WRs, as shown in FIG. 26, the distance SP between the specific wire WRr and the standard wire WRs (straight wire in plan view). Is more widely secured.

  Of the bonding wires WR, the wire that intersects the portion L7b near the vertex A6b of the second side L7 is formed to have a convex shape toward the vertex A6b in plan view, as shown in FIG. .

  Referring to FIGS. 27 and 28, the upper die MMa includes a cull 5, a part of the cull-side runner 6, an overflow cavity 7, a part of the overflow cavity runner 8, a positioning pin receiving portion 17, and a taper pin 18. Is provided. On the other hand, the lower mold MMb is provided with a cull 5, a part of the cull-side runner 6, a part of the overflow cavity runner 8, a recess 19 for placing the substrate CBA, a cavity CM and a positioning pin 20. .

  29 and 30, substrate CBA is placed in recess 19 of lower mold MMb so that semiconductor chip CH is placed in cavity CM. That is, the semiconductor chips CH1 and CH2 are simultaneously stored in the cavity CM.

  Next, in a state where the substrate CBA is sandwiched between the lower mold MMb and the upper mold MMa, the liquid resin is poured into the cavity CM from the cull 5 via the cull-side runner 6. Thereby, the resin sealing for the semiconductor chips CH1 and CH2 is performed in a lump.

  In the pouring of the liquid resin, the liquid resin first passes through the position along the fifth side L9 (FIG. 29) of the semiconductor chip CH2, and then the first side as shown by the arrow M (FIG. 30). The position passes along the position along L6a and the vertex A6a in order, and flows to the position along the second side, thereby reaching the portion L7a on the second side.

  Next, the liquid resin is cured to obtain a resin structure in which a plurality of resin portions MR (FIG. 20) are integrated. Next, by cutting the integrated resin structure together with the substrate CB, a semiconductor device (FIGS. 20 to 22) substantially similar to that of the second embodiment is obtained.

Next, the effect of this modification is demonstrated.
As shown in the white arrow M of FIG. 30 bent at a right angle, the liquid resin immediately after the direction is changed around the vertex A6a from the direction along the first side L6a to the direction along the second side L7. The momentum of the flow increases. According to the present embodiment, the distance SP between the bonding wires can be widely ensured at the position exposed to the liquid resin with increased momentum. Therefore, it is possible to prevent contact between the specific wire WRr and the standard wire WRs separated by the wide space SP due to the liquid resin.

  On the other hand, standard wires WRs, that is, wires having a more general shape, can be used at positions exposed to a relatively gentle liquid resin.

  Since the configuration other than the above is substantially the same as the configuration of the second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  In the present specification, the “rectangular shape” refers to a quadrangular shape in which all four corners are right angles, and is therefore a concept including a square shape.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be particularly advantageously applied to a method for manufacturing a semiconductor device having a resin portion for sealing a wire.

  A1 first vertex, A2 second vertex, BB bus bar, BL solder ball, BP, QP package, CB circuit board, CH semiconductor chip, CP connection, CV cavity, DP die pad, EL electrode, F bending point, GR Ground ring, IL inner lead part (electrode), L1 first side, L2 second side, LF lead frame, ML mold, MLa upper mold, MLb lower mold, MR, MRb resin part, OL outer lead Part (electrode), PD bonding pad, PD1 inner periphery bonding pad, PD2 outer periphery bonding pad, SL suspension lead, ST, ST1, ST2 bent portion, WR bonding wire, WR1 inner periphery bonding wire, WR2 outer periphery bonding wire, WZ bonding wire .

Claims (14)

A rectangular main surface having first and second vertices that are diagonal to each other and first and second sides connecting the first and second vertices; and a first on the main surface A method of manufacturing a semiconductor device, comprising: a semiconductor chip having a plurality of pads; an electrode; a wire connecting the first pad and the electrode; and a resin portion for sealing the wire.
Forming the wire between the first pad and the electrode;
Placing the wire in a mold cavity;
Pouring a liquid resin into the cavity from the first vertex toward the second vertex along the first and second sides;
Forming the resin part by curing the liquid resin,
The step of forming the wire is performed by forming the wire so as to pass through a side farther from the first vertex with respect to a straight line connecting the first pad and the electrode in a plan view. A method for manufacturing a semiconductor device.   The semiconductor chip includes a second pad provided on the main surface, and a distance between the second pad and the outer edge of the main surface is smaller than a distance between the first pad and the outer edge. A method for manufacturing a semiconductor device according to claim 1.   The method for manufacturing a semiconductor device according to claim 1, wherein the electrode has a portion protruding from the resin portion.   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes a circuit board that supports each of the semiconductor chip and the electrode. A rectangular main surface having first and second vertices diagonally to each other and first and second sides connecting the first and second vertices, and a pad on the main surface; A semiconductor device manufacturing method including a semiconductor chip having a group, an electrode group, a wire group connecting the pad group and the electrode group, and a resin portion sealing the wire group,
Forming the wire group between the pad group and the electrode group, the forming the wire group comprising: a first pad belonging to the pad group; and a first electrode belonging to the electrode group. Including a step of forming a first wire belonging to the group of wires,
Placing the group of wires in a cavity of a mold;
Pouring a liquid resin into the cavity from the first vertex toward the second vertex along the first and second sides;
Forming the resin part by curing the liquid resin,
The step of forming the first wire includes the first wire passing through a side far from the first vertex with respect to a straight line connecting the first pad and the first electrode in plan view. A method of manufacturing a semiconductor device, which is performed by forming a wire.   The semiconductor chip includes a second pad provided on the main surface, and an interval between the second pad and an outer edge of the main surface is larger than an interval between the first pad and the outer edge. The manufacturing method of the semiconductor device according to claim 5, which is small.   Each of the said electrode group is a manufacturing method of the semiconductor device of Claim 5 or 6 which has the part protruded from the said resin part.   The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device includes a circuit board that supports each of the semiconductor chip and the electrode group. The step of forming the wire group includes a step of forming a second wire belonging to the wire group between a third pad belonging to the pad group and a second electrode belonging to the electrode group,
The step of forming the second wire is performed by forming the second wire along a straight line connecting the third pad and the second electrode in plan view. The manufacturing method of the semiconductor device in any one of 5-8. A first semiconductor chip having a rectangular main surface having first and second sides sharing a vertex and having a pad group on the main surface, an electrode group, the pad group, and the electrode A method for manufacturing a semiconductor device, comprising: a wire group that connects a group; and a resin portion that seals the wire group,
Forming the wire group between the pad group and the electrode group, the forming the wire group comprising: a first pad belonging to the pad group; and a first electrode belonging to the electrode group. Forming a first wire that belongs to the wire group and intersects the second side in plan view, and
Placing the group of wires in a cavity of a mold;
A step of pouring a liquid resin into the cavity, the step of pouring the liquid resin, the liquid resin passing through a position along the first side and a position around the apex in order, Flow to a position along the second side, and
Comprising the step of forming the resin portion by curing the liquid resin;
The step of forming the first wire includes a side close to the apex with respect to a straight line that intersects the second side and connects the first pad and the first electrode in a plan view. A method for manufacturing a semiconductor device, comprising: forming the first wire so as to pass therethrough.   The semiconductor chip includes a second pad provided on the main surface, and an interval between the second pad and an outer edge of the main surface is larger than an interval between the first pad and the outer edge. The method for manufacturing a semiconductor device according to claim 10, wherein the method is small.   The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device includes a circuit substrate that supports each of the semiconductor chip and the electrode group. The step of forming the wire group includes a step of forming a second wire belonging to the wire group between a third pad belonging to the pad group and a second electrode belonging to the electrode group,
The step of forming the second wire is performed by forming the second wire along a straight line connecting the third pad and the second electrode in plan view. The manufacturing method of the semiconductor device in any one of 10-12. The cavity is configured so that the first semiconductor chip and the second semiconductor chip can be accommodated simultaneously,
The step of pouring the liquid resin is performed such that the liquid resin flows to a position along the first side via a position along the third side of the second semiconductor chip. The manufacturing method of the semiconductor device in any one of 10-13.

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