JP2011071431A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To suppress degradation of narrow channel characteristics.
An element isolation region STI is provided in a trench 104 formed in a semiconductor substrate 100, and has a base insulating film 105 formed on a side wall of the trench 104. A gate insulating film 112 is formed on the element formation region 100 a, and the gate insulating film 112 has a high dielectric constant film 110. The first portion 110a of the high dielectric constant film 110 is formed on the upper surface in the element formation region 100a, and the second portion 110b of the high dielectric constant film 110 is underlying insulating on the upper side surface 104a in the element formation region. It is formed through the film 105. A first cap film 106 containing a metal that changes the threshold voltage of the MIS transistor is provided between the second portion 110 b and the base insulating film 105.
[Selection] Figure 6

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a cap film containing a metal that changes a threshold voltage of a MIS (Metal Insulator Semiconductor) transistor and a manufacturing method thereof.

  With the reduction of semiconductor devices in the design rules, the degree of circuit integration has dramatically improved, and more than 100 million field effect transistors (FETs) can be mounted on one chip. Yes. In order to realize a high-performance transistor, not only reduction of the gate length but also reduction of the gate insulating film is required.

  Conventionally, a silicon oxide film or a silicon oxynitride film is used as the gate insulating film. However, when the EOT (Equivalent Oxide Thickness: equivalent oxide thickness) is reduced to 2 nm or less, a problem arises in that the power consumption of the circuit increases because the gate leakage current increases. In order to reduce the thickness of the EOT while reducing the gate leakage current, there is an interest in a high dielectric constant film. Further, a transistor having a high dielectric constant film and a metal gate electrode (a metal gate electrode is not a silicon electrode but a gate electrode made of a metal material such as titanium nitride or tantalum nitride) for further thinning of the EOT. A lot of research and development has been done.

  One of the problems in realizing a transistor having a high dielectric constant film and a metal gate electrode is control of the threshold voltage of the transistor. In the conventional silicon electrode which is a gate electrode, the work function of the silicon electrode is adjusted by implanting impurity ions, thereby realizing a threshold voltage suitable for each of the N-type FET and the P-type FET. That is, for an N-type FET, the work function of the silicon electrode is reduced by injecting an N-type impurity such as arsenic or phosphorus into the silicon electrode. For a P-type FET, boron or the like is used for the silicon electrode. The work function of the silicon electrode is increased by implanting P-type impurities. However, the metal gate electrode cannot control the work function by implanting impurity ions. Therefore, when a metal gate electrode is used as the gate electrode, control of the threshold voltage of the transistor is a big problem. In this specification, the threshold voltage is described as an absolute value in order to uniformly express the change in the threshold voltage in the N-type FET and the P-type FET. As a result, regardless of the N-type FET and the P-type FET, the case where the threshold voltage changes in a direction approaching 0 V is described as “the threshold voltage decreases (decreases) or the threshold voltage decreases”. Is described as "the threshold voltage increases or the threshold voltage increases".

  Non-Patent Document 1 discloses a method for controlling a threshold voltage in a transistor having a high dielectric constant film and a metal gate electrode. In the transistor disclosed in Non-Patent Document 1, an oxide film and a high dielectric constant film are sequentially formed on an element formation region, and this transistor has an electric dipole at the interface between the oxide film and the high dielectric constant film. A metal oxide film (cap film) to be generated is provided.

  FIG. 8 is a plan view of a conventional semiconductor device having a cap film. 9A is a cross-sectional view taken along line IXA-IXA shown in FIG. 8, and FIG. 9B is a cross-sectional view taken along line IXB-IXB shown in FIG. 8 and 9A, “NFET” indicates a region where an N-type MIS transistor is formed, and “STI” indicates an element isolation region. In FIG. 8, “S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively, and “W” and “L” indicate a gate width and a gate length, respectively. Yes.

  As shown in FIGS. 8 to 9B, in the conventional semiconductor device, a trench 701 is formed in a silicon substrate 700. An element isolation insulating film 703 is formed in the trench 701 via a base insulating film (for example, a silicon oxide film) 702, and an element isolation region STI (Shallow Trench Isolation) is formed by the base insulating film 702 and the element isolation insulating film 703. Is configured. A portion of the silicon substrate 700 surrounded by the element isolation region STI is an element formation region 700a, and a gate insulating film 707 and a gate electrode 710 are sequentially provided on the element formation region 700a. In the gate insulating film 707, a silicon oxide film 704, a hafnium oxide film 705, and a cap film 706 are sequentially provided on the element formation region 700a. In the gate electrode 710, a TiN film 708 and a polysilicon film 709 are formed in the gate insulating film 707. They are provided in order. A sidewall 712 is provided on the side surface of the gate electrode 710. In the element formation region 700a, an extension region 711 is formed below the side of the gate electrode 710, and a source / drain region 713 is formed below the side of the sidewall 712.

  When manufacturing such a semiconductor device, heat treatment is performed after the cap film 706 is formed. Then, the metal in the cap film 706 (for example, lanthanum when manufacturing an N-type FET, or aluminum when manufacturing a P-type FET) diffuses to the interface between the hafnium oxide film 705 and the silicon oxide film 704. As a result, an electric dipole is generated at this interface, so that the threshold voltage of the transistor can be reduced. In Non-Patent Document 1, if a lanthanum oxide film is used as a cap film, the threshold voltage of the N-type FET can be lowered by about 400 mV, and if an aluminum oxide film is used as the cap film, the threshold voltage of the P-type FET is lowered by about 300 mV. It can be done.

S. Kubicek et al., Symp. VLSI Technology, p.130, 2008.

  However, it has been found that when the threshold voltage of the MIS transistor is reduced by the method disclosed in Non-Patent Document 1, the narrow channel characteristics are deteriorated. FIG. 10 is a graph schematically showing the evaluation results of the narrow channel characteristics of a conventional N-type MIS transistor.

When the cap film was not formed, as shown by the line 91 in FIG. 10, there was almost no variation in the threshold voltage with respect to the gate width. On the other hand, when the cap film is formed, as shown by the line 92 in FIG. 10, when the gate width is wide, the threshold voltage hardly fluctuates with respect to the gate width, but when the gate width is narrow, the gate width is small. The threshold voltage increased as it narrowed. Specifically, when the gate width is wide (when the gate width is 10 μm, for example), if a lanthanum oxide film having a film thickness of 1 nm is formed on a hafnium oxide film having a film thickness of 2 nm, the threshold voltage is 500 mV. It could be lowered to some extent (Δ ₁ ≈500 mV). This result is comparable to the experimental data described in Non-Patent Document 1. However, the threshold voltage increased as the gate width narrowed, and the threshold voltage increased as high as 200 mV or more (Δ ₂ ≧ 200 mV) when the gate width narrowed to about 0.1 μm. That is, when the gate width is narrowed, the effect of lowering the threshold voltage by lanthanum is greatly reduced from 500 mV to 300 mV or less (degradation of narrow channel characteristics, dependence of threshold voltage on gate width).

  Although not shown, when the narrow channel characteristics of a conventional P-type MIS transistor are examined, as with the N-type MIS transistor, when the gate width is wide, there is almost no variation in the threshold voltage with respect to the gate width. However, when the gate width was narrow, the threshold voltage increased as the gate width narrowed.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a transistor capable of suppressing deterioration of narrow channel characteristics and a method for manufacturing the same.

  In order to solve the above problem, in the present invention, the cap film is formed not only on the element formation region but also on the base insulating film (the base insulating film is formed on the sidewall of the trench when the element isolation region is formed). .

  There are three possible causes for the degradation of the narrow channel characteristics in a conventional semiconductor device having a cap film. The first factor is that when the cap film is formed, the cap film is thinned due to coverage deterioration in a portion of the element isolation region that is in contact with the element formation region (the edge portion of the transistor). The second factor is that when the high dielectric constant film is formed, the high dielectric constant film becomes thicker due to the loading effect at the edge portion of the transistor. The third factor is that the metal applied to the cap film diffuses into the metal gate electrode during the heat treatment because the stress applied to the cap film is different between the central portion of the transistor and the edge portion of the transistor.

  What is common to all the above three factors is that the effect of the cap film is reduced only at the edge of the transistor. When the gate width is wide, the influence of the edge portion of the transistor on the entire transistor is small. Therefore, if a cap film is formed over the element formation region, the threshold voltage of the transistor can be reduced. However, when the gate width is narrow, the influence of the edge portion of the transistor on the entire transistor is large, and thus the reduction in the effect of the cap film at the edge portion of the transistor cannot be ignored, and therefore the threshold voltage of the transistor increases.

  In the present invention, a cap film containing lanthanum or aluminum is formed on the base insulating film when forming the element isolation region. Thereby, the film thickness of the cap film can be made thicker than before only at the edge portion of the transistor. Accordingly, it is possible to prevent a reduction in the effect of the cap film at the edge portion of the transistor. Therefore, the threshold voltage can be made substantially the same at the edge portion of the transistor and the central portion of the transistor, so that deterioration of the narrow channel characteristic can be suppressed.

  Specifically, a semiconductor device according to the present invention is provided in a trench formed in a semiconductor substrate, and includes an element isolation region surrounding the element formation region, and a gate provided on the element formation region and having a high dielectric constant film. An insulating film and a gate electrode provided on the gate insulating film are provided. The element isolation region has a base insulating film containing oxygen formed on the sidewall of the trench. The high dielectric constant film has a first portion formed on the upper surface in the element formation region and a second portion formed on the upper side surface in the element formation region via a base insulating film. A first cap film containing a metal that changes the threshold voltage of the MIS transistor is provided between the second portion of the high dielectric constant film and the base insulating film.

  Thus, in the semiconductor device according to the present invention, the first cap film is provided at the edge portion of the transistor. Therefore, the effect of the cap film at the edge portion of the transistor can be improved.

  In a preferred embodiment to be described later, the element isolation region further includes an element isolation insulating film formed in the trench via the base insulating film, and the first region is between the base insulating film and the element isolation insulating film. The cap film is provided.

  In a preferred embodiment described later, the gate electrode is formed on the upper side surface in the element formation region via the second portion of the high dielectric constant film.

  In the semiconductor device according to the present invention, the gate insulating film includes an oxygen-containing film formed on the element formation region, a first portion in the high dielectric constant film formed on the oxygen-containing film, and a high dielectric constant film. It is preferable to have a second cap film formed on the first portion and containing a metal. Thereby, the threshold voltage of the transistor can be set to a desired value.

  In a preferred embodiment described later, the second cap film is also formed on the second portion of the high dielectric constant film. In addition, the film thickness of the second cap film formed on the second portion of the high dielectric constant film is the same as that of the second cap film formed on the first portion of the high dielectric constant film. Thinner than film thickness.

  In a preferred embodiment described later, the oxygen-containing film is a silicon oxide film or a silicon oxynitride film, and the base insulating film is a silicon oxide film or a silicon oxynitride film.

  In a preferred embodiment described later, the metal impurity concentration in the second portion of the high dielectric constant film is equal to or higher than the metal impurity concentration in the first portion of the high dielectric constant film.

  In a preferred embodiment described later, the MIS transistor is an N-channel MIS transistor, and the metal is at least one selected from lanthanum, dysprosium, scandium, erbium, magnesium, and strontium.

  In a preferred embodiment described later, the MIS transistor is a P-channel MIS transistor, and the metal is aluminum.

  In a preferred embodiment described below, the high dielectric constant film is any of a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxide film, a zirconium oxide film, or a hafnium zirconium oxide film.

  In a preferred embodiment described later, the gate electrode is a single-layer film made of any one of a titanium nitride film, a tantalum nitride film, a tantalum carbide film, and a tantalum nitride carbide film, or a laminated film made of two or more.

  In the semiconductor device of the present invention, a recess is formed on the upper surface of the edge portion adjacent to the element formation region in the element isolation region, and the second portion of the high dielectric constant film is provided on the inner surface of the recess. As described above, since the concave portion is formed on the upper surface of the edge portion, the first cap film can be provided on the edge portion of the transistor.

  In a preferred embodiment described later, the base insulating film contains a metal.

  The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a trench in a semiconductor substrate so as to surround an element formation region, and then providing a base insulating film containing oxygen on the sidewall of the trench; (B) providing a cap film containing a metal that changes the threshold voltage of the MIS transistor, and after the step (b), an element isolation insulating film is provided in the trench via the base insulating film, A step (c) of forming an element isolation region having an element isolation insulating film, a step (d) of providing a gate insulating film having a high dielectric constant film on the element formation region after the step (c), and gate insulation And (e) providing a gate electrode on the film. In the step (d), a high dielectric constant film is formed on the upper side surface in the element formation region via a base insulating film and a cap film.

  In a preferred embodiment described later, a step (f) of diffusing metal from the cap film into the base insulating film is provided after the step (b).

  In the present invention, it is possible to suppress degradation of narrow channel characteristics.

It is a top view of the semiconductor device concerning one embodiment of the present invention. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (A) is sectional drawing in the VIA-VIA line | wire shown in FIG. 1, (b) is sectional drawing in the VIB-VIB line | wire shown in FIG. It is a graph which shows typically the evaluation result of a narrow channel characteristic. It is a top view of the conventional semiconductor device which has a cap film | membrane. (A) is sectional drawing in the IXA-IXA line | wire shown in FIG. 8, (b) is sectional drawing in the IXB-IXB line | wire shown in FIG. It is a graph which shows typically another evaluation result of a narrow channel characteristic.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited to embodiment shown below. In addition, the film thickness, material, manufacturing method, and the like described in the following embodiments are merely examples, and are not limited to the items described below. Moreover, in the following embodiment, the same code | symbol may be attached | subjected with respect to substantially the same member, and the description may be abbreviate | omitted.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of the semiconductor device according to the present embodiment. FIG. 2A to FIG. 5B are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of steps. 2A to 4B are cross-sectional views taken along the line VIA-VIA shown in FIG. 1, and FIGS. 5A and 5B are cross-sectional views taken along the line VIB-VIB shown in FIG. 1 to 4B, “NFET” indicates a region where an N-type MIS transistor is formed, and “STI” indicates an element isolation region. That is, in this embodiment, a method for manufacturing a semiconductor device including an N-type MIS transistor and its structure are shown. In FIG. 1, “S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively, and “W” and “L” indicate a gate width and a gate length, respectively. “A” is a portion in contact with the element formation region in the element isolation region STI (referred to as an “edge portion of the N-type FET” in the present embodiment).

  First, in the process shown in FIG. 2A, a silicon oxide film 101 of, eg, a 10 nm-thickness is formed on a semiconductor substrate (hereinafter referred to as “substrate”) 100 made of, eg, silicon by thermal oxidation. Subsequently, a silicon nitride film 102 of, eg, a 70 nm-thickness is formed on the silicon oxide film 101. Subsequently, after forming a resist film (not shown) on the silicon nitride film 102, an opening is formed in a portion of the resist film that becomes the element isolation region STI by using a photolithography technique. As a result, a resist pattern 103 is formed on the silicon nitride film 102 so as to expose the silicon nitride film 102 in a portion serving as the element isolation region STI.

  Next, in the process shown in FIG. 2B, the silicon nitride film 102, the silicon oxide film 101, and the substrate 100 are etched using the resist pattern 103 (see FIG. 2A) as a mask. As a result, a trench 104 having a depth of, for example, 300 nm is formed in the substrate 100. Subsequently, the resist pattern 103 is removed, and then heat treatment is performed in an oxygen gas and hydrogen gas atmosphere. As a result, a base insulating film 105 made of, for example, a silicon oxide film having a thickness of 2 nm is formed on the sidewall and the bottom surface of the trench 104 (step (a)).

  Next, in the step shown in FIG. 2C, the top surface and side surface of the silicon nitride film 102, the side surface of the silicon oxide film 101, and the base insulating film 105 are formed by using, for example, an ALD (Atomic Layer Deposition) method. For example, a first cap film (cap film) 106 made of a lanthanum oxide film having a thickness of 1 nm is formed (step (b)). Subsequently, heat treatment is performed in a nitrogen gas atmosphere at, for example, 800 ° C. for 30 seconds. Thereby, the lanthanum in the first cap film 106 diffuses into the base insulating film 105 (step (f)). Accordingly, lanthanum exists in the base insulating film 105. At this time, it is preferable to perform thermal diffusion so that lanthanum exists in the vicinity of the interface between the base insulating film 105 and the first cap film 106.

  Next, in the process shown in FIG. 3A, for example, silicon having a film thickness of, for example, 500 nm is formed on the entire surface of the substrate 100 so as to bury the trench 104 by using, for example, plasma CVD (Chemical Vapor Deposition) or thermal CVD. An oxide film (not shown) is formed. Thereafter, using, for example, a CMP (Chemical Mechanical Polishing) method, the silicon oxide film is present above the silicon nitride film 102, and the first cap film 106 is present above the silicon nitride film 102. Remove the part that is. As a result, the surface on the substrate 100 is planarized, and the element isolation insulating film 107 made of a silicon oxide film is formed in the trench 104 on the side wall and the bottom surface of the trench 104 via the base insulating film 105 and the first cap film 106. Formed on top. That is, the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104. The element isolation insulating film 107, the first cap film 106, and the base insulating film 105 form an element isolation region STI (step (c)), and a portion of the substrate 100 surrounded by the element isolation region STI is formed as an element. It becomes area | region 100a.

  Next, in the process shown in FIG. 3B, the silicon nitride film 102 on the silicon oxide film 101 and the silicon oxide film 101 in the first cap film 106 are etched by etching using a chemical solution such as phosphoric acid. Remove the existing part. Subsequently, after forming a resist pattern (not shown) that opens a desired region, impurity ions 108 are implanted into the substrate 100 using the resist pattern as a mask. In this embodiment, since an N-type FET is manufactured, a P-type impurity such as boron may be used as the impurity ions 108. In this manner, a P-type well (not shown) is formed and the threshold voltage of the channel region is adjusted. Subsequently, after removing the resist pattern, annealing is performed at 1000 ° C. for 1 minute in a nitrogen atmosphere in order to diffuse and activate impurities (P-type impurities) implanted into the substrate 100.

  Next, in the step shown in FIG. 3C, the silicon oxide film 101 is removed by etching using a chemical solution such as hydrofluoric acid. At this time, the wet etching rate of the silicon oxide film formed in the trench 104 is higher than the wet etching rate of the silicon oxide film 101 formed by the thermal oxidation method. Therefore, a recess 107 a is formed on the upper surface of the element isolation insulating film 107 at the edge portion of the N-type FET. As a result, a portion of the first cap film 106 formed on the upper side wall (upper side surface in the element formation region) 104a of the trench is exposed.

Next, in the steps shown in FIGS. 4A and 5A, an oxygen-containing film 109 made of, for example, a silicon oxide film having a thickness of 1 nm is formed on the element formation region 100a. Subsequently, a high dielectric constant made of, for example, a 2 nm-thickness HfO ₂ film (hafnium oxide film) is formed on the upper surface of the oxygen-containing film 109, the inner surface of the recess 107a, and the upper surface of the element isolation region STI by, for example, ALD. A film 110 is formed. As a result, the first cap film 106 is sandwiched between the portion (second portion) 110 b formed on the upper side surface 104 a in the element formation region of the high dielectric constant film 110 and the base insulating film 105. The base insulating film 105 contains lanthanum. For these reasons, since lanthanum exists at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, an electric dipole is generated at this interface. Therefore, the threshold voltage can be reduced by the first cap film 106 at the edge portion of the N-type FET.

  Subsequently, a second cap film 111 made of a lanthanum oxide film having a film thickness of 1 nm, for example, is formed on the upper surface of the high dielectric constant film 110. Therefore, the second cap film 111 is formed not only on the upper surface of the portion (first portion) 110a formed on the upper surface of the oxygen-containing film 109 in the high dielectric constant film 110 but also on the second dielectric layer 110 of the high dielectric constant film 110. Also formed on the upper surface of the second portion 110b. Note that the film thickness of the portion of the second cap film 111 formed on the second portion 110b of the high dielectric constant film 110 is that of the high dielectric constant film 110 of the second cap film 111 due to coverage deterioration. It is thinner than the thickness of the portion formed on the first portion 110a. Then, a TiN film (titanium nitride film) 113 having a thickness of, for example, 10 nm is formed on the upper surface of the second cap film 111, and a polysilicon film 114 having a thickness of, for example, 80 nm is formed on the upper surface of the TiN film 113. .

  Next, in the steps shown in FIGS. 4B and 5B, after forming a resist mask (not shown) on the upper surface of the polysilicon film 114, dry etching is performed using the resist mask as a mask. At this time, dry etching may be performed so that the gate length L is, for example, 50 nm. By this dry etching, a gate insulating film 112 formed by sequentially stacking the oxygen-containing film 109, the first portion 110a of the high dielectric constant film 110, and the second cap film 111 is formed on the upper surface of the element formation region 100a. (Step (d)), a gate electrode 115 formed by sequentially laminating the TiN film 113 and the polysilicon film 114 is formed on the upper surface of the gate insulating film 112 (Step (e)). As shown in FIG. 4B, the gate insulating film 112 is also formed on the upper side surface 104a in the element formation region, and the gate electrode 115 is formed of the gate insulating film 112 (the first layer in the high dielectric constant film 110). 2 is also formed on the upper side surface 104a in the element formation region via the second portion 110b).

Subsequently, a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100. Then, N-type impurities such as arsenic ions or phosphorus ions are implanted using the resist and the gate electrode 115 as a mask. At this time, the implantation energy is, for example, 2 to 5 keV, and the dose amount is, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . As a result, an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a. Thereafter, the resist is removed.

  Subsequently, after forming a silicon nitride film (not shown) of 80 nm, for example, on the upper surface of the substrate 100, anisotropic etching is performed on the silicon nitride film. As a result, sidewall spacers 117 are formed on the side surfaces of the gate electrode 115.

Subsequently, a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100. Then, N-type impurities such as arsenic ions or phosphorus ions are ion-implanted using the resist, the gate electrode 115 and the sidewall spacer 117 as a mask. At this time, the implantation energy is, for example, 30 keV, and the dose amount is, for example, 1 × 10 ¹⁶ / cm ² . As a result, an N-type source / drain region 118 is formed below the side wall spacer 117 in the element formation region. Thereafter, the resist is removed.

  Then, spike annealing is performed at 1000 ° C. for 0 second. As a result, the N-type impurity implanted into the N-type extension region 116 is diffused and activated, and the junction depth of the N-type extension region 116 becomes about 20 nm. Similarly, the N-type impurity implanted into the N-type source / drain region 118 is diffused and activated, and the junction depth of the N-type source / drain region 118 becomes about 60 nm. In this way, the semiconductor device according to this embodiment is manufactured.

  In this spike annealing process, lanthanum in the second cap film 111 diffuses to the interface between the high dielectric constant film 110 and the oxygen-containing film 109. Thereby, since an electric dipole is generated at the interface, the threshold voltage of the N-type FET can be reduced.

  In addition, in this spike annealing process, lanthanum in the first cap film 106 diffuses into the second portion 110 b of the high dielectric constant film 110. As described above, the lanthanum in the second cap film 111 is only diffused into the first portion 110a of the high dielectric constant film 110, but the second portion 110b of the high dielectric constant film 110 is diffused into the second portion 110b. Not only lanthanum in the cap film 111 but also lanthanum in the first cap film 106 diffuses. Therefore, the lanthanum concentration in the second portion 110b of the high dielectric constant film 110 is equal to or higher than the lanthanum concentration in the first portion 110a of the high dielectric constant film 110.

  Hereinafter, the configuration of the semiconductor device according to the present embodiment will be briefly described with reference to FIGS. 1 and 6A to 7. 6A is a cross-sectional view taken along line VIA-VIA shown in FIG. 1, and FIG. 6B is a cross-sectional view taken along line VIB-VIB shown in FIG. FIG. 7 is a graph schematically showing the evaluation results of the narrow channel characteristics.

  A trench 104 is formed in the substrate 100. A base insulating film 105 and a first cap film 106 are sequentially formed on the sidewall and the bottom surface of the trench 104, and the element is interposed in the trench 104 via the base insulating film 105 and the first cap film 106. An isolation insulating film 107 is formed. The base insulating film 105, the first cap film 106, and the element isolation insulating film 107 constitute an element isolation region STI, and a portion of the substrate 100 surrounded by the element isolation region STI is an element formation region 100a.

  A gate insulating film 112 and a gate electrode 115 are sequentially formed on the element formation region 100a. In the gate insulating film 112, an oxygen-containing film 109, a high dielectric constant film 110, and a second cap film 111 are sequentially formed on the element formation region 100 a, and at the interface between the oxygen-containing film 109 and the high dielectric constant film 110. There is a lantern. In the gate electrode 115, a TiN film 113 and a polysilicon film 114 are sequentially formed on the gate insulating film 112.

  The high dielectric constant film 110 is formed not only on the element formation region 100 a but also on the element isolation region STI. Specifically, in the element formation region via the base insulating film 105 and the first cap film 106. It is also provided on the upper side surface 104a (second portion 110b). Therefore, the first cap film 106 is sandwiched between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110 on the upper side surface 104a in the element formation region. Similarly, the second cap film 111, the TiN film 113, and the polysilicon film 114 are formed not only on the element formation region 100a but also on the element isolation region STI.

  A sidewall spacer 117 is formed on the side surface of the gate electrode 115, and an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a. An N-type source / drain region 118 is formed below the side wall spacer 117.

  As described above, in the present embodiment, the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104, and the base is formed on the upper side surface 104a in the element formation region. It is sandwiched between the insulating film 105 and the second portion 110 b of the high dielectric constant film 110. The base insulating film 105 contains lanthanum, particularly in the vicinity of the interface with the first cap film 106. For these reasons, since an electric dipole is generated at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, the threshold voltage is applied by the first cap film 106 at the edge portion A of the N-type FET. Can be reduced. Therefore, in this embodiment, as shown by the line 61 in FIG. 7, it is possible to suppress a decrease in narrow channel characteristics.

  In the present embodiment, the threshold voltage can be reduced by the first cap film 106 at the edge portion A of the N-type FET. Therefore, even when the thickness of the second cap film 111 is reduced at the edge portion A of the N-type FET when the second cap film 111 is formed (coverage deterioration), it is possible to suppress a decrease in narrow channel characteristics. . Furthermore, even when the high dielectric constant film 110 is formed and the thickness of the high dielectric constant film 110 becomes thicker at the edge portion A of the N-type FET (loading effect), it is possible to suppress a decrease in narrow channel characteristics. In addition, even if lanthanum in the second cap film 111 diffuses into the gate electrode 115 during the heat treatment, it is possible to suppress a decrease in narrow channel characteristics.

  Further, in this embodiment, since lanthanum exists at the interface between the oxygen-containing film 109 and the high dielectric constant film 110, an electric dipole is generated at this interface. Therefore, the threshold voltage of the N-type FET can be reduced.

  In addition, this embodiment may have the structure shown below.

  In the step shown in FIG. 2B, the silicon nitride film 102, the silicon nitride film 102, and the silicon oxide film 101 are positioned so that the etching end faces of the silicon nitride film 102 and the silicon oxide film 101 are about 5 nm from the etching end face of the substrate 100. It is preferable to etch the silicon oxide film 101 and the substrate 100. Thereby, in the process of forming the base insulating film 105 on the side wall and the bottom surface of the trench 104, which is the next process, the corner at the upper end of the side wall of the trench 104 can be rounded off. Thereby, it is possible to avoid the concentration of the electric field at the upper end of the sidewall of the trench 104.

  In the heat treatment in FIG. 2C, depending on the conditions of the heat treatment, the structure of the base insulating film 105, and the structure of the first cap film 106, lanthanum forms the base insulating film 105 until the first cap film 106 is completely removed. May diffuse. In this case, the boundary between the base insulating film 105 and the first cap film 106 does not exist on the upper side surface 104a in the element formation region. In other words, in the manufactured semiconductor device, the first cap film 106 is not formed on the base insulating film 105, and instead, the base insulating film 105 is the second portion of the high dielectric constant film 110. Lanthanum is contained in the vicinity of the interface with 110b. Even in the semiconductor device having such a structure, since lanthanum exists at the interface between the base insulating film 105 and the high dielectric constant film 110, deterioration of narrow channel characteristics can be suppressed. Note that the first cap film 106 may be removed after lanthanum is diffused from the first cap film 106 to the base insulating film 105.

  The heat treatment in FIG. 2C may be omitted. In this case, the lanthanum in the first cap film 106 diffuses into the base insulating film 105 by the heat treatment in FIG. 3B or the heat treatment in FIGS. 4B and 5B. However, if heat treatment is performed in FIG. 2C, the degradation of the narrow channel characteristics can be suppressed even when the first cap film 106 is removed after the heat treatment. Therefore, it is preferable to perform heat treatment in FIG.

  In the heat treatment in FIGS. 4B and 5B, the second cap film 111 is completely removed depending on the conditions of the heat treatment, the configuration of the high dielectric constant film 110, and the configuration of the second cap film 111. Lanthanum may diffuse to the lower part of the high dielectric constant film 110 or the upper part of the oxygen-containing film 109. In this case, in the manufactured semiconductor device, there is no boundary between the high dielectric constant film 110 and the second cap film 111. In other words, in the manufactured semiconductor device, the second cap film 111 is not formed on the high dielectric constant film 110, and instead, the interface between the oxygen-containing film 109 and the high dielectric constant film 110. There is a lantern in the vicinity. Even in a semiconductor device having such a configuration, since lanthanum exists at the interface between the oxygen-containing film 109 and the high dielectric constant film 110, the threshold voltage of the N-type FET can be reduced.

  When it is difficult to diffuse lanthanum to the lower part of the high dielectric constant film 110 in the heat treatment in FIGS. 4B and 5B, the second cap film 111 is replaced with the oxygen-containing film 109 and the high dielectric constant film 110. What is necessary is just to form between.

  The base insulating film 105 is not limited to a silicon oxide film, and may be a silicon oxynitride film, for example. If the base insulating film 105 contains oxygen, the first cap film 106 can be used to suppress degradation of the narrow channel characteristics.

  The thickness of the base insulating film 105 is not limited to 2 nm and may be in the range of about 1 to 10 nm. When the thickness of the base insulating film 105 is in the range of about 0.5 to 15 nm, it is possible to suppress the degradation of narrow channel characteristics.

  The first cap film 106 only needs to contain a metal capable of lowering the threshold voltage of the N-type FET. Examples of such a metal include dysprosium (Dy), scandium (Sc), erbium (Er), magnesium (Mg), and strontium (Sr) in addition to lanthanum. Therefore, the first cap film 106 is not limited to the lanthanum oxide film, and may be a film made of any one of the above metals, or an oxide film of any one of the above metals. It may be a film containing any two or more of the metals, or a film containing an oxide of any two or more of the metals. good.

  The film thickness of the first cap film 106 is not limited to 1 nm. It is preferable to adjust the film thickness of the first cap film 106 in accordance with the amount of decrease in the threshold voltage at the edge portion A of the N-type FET. That is, when it is assumed that the threshold voltage decrease amount at the edge portion A of the N-type FET is small (for example, when the gate width is not so narrow), the thickness of the first cap film 106 is reduced (for example, 0.5 nm), and when the reduction amount of the threshold voltage at the edge portion A of the N-type FET is assumed to be large (for example, when the gate width is narrow), the thickness of the first cap film 106 is increased. A film may be formed (for example, 2 nm).

  If the first cap film 106 is sandwiched between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, the degradation of the narrow channel characteristics can be suppressed. Therefore, the first cap film 106 may be formed only on the upper side surface 104 a in the element formation region with the base insulating film 105 interposed therebetween. The high dielectric constant film 110 may include only the first portion 110a and the second portion 110b.

The high dielectric constant film 110 may be made of a material having a higher dielectric constant than silicon oxide, silicon nitride, and silicon oxynitride. Specifically, a metal oxide, metal oxynitride having a dielectric constant of 8 or more, A silicate or a nitrogen-containing silicate may be used. Therefore, the high dielectric constant film 110 is not limited to the HfO ₂ film, but is an HfSiO film (hafnium silicon oxide film), an HfSiON film (hafnium silicon oxide film), a ZrO ₂ film (zirconium oxide film), or an HfZrO film (hafnium film). Zirconium oxide film) or the like.

  The second cap film 111 is not limited to a lanthanum oxide film, and any film that can be used as the first cap film 106 may be used. Further, the first cap film 106 and the second cap film 111 may be made of the same material or different materials.

  The gate insulating film 112 may not contain lanthanum. Even if the gate insulating film 112 does not contain lanthanum, if the first cap film 106 is formed between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, Degradation of narrow channel characteristics can be suppressed.

  Instead of the TiN film 113 in the gate electrode 115, any one single layer film or two layers of TaN film (tantalum nitride film), TaC film (tantalum carbide film), TaCN (tantalum nitride carbide film), etc. More than one type of laminated film may be used. Further, the gate electrode 115 may not have the polysilicon film 114.

  A P-type pocket region may be formed below the N-type extension region 116 in the element formation region 100a. Further, a silicide layer made of NiSi having a thickness of, for example, 20 nm may be formed on the upper surface of the gate electrode 115 and the upper surface of the N-type source / drain region 118.

  Although the N-type FET has been described above, the conductivity type of the transistor may be P-type. When the semiconductor device according to the present embodiment includes a P-type FET, the conductivity types in the above description are opposite to each other, and the first and second cap films 106 and 111 are aluminum films or aluminum oxide films. is there. In the semiconductor device according to the present embodiment, an N-type FET and a P-type FET may be formed with the element isolation region STI interposed therebetween.

  The present invention is useful, for example, for a transistor having a high dielectric constant film.

100 substrate (semiconductor substrate)
100a Element formation region
101 Silicon oxide film
102 Silicon nitride film
103 resist pattern
104 trench
104a Upper side surface in element formation region
105 Underlying insulating film
106 First cap membrane
107 element isolation insulating film
107a recess
109 Oxygen-containing film
110 High dielectric constant film
110a first part
110b second part
111 Second cap membrane
112 Gate insulation film
113 TiN film
114 Polysilicon film
115 Gate electrode
116 N-type extension region
117 Sidewall spacer
118 N-type source / drain region
STI element isolation region

Claims (17)

A semiconductor device including a MIS transistor formed in an element formation region in a semiconductor substrate,
An element isolation region provided in a trench formed in the semiconductor substrate and surrounding the element formation region;
A gate insulating film provided on the element formation region and having a high dielectric constant film;
A gate electrode provided on the gate insulating film,
The element isolation region has a base insulating film containing oxygen formed on a sidewall of the trench,
The high dielectric constant film has a first portion formed on the upper surface in the element formation region and a second portion formed on the upper side surface in the element formation region via the base insulating film. And
A semiconductor device in which a first cap film containing a metal that changes a threshold voltage of the MIS transistor is provided between a second portion of the high dielectric constant film and the base insulating film. The semiconductor device according to claim 1,
The element isolation region further includes an element isolation insulating film formed in the trench through the base insulating film,
A semiconductor device in which the first cap film is provided between the base insulating film and the element isolation insulating film. The semiconductor device according to claim 1 or 2,
The gate electrode is formed on the upper side surface in the element formation region via the second portion of the high dielectric constant film. The semiconductor device according to any one of claims 1 to 3,
The gate insulating film includes an oxygen-containing film formed on the element formation region, the first portion in the high dielectric constant film formed on the oxygen-containing film, and the first portion in the high dielectric constant film. And a second cap film formed on the first portion and containing the metal. The semiconductor device according to claim 4,
The semiconductor device wherein the second cap film is also formed on the second portion of the high dielectric constant film. The semiconductor device according to claim 5,
The film thickness of the second cap film formed on the second portion in the high dielectric constant film is the second thickness formed on the first portion in the high dielectric constant film. Semiconductor device thinner than the cap film thickness. The semiconductor device according to any one of claims 4 to 6,
The semiconductor device, wherein the oxygen-containing film is a silicon oxide film or a silicon oxynitride film. The semiconductor device according to any one of claims 1 to 7,
A semiconductor device in which an impurity concentration of the metal in the second portion of the high dielectric constant film is equal to or higher than an impurity concentration of the metal in the first portion of the high dielectric constant film. The semiconductor device according to any one of claims 1 to 8,
The MIS transistor is an N-channel MIS transistor,
The semiconductor device, wherein the metal is at least one selected from lanthanum, dysprosium, scandium, erbium, magnesium, and strontium. The semiconductor device according to any one of claims 1 to 8,
The MIS transistor is a P-channel MIS transistor,
The semiconductor device, wherein the metal is aluminum. The semiconductor device according to any one of claims 1 to 10,
The semiconductor device, wherein the high dielectric constant film is any one of a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxide film, a zirconium oxide film, or a hafnium zirconium oxide film. The semiconductor device according to any one of claims 1 to 11,
The gate electrode is a semiconductor device which is a single layer film made of any one of a titanium nitride film, a tantalum nitride film, a tantalum carbide film and a tantalum nitride carbide film or a laminated film made of two or more. The semiconductor device according to any one of claims 1 to 12,
A semiconductor device in which the base insulating film is a silicon oxide film or a silicon oxynitride film. The semiconductor device according to any one of claims 1 to 13,
A recess is formed on the upper surface of the edge portion adjacent to the element formation region in the element isolation region,
The semiconductor device, wherein the second portion of the high dielectric constant film is provided on an inner surface of the recess. The semiconductor device according to any one of claims 1 to 14,
The base insulating film is a semiconductor device containing the metal. A method of manufacturing a semiconductor device including a MIS transistor formed in an element formation region in a semiconductor substrate,
After forming a trench in the semiconductor substrate so as to surround the element formation region, a step (a) of providing a base insulating film containing oxygen on a sidewall of the trench;
Providing a cap film containing a metal for changing a threshold voltage of the MIS transistor on the base insulating film (b);
After the step (b), a step (c) of providing an element isolation insulating film through the base insulating film in the trench and forming an element isolation region having the base insulating film and the element isolation insulating film;
A step (d) of providing a gate insulating film having a high dielectric constant film on the element formation region after the step (c);
Providing a gate electrode on the gate insulating film (e),
In the step (d), a method of manufacturing a semiconductor device, wherein the high dielectric constant film is formed on the upper side surface in the element formation region via the base insulating film and the cap film. In the manufacturing method of the semiconductor device according to claim 16,
A method of manufacturing a semiconductor device, comprising a step (f) of diffusing the metal from the cap film into the base insulating film after the step (b).

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