JP2011071204A - Semiconductor-substrate manufacturing method - Google Patents

Abstract

A method of manufacturing a semiconductor substrate for efficiently manufacturing a semiconductor device using SiC is provided.
First and second silicon carbide substrates are formed such that each of first and second back surfaces B1, B2 faces one direction, and first and second side surfaces S1, S2 face each other. 11 and 12 are arranged. After the arranging step, the first and second silicon carbides are connected so that the first and second back surfaces B1 and B2 are connected to each other and the first and second side surfaces S1 and S2 are filled with each other. A silicon carbide layer 30 is formed on substrates 11 and 12 by molecular beam epitaxy.
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate including a portion made of silicon carbide (SiC) having a single crystal structure.

  In recent years, SiC substrates are being adopted as semiconductor substrates used for manufacturing semiconductor devices. SiC has a larger band gap than Si (silicon) which is more commonly used. Therefore, a semiconductor device using a SiC substrate has advantages such as high breakdown voltage, low on-resistance, and small deterioration in characteristics under a high temperature environment.

  In order to efficiently manufacture a semiconductor device, a substrate size of a certain level or more is required. According to US Pat. No. 7,314,520 (Patent Document 1), a SiC substrate of 76 mm (3 inches) or more can be manufactured.

US Pat. No. 7,314,520

  The size of the SiC substrate is industrially limited to about 100 mm (4 inches). Therefore, there is a problem that a semiconductor device cannot be efficiently manufactured using a large substrate. In particular, in the case of hexagonal SiC, the above-described problem becomes particularly serious when the characteristics of a plane other than the (0001) plane are used. This will be described below.

  A SiC substrate with few defects is usually manufactured by cutting out from a SiC ingot obtained by (0001) plane growth in which stacking faults are unlikely to occur. For this reason, the SiC substrate having a plane orientation other than the (0001) plane is cut out non-parallel to the growth plane. For this reason, it is difficult to ensure a sufficient size of the substrate, or many portions of the ingot cannot be used effectively. For this reason, it is particularly difficult to efficiently manufacture a semiconductor device using a surface other than the (0001) surface of SiC.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor substrate manufacturing method for efficiently manufacturing a semiconductor device using SiC.

The manufacturing method of the semiconductor substrate of this invention has the following processes.
A first silicon carbide substrate having a first crystal surface and a first back surface facing each other and a first side surface connecting the first surface and the first back surface and having a single crystal structure, and a first silicon carbide substrate facing each other And a second silicon carbide substrate having a single crystal structure and a second side surface connecting the second surface and the second back surface and a second side surface connecting the second surface and the second back surface. The first and second silicon carbide substrates are arranged such that each of the first and second back surfaces faces one direction and the first and second side surfaces face each other. After this arranging step, the silicon carbide layer is formed on the first and second silicon carbide substrates so that the first and second back surfaces are connected to each other and the first and second side surfaces are filled with each other. Are formed by molecular beam epitaxy (MBE).

  According to this manufacturing method, the first and second silicon carbide substrates are integrated as one semiconductor substrate via the silicon carbide layer. This semiconductor substrate includes both the first and second surfaces of each of the first and second silicon carbide substrates as the substrate surface on which the semiconductor device is formed. That is, this semiconductor substrate has a larger substrate surface as compared with the case where either one of the first and second silicon carbide substrates is used alone. Therefore, by using this semiconductor substrate, a semiconductor device using silicon carbide can be efficiently manufactured.

  Since the silicon carbide layer formed on the first and second silicon carbide substrates is made of silicon carbide in the same manner as the first and second silicon carbide substrates, the first and second silicon carbide substrates and the silicon carbide layer are formed. Various physical properties are close to each other. Therefore, warpage and cracking of the semiconductor substrate due to the difference in various physical properties can be suppressed.

  In addition, since the space where the first and second side surfaces of the silicon carbide layer are opposed to each other is filled, foreign matter is prevented from accumulating in this space.

  Further, since the MBE method is used to form the silicon carbide layer, the silicon carbide layer can be more reliably formed in the space, and the silicon carbide layer and the first and second silicon carbide substrates can be bonded. Strength can be increased.

  Preferably, the silicon carbide layer has a single crystal structure. Thereby, various physical properties of the silicon carbide layer can be brought close to various physical properties of the first and second silicon carbide substrates having the same single crystal structure.

  Preferably, the step of forming the silicon carbide layer includes the steps of heating the first and second silicon carbide substrates, and the first gas containing Si on the heated first and second silicon carbide substrates. And introducing a second gas containing C.

  Preferably, the first gas includes at least one of silane, disilane, dichlorosilane, and trichlorosilane.

  Preferably, the second gas includes at least one of methane, propane, and acetylene.

  Preferably, the step of heating the first and second silicon carbide substrates is performed by heating the first and second silicon carbide substrates to a temperature of 750 ° C. or higher and 1200 ° C. or lower. Thereby, the adhesive strength between the silicon carbide layer and the first and second silicon carbide substrates can be further increased, and damage to the crystallinity of the first and second silicon carbide substrates can be suppressed.

Preferably, the step of introducing the first and second gases is performed at a pressure of 1 × 10 ⁻² Pa or less. Thereby, the adhesive strength between the silicon carbide layer and the first and second silicon carbide substrates can be further increased.

  Preferably, the impurity concentration of each of the first and second silicon carbide substrates is different from the impurity concentration of the silicon carbide layer. Thereby, a semiconductor substrate having a two-layer structure with different impurity concentrations can be obtained.

  Preferably, the impurity concentration of the silicon carbide layer is made higher than the impurity concentration of each of the first and second silicon carbide substrates. Thereby, the resistivity of the silicon carbide layer can be reduced as compared with the resistivity of each of the first and second silicon carbide substrates.

  Preferably, the step of forming the silicon carbide layer introduces at least one of a third gas containing nitrogen and a fourth gas containing phosphine onto the heated first and second silicon carbide substrates. The process of carrying out is included. As a result, the silicon carbide layer can contain at least one of N and P as an impurity.

  Preferably, the step of arranging the first and second silicon carbide substrates is performed such that the distance between the first and second side surfaces facing each other is 200 μm or less. Thereby, the said space can be more reliably filled with a silicon carbide layer.

  Preferably, the off angle of the first surface with respect to the {0001} plane of the first silicon carbide substrate is not less than 50 ° and not more than 65 °. The off angle of the second surface with respect to the {0001} plane of the second silicon carbide substrate is not less than 50 ° and not more than 65 °. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  Preferably, the angle formed by the off orientation of the first surface and the <1-100> direction of the first silicon carbide substrate is 5 ° or less. The angle formed between the off orientation of the second surface and the <1-100> direction of the second silicon carbide substrate is 5 ° or less. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  Preferably, the off angle of the first surface with respect to the {03-38} plane in the <1-100> direction of the first silicon carbide substrate is −3 ° to 5 °. The off angle of the second surface relative to the {03-38} plane in the <1-100> direction of the second silicon carbide substrate is −3 ° to 5 °. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  Preferably, the angle formed by the off orientation of the first surface and the <11-20> direction of the first silicon carbide substrate is 5 ° or less. The angle formed between the off orientation of the second surface and the <11-20> direction of the second silicon carbide substrate is 5 ° or less. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  As is apparent from the above description, according to the method for manufacturing a semiconductor substrate of the present invention, a method for manufacturing a semiconductor substrate for efficiently manufacturing a semiconductor device using silicon carbide can be provided.

It is a top view which shows roughly the structure of the semiconductor substrate in Embodiment 1 of this invention. It is a schematic sectional drawing in alignment with line II-II of FIG. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the semiconductor substrate in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor substrate in Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is a schematic flowchart of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows roughly the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the 4th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1 and 2, semiconductor substrate 80 of the present embodiment includes a plurality of SiC substrates 11 to 19 having a single crystal structure, and SiC layer 30 (silicon carbide layer) made of silicon carbide.

  SiC substrate 11 (first silicon carbide substrate) includes a front surface F1 (first surface) and a back surface B1 (first back surface) facing each other, and a side surface S1 (first side surface) connecting the front surface F1 and back surface B1. ). Further, SiC substrate 12 (second silicon carbide substrate) includes surface F2 (second surface) and back surface B2 (second back surface) facing each other, and side surface S2 (second surface) connecting the surface F2 and back surface B2. Side). Each of SiC substrates 13 to 19 has a similar front surface, back surface, and side surface.

  The SiC substrates 11 to 19 are arranged in a matrix on a plane. Thereby, for example, SiC substrates 11 and 12 are arranged such that each of back surfaces B1 and B2 faces one direction (downward direction in FIG. 2), and side surfaces S1 and S2 face each other.

  SiC layer 30 is formed so that the back surfaces of SiC substrates 11 to 19 arranged as described above are connected to each other, and the side surfaces are filled with the opposing spaces. More specifically, SiC layer 30 is formed on SiC substrates 11 and 12 such that, for example, back surfaces B1 and B2 are connected to each other and side surfaces S1 and S2 are opposed to each other. SiC layer 30 may have voids therein.

  The SiC substrates 11 to 19 are fixed to each other by the SiC layer 30 described above. Each of SiC substrates 11 to 19 has a surface exposed on the same plane. For example, each of SiC substrates 11 and 12 has surfaces F1 and F2 (FIG. 2). Thereby, semiconductor substrate 80 has a larger surface than each of SiC substrates 11-19. Therefore, when the semiconductor substrate 80 is used, a semiconductor device using SiC can be manufactured more efficiently than when each of the SiC substrates 11 to 19 is used alone.

  Preferably, surface F1 and surface F2 are connected by surface FM of SiC layer 30. More preferably, surface FM is coplanar with each of surfaces F1 and F2.

  A protruding shape or a depressed shape may be formed at a position (position C in FIG. 2) facing the surface FM in the semiconductor substrate 80.

  Also preferably, the crystal structures of the SiC substrates 11 and 12 are hexagonal, more preferably 4H—SiC or 6H—SiC. Preferably, SiC layer 30 has a single crystal structure.

  Preferably, the off angle of surface F1 with respect to the {0001} plane of SiC substrate 11 is not less than 50 ° and not more than 65 °, and the off angle of surface F2 with respect to the {0001} plane of SiC substrate 12 is not less than 50 ° and not more than 65 °. It is. More preferably, the angle formed by the off orientation of surface F1 and the <1-100> direction of SiC substrate 11 is 5 ° or less, and the off orientation of surface F2 and the <1-100> direction of SiC substrate 12 The formed angle is 5 ° or less. More preferably, the off angle of the surface F1 with respect to the {03-38} plane in the <1-100> direction of the SiC substrate 11 is −3 ° to 5 °, and the {1-100> direction of the SiC substrate 12 is { The off-angle of the surface F2 with respect to the 03-38} plane is −3 ° to 5 °.

  In the above description, the “off angle of the surface F1 with respect to the {03-38} plane in the <1-100> direction” means the normal line of the surface F1 to the projecting plane extending in the <1-100> direction and the <0001> direction. Is an angle formed by the normal projection of the {03-38} plane, and the sign thereof is positive when the orthographic projection approaches parallel to the <1-100> direction. Is negative when approaching parallel to the <0001> direction. The same applies to the “off angle of the surface F2 with respect to the {03-38} plane in the <1-100> direction”.

  Preferably, the off angle of surface F1 with respect to the {0001} plane of SiC substrate 11 is not less than 50 ° and not more than 65 °, and the off angle of surface F2 with respect to the {0001} plane of SiC substrate 12 is not less than 50 ° and not more than 65 °. And the angle between the off orientation of surface F1 and the <11-20> direction of SiC substrate 11 is 5 ° or less, and the off orientation of surface F2 and the <11-20> direction of SiC substrate 12 The formed angle is 5 ° or less.

  Next, a method for manufacturing the semiconductor substrate 80 will be described. In the following description, only the SiC substrates 11 and 12 among the SiC substrates 11 to 19 may be referred to in order to simplify the description, but the SiC substrates 13 to 19 are also handled in the same manner as the SiC substrates 11 and 12.

  Referring to FIG. 3, first, SiC substrate 11 and SiC substrate 12 are prepared. Specifically, for example, SiC substrates 11 and 12 are prepared by cutting a SiC ingot grown on the (0001) plane in the hexagonal system along the (03-38) plane. Preferably, the back surfaces B1 and B2 are polished surfaces, and more preferably the roughness is 100 μm or less as Ra.

  Next, in a processing chamber (not shown) for the MBE method, each of the back surfaces B1 and B2 is exposed in one direction (upward direction in FIG. 3) on the heating body 81, and the side surfaces S1 and S2 are mutually connected. SiC substrates 11 and 12 are arranged so as to face each other. That is, SiC substrates 11 and 12 are arranged so as to be aligned in plan view.

  Preferably, the distance at which side surfaces S1 and S2 face each other (the distance between side surfaces S1 and S2 in FIG. 3) is 200 μm or less. Specifically, for example, substrates having the same rectangular shape may be arranged in a matrix with an interval of 200 μm or less.

  In order to install SiC substrates 11 and 12 at equal intervals, for example, a countersink having a size corresponding to SiC substrates 11 and 12 may be formed on heating body 81. By placing the SiC substrates 11 and 12 in the countersink, the SiC substrates 11 and 12 can be installed at equal intervals.

  Preferably, the arrangement is performed such that each of back surfaces B1 and B2 is located on the same plane, or each of front surfaces F1 and F2 is located on the same plane.

Next, the processing chamber is evacuated, so that the pressure in the processing chamber is, for example, 10 ⁻³ Pa.

  Next, by heating by heating body 81, SiC substrates 11 and 12 are heated to a predetermined temperature. Preferably, this temperature is 750 ° C. or higher and 1200 ° C. or lower. More preferably, this temperature is 950 ° C. or higher and 1150 ° C. or lower.

Subsequently, a first gas containing Si and a second gas containing C are introduced as raw material gases in the MBE method onto the SiC substrates 11 and 12 from one direction (upward direction in FIG. 3). . Preferably, the first gas includes at least one of silane, disilane, dichlorosilane, and trichlorosilane. Preferably, the second gas includes at least one of methane, propane, and acetylene. The introduction of the raw material gas is preferably performed so that the pressure in the processing chamber is 1 × 10 ⁻² Pa or less, more preferably 1 × 10 ⁻³ Pa or less.

  Further, as the source gas, a third gas containing N may be introduced as needed together with the first and second gases. Specifically, a third gas containing nitrogen gas is introduced. Also good.

  Further, as the source gas, together with the first and second gases, a fourth gas containing P may be introduced as needed. Specifically, a fourth gas containing phosphine may be introduced. Good.

  Referring to FIG. 4, SiC layer 30 is formed on SiC substrates 11 and 12 by introducing the above-described source gas. Thus, the semiconductor substrate 80 is manufactured.

  If necessary, the polishing of the surface of the semiconductor substrate 80 (the upper surface in FIG. 2) may be performed, for example, by chemical mechanical polishing (CMP). Thereby, each of the surface F1, F2, and FM can be reliably located on the same plane.

  According to the present embodiment, as shown in FIG. 2, SiC substrates 11 and 12 are integrated as one semiconductor substrate 80 via SiC layer 30. Semiconductor substrate 80 includes both surfaces F1 and F2 of each of the SiC substrates as a substrate surface on which a semiconductor device such as a transistor is formed. That is, semiconductor substrate 80 has a larger substrate surface as compared to the case where either SiC substrate 11 or 12 is used alone. Therefore, a semiconductor device using SiC can be efficiently manufactured by using the semiconductor substrate 80.

  SiC layer 30 formed on SiC substrates 11 and 12 is made of silicon carbide, similarly to SiC substrates 11 and 12. Thereby, various physical properties become close between SiC substrates 11 and 12 and SiC layer 30. Therefore, warpage and cracking of the semiconductor substrate 80 due to the difference in various physical properties can be suppressed.

  In addition, since the space where the side surfaces S1 and S2 face each other in the SiC layer 30 is filled, foreign matter is prevented from accumulating in this space. Therefore, it is possible to prevent problems caused by such foreign matters during the manufacturing process of the semiconductor device using the semiconductor substrate 80.

  Moreover, since the MBE method is used to form the SiC layer 30, the SiC layer 30 can be more reliably formed in the space. Moreover, the adhesive strength between SiC layer 30 and each of SiC substrates 11 and 12 can be increased.

  Preferably, SiC layer 30 has a single crystal structure. Thereby, various physical properties of SiC layer 30 can be brought close to various physical properties of SiC substrates 11 and 12 having a single crystal structure. Therefore, warping and cracking of the semiconductor substrate 80 due to the difference in various physical properties can be more reliably suppressed.

  Preferably, the step of heating SiC substrates 11 and 12 is performed by heating SiC substrates 11 and 12 to a temperature of 750 ° C. or higher and 1200 ° C. or lower. Thereby, the adhesive strength between SiC layer 30 and each of SiC substrates 11 and 12 can be further increased, and damage to the crystallinity of SiC substrates 11 and 12 can be suppressed.

Preferably, the step of introducing the first and second gases is performed at a pressure of 1 × 10 ⁻² Pa or less. Thereby, the adhesive strength between SiC layer 30 and each of SiC substrates 11 and 12 can be further increased.

  Preferably, the impurity concentrations of SiC substrates 11 and 12 and the impurity concentration of SiC layer 30 are different from each other. Thereby, a semiconductor substrate having a two-layer structure with different impurity concentrations can be obtained.

  Preferably, the impurity concentration of SiC layer 30 is higher than the impurity concentration of each of SiC substrates 11 and 12. Thereby, the resistivity of SiC layer 30 can be made smaller than the resistivity of each of SiC substrates 11 and 12.

  Preferably, the step of forming SiC layer 30 includes a step of introducing at least one of a third gas containing N and a fourth gas containing P onto heated SiC substrates 11 and 12. Including. Thereby, SiC layer 30 can contain at least one of N and P as an impurity.

  Preferably, the step of arranging SiC substrates 11 and 12 is performed such that the distance at which side surfaces S1 and S2 face each other is 200 μm or less. Thereby, the space can be more reliably filled with the SiC layer 30.

  Preferably, in the above embodiment, the off angle of the surface F1 with respect to the {0001} plane of the SiC substrate 11 is not less than 50 ° and not more than 65 °, and the off angle of the surface F2 with respect to the {0001} plane of the SiC substrate 12 is It is 50 degrees or more and 65 degrees or less. Thereby, the channel mobility in the surface F1 and F2 can be raised compared with the case where the surfaces F1 and F2 are {0001} planes.

  Preferably, the angle formed between the off orientation of surface F1 and the <1-100> direction of SiC substrate 11 is 5 ° or less, and the off orientation of surface F2 and the <1-100> direction of SiC substrate 12 The formed angle is 5 ° or less. Thereby, the channel mobility in the surface F1 and F2 can be raised more.

  Preferably, the off angle of the surface F1 with respect to the {03-38} plane in the <1-100> direction of the SiC substrate 11 is −3 ° to 5 °, and the {1-100> direction of the SiC substrate 12 is { The off-angle of the surface F2 with respect to the 03-38} plane is −3 ° to 5 °. Thereby, the channel mobility in the surfaces F1 and F2 can be further increased.

  Preferably, the angle formed by the off orientation of surface F1 and the <11-20> direction of SiC substrate 11 is 5 ° or less, and the off orientation of surface F2 and the <11-20> direction of SiC substrate 12 The formed angle is 5 ° or less. Thereby, the channel mobility in the surface F1 and F2 can be raised compared with the case where the surfaces F1 and F2 are {0001} planes.

  Next, the results of studying manufacturing conditions suitable for manufacturing the semiconductor substrate 80 will be described below.

  First, the temperature at which SiC substrates 11 and 12 were heated was examined. As a result, when the temperature is 700 ° C., it is difficult to bond the SiC layer 30 to each of the SiC substrates 11 and 12, but when the temperature is 750 ° C., this bonding can be performed, and further 950 ° C. In the case of 1150 ° C., 1200 ° C., and 1250 ° C., this adhesion could be performed more firmly. In addition, when the temperature was 1250 ° C., damage to the crystallinity of the SiC substrates 11 and 12 was large. However, when the temperature was 1200 ° C., this damage could be suppressed, and further, 1150 ° C., 950 ° C., 750 ° C. In the case of ℃, this damage could be further suppressed. From this result, in order to adhere the SiC layer 30 and each of the SiC substrates 11 and 12 more reliably and to suppress damage to the crystallinity of the SiC substrates 11 and 12, this temperature is 750 ° C. or more and 1200 ° C. The following were found to be preferred.

Second, the pressure at which the raw material gas was introduced was examined. As a result, when this pressure was 1 × 10 ⁻¹ Pa, it was difficult to bond the SiC layer 30 and each of the SiC substrates 11 and 12, but when this pressure was 1 × 10 ⁻² Pa, this bonding was difficult. In addition, in the case of 1 × 10 ⁻³ Pa and 1 × 10 ⁻⁴ Pa, this adhesion could be performed more firmly. From this result, it was found that the pressure is preferably 1 × 10 ⁻² Pa or less in order to bond the SiC layer 30 and each of the SiC substrates 11 and 12 more reliably.

(Embodiment 2)
Referring to FIG. 5, semiconductor device 100 of the present embodiment is a vertical DiMOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor), and includes substrate 80, buffer layer 121, breakdown voltage holding layer 122, p region 123, It has an n ⁺ region 124, a p ⁺ region 125, an oxide film 126, a source electrode 111, an upper source electrode 127, a gate electrode 110, and a drain electrode 112.

  Substrate 80 has n-type conductivity in the present embodiment, and has SiC layer 30 and SiC substrate 11 as described in the first embodiment. Drain electrode 112 is provided on SiC layer 30 so that SiC layer 30 is sandwiched between SiC substrate 11 and drain electrode 112. The buffer layer 121 is provided on the SiC substrate 11 so that the SiC substrate 11 is sandwiched between the buffer layer 121 and the SiC layer 30.

Buffer layer 121 has n-type conductivity and has a thickness of 0.5 μm, for example. The concentration of the n-type conductive impurity in the buffer layer 121 is, for example, 5 × 10 ¹⁷ cm ⁻³ .

The breakdown voltage holding layer 122 is formed on the buffer layer 121 and is made of silicon carbide whose conductivity type is n-type. For example, the thickness of the breakdown voltage holding layer 122 is 10 μm, and the concentration of the n-type conductive impurity is 5 × 10 ¹⁵ cm ⁻³ .

On the surface of the breakdown voltage holding layer 122, a plurality of p regions 123 having a p-type conductivity are formed at intervals. An n ⁺ region 124 is formed in the surface layer of the p region 123 inside the p region 123. A p ⁺ region 125 is formed at a position adjacent to the n ⁺ region 124. From the top of the n ⁺ region 124 in one p region 123, the breakdown voltage holding layer 122 exposed between the p region 123 and the two p regions 123, the other p region 123, and the n ⁺ region 124 in the other p region 123 An oxide film 126 is formed so as to extend to. A gate electrode 110 is formed on the oxide film 126. A source electrode 111 is formed on the n ⁺ region 124 and the p ⁺ region 125. An upper source electrode 127 is formed on the source electrode 111.

The maximum value of the nitrogen atom concentration in the region within 10 nm from the interface between the oxide film 126 and the n ⁺ region 124, p ⁺ region 125, p region 123 and the breakdown voltage holding layer 122 as the semiconductor layer is 1 × 10 ²¹ cm ^−3. That's it. Thereby, the mobility of the channel region under the oxide film 126 (part of the p region 123 between the n ⁺ region 124 and the breakdown voltage holding layer 122, which is in contact with the oxide film 126) can be improved. .

  Next, a method for manufacturing the semiconductor device 100 will be described. 7 to 10 show only steps in the vicinity of SiC substrate 11 among SiC substrates 11 to 19 (FIG. 1), but similar steps are performed in the vicinity of each of SiC substrate 12 to SiC substrate 19. It is.

  First, in the substrate preparation step (step S110: FIG. 6), the semiconductor substrate 80 (FIGS. 1 and 2) is prepared. The conductivity type of the semiconductor substrate 80 is n-type.

  Referring to FIG. 7, buffer layer 121 and breakdown voltage holding layer 122 are formed as follows by the epitaxial layer forming step (step S120: FIG. 6).

First, the buffer layer 121 is formed on the surface of the substrate 80. Buffer layer 121 is made of n-type silicon carbide and is, for example, an epitaxial layer having a thickness of 0.5 μm. Further, the concentration of the conductive impurity in the buffer layer 121 is set to 5 × 10 ¹⁷ cm ⁻³ , for example.

Next, the breakdown voltage holding layer 122 is formed on the buffer layer 121. Specifically, a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method. The thickness of the breakdown voltage holding layer 122 is, for example, 10 μm. The concentration of the n-type conductive impurity in the breakdown voltage holding layer 122 is, for example, 5 × 10 ¹⁵ cm ⁻³ .

Referring to FIG. 8, p region 123, n ⁺ region 124, and p ⁺ region 125 are formed as follows by the implantation step (step S130: FIG. 6).

First, an impurity having a p-type conductivity is selectively implanted into a part of the breakdown voltage holding layer 122, whereby the p region 123 is formed. Next, n ⁺ region 124 is formed by selectively injecting n-type conductive impurities into a predetermined region, and p-type conductive impurities having a conductivity type are selectively injected into the predetermined region. As a result, a p ⁺ region 125 is formed. The impurity is selectively implanted using a mask made of an oxide film, for example.

  After such an implantation step, an activation annealing process is performed. For example, annealing is performed in an argon atmosphere at a heating temperature of 1700 ° C. for 30 minutes.

Referring to FIG. 9, a gate insulating film forming step (step S140: FIG. 6) is performed. Specifically, oxide film 126 is formed so as to cover the breakdown voltage holding layer 122, p region 123, n ⁺ region 124, and p ⁺ region 125. This formation may be performed by dry oxidation (thermal oxidation). The dry oxidation conditions are, for example, a heating temperature of 1200 ° C. and a heating time of 30 minutes.

Thereafter, a nitrogen annealing step (step S150) is performed. Specifically, an annealing process is performed in a nitrogen monoxide (NO) atmosphere. For example, the heating temperature is 1100 ° C. and the heating time is 120 minutes. As a result, nitrogen atoms are introduced in the vicinity of the interface between each of the breakdown voltage holding layer 122, the p region 123, the n ⁺ region 124, and the p ⁺ region 125 and the oxide film 126.

  Note that an annealing process using an argon (Ar) gas that is an inert gas may be performed after the annealing process using nitrogen monoxide. The conditions for this treatment are, for example, a heating temperature of 1100 ° C. and a heating time of 60 minutes.

  Referring to FIG. 10, source electrode 111 and drain electrode 112 are formed as follows by the electrode formation step (step S160: FIG. 6).

First, a resist film having a pattern is formed on the oxide film 126 by photolithography. Using this resist film as a mask, portions of oxide film 126 located on n ⁺ region 124 and p ⁺ region 125 are removed by etching. As a result, an opening is formed in the oxide film 126. Next, a conductor film is formed in contact with each of n ⁺ region 124 and p ⁺ region 125 in this opening. Next, by removing the resist film, the portion of the conductor film located on the resist film is removed (lifted off). The conductor film may be a metal film, and is made of nickel (Ni), for example. As a result of this lift-off, the source electrode 111 is formed.

  In addition, it is preferable that the heat processing for alloying is performed here. For example, heat treatment is performed for 2 minutes at a heating temperature of 950 ° C. in an atmosphere of argon (Ar) gas that is an inert gas.

  Referring to FIG. 5 again, upper source electrode 127 is formed on source electrode 111. A drain electrode 112 is formed on the back surface of the substrate 80. Thus, the semiconductor device 100 is obtained.

  Note that a structure in which the conductivity types in this embodiment are switched, that is, a structure in which the p-type and the n-type are replaced can also be used.

  Although a vertical DiMOSFET is illustrated, other semiconductor devices may be manufactured using the semiconductor substrate of the present invention. For example, a RESURF-JFET (Reduced Surface Field-Junction Field Effect Transistor) or a Schottky diode is manufactured. Also good.

(Appendix 1)
The semiconductor substrate of the present invention is manufactured by the following manufacturing method.

  A first silicon carbide substrate having a first crystal surface and a first back surface facing each other and a first side surface connecting the first surface and the first back surface and having a single crystal structure, and a first silicon carbide substrate facing each other And a second silicon carbide substrate having a single crystal structure and a second side surface connecting the second surface and the second back surface and a second side surface connecting the second surface and the second back surface. The first and second silicon carbide substrates are arranged such that each of the first and second back surfaces faces one direction and the first and second side surfaces face each other. After this disposing step, the silicon carbide layer is formed on the first and second silicon carbide substrates so as to connect the first and second back surfaces to each other and to fill a space where the first and second side surfaces oppose each other. Is formed by molecular beam epitaxy.

(Appendix 2)
The semiconductor device of the present invention is manufactured using a semiconductor substrate manufactured by the following manufacturing method.

  A first silicon carbide substrate having a first crystal surface and a first back surface facing each other and a first side surface connecting the first surface and the first back surface and having a single crystal structure, and a first silicon carbide substrate facing each other And a second silicon carbide substrate having a single crystal structure and a second side surface connecting the second surface and the second back surface and a second side surface connecting the second surface and the second back surface. The first and second silicon carbide substrates are arranged such that each of the first and second back surfaces faces one direction and the first and second side surfaces face each other. After this disposing step, the silicon carbide layer is formed on the first and second silicon carbide substrates so as to connect the first and second back surfaces to each other and to fill a space where the first and second side surfaces oppose each other. Is formed by molecular beam epitaxy.

  The embodiments and examples disclosed herein are illustrative in all respects and should not be construed as being restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The method for manufacturing a semiconductor substrate of the present invention can be particularly advantageously applied to a method for manufacturing a semiconductor substrate including a portion made of silicon carbide having a single crystal structure.

  DESCRIPTION OF SYMBOLS 11 SiC substrate (1st silicon carbide substrate), 12 SiC substrate (2nd silicon carbide substrate), 13-19 SiC substrate, 30 SiC layer (silicon carbide layer), 80 Semiconductor substrate, 81 Heating body, 100 Semiconductor device .

Claims (15)

A first silicon carbide substrate having a first crystal surface and a first back surface facing each other and a first side surface connecting the first surface and the first back surface and having a single crystal structure, and facing each other Preparing a second silicon carbide substrate having a single crystal structure and having a second surface and a second back surface and a second side surface connecting the second surface and the second back surface; ,
Disposing the first and second silicon carbide substrates such that each of the first and second back surfaces faces one direction and the first and second side surfaces oppose each other;
After the arranging step, the first and second silicon carbide substrates are formed on the first and second silicon carbide substrates so that the first and second back surfaces are connected to each other and the first and second side surfaces are opposed to each other. Forming a silicon carbide layer by a molecular beam epitaxy method.   The method for manufacturing a semiconductor substrate according to claim 1, wherein the silicon carbide layer has a single crystal structure.   The step of forming the silicon carbide layer includes a step of heating the first and second silicon carbide substrates, and a first gas containing Si on the heated first and second silicon carbide substrates. The method for manufacturing a semiconductor substrate according to claim 1, further comprising: introducing a second gas containing C.   The method of manufacturing a semiconductor substrate according to claim 3, wherein the first gas includes at least one of silane, disilane, dichlorosilane, and trichlorosilane.   5. The method of manufacturing a semiconductor substrate according to claim 3, wherein the second gas includes at least one of methane, propane, and acetylene.   The step of heating the first and second silicon carbide substrates is performed by heating the first and second silicon carbide substrates to a temperature of 750 ° C. or higher and 1200 ° C. or lower. A method for manufacturing a semiconductor substrate according to claim 1. The method of manufacturing a semiconductor substrate according to claim 3, wherein the introducing step is performed at a pressure of 1 × 10 ⁻² Pa or less.   The method for manufacturing a semiconductor substrate according to claim 1, wherein an impurity concentration of each of the first and second silicon carbide substrates is different from an impurity concentration of the silicon carbide layer.   The method for manufacturing a semiconductor substrate according to claim 1, wherein an impurity concentration of the growth layer is higher than an impurity concentration of each of the first and second silicon carbide substrates.   The step of forming the silicon carbide layer introduces at least one of a third gas containing nitrogen and a fourth gas containing phosphine onto the heated first and second silicon carbide substrates. The manufacturing method of the semiconductor substrate in any one of Claims 1-9 including a process.   The step of disposing the first and second silicon carbide substrates is performed such that a distance at which the first and second side surfaces oppose each other is 200 μm or less. A method for manufacturing a semiconductor substrate.   The off angle of the first surface with respect to the {0001} plane of the first silicon carbide substrate is not less than 50 ° and not more than 65 °, and the second surface with respect to the {0001} plane of the second silicon carbide substrate The manufacturing method of a semiconductor substrate according to claim 1, wherein the off angle is not less than 50 ° and not more than 65 °.   The angle formed by the off orientation of the first surface and the <1-100> direction of the first silicon carbide substrate is 5 ° or less, and the off orientation of the second surface and the second silicon carbide The method for manufacturing a semiconductor substrate according to claim 12, wherein an angle formed by a <1-100> direction of the substrate is 5 ° or less.   The off angle of the first surface with respect to the {03-38} plane in the <1-100> direction of the first silicon carbide substrate is -3 ° or more and 5 ° or less, and the <1-100> direction of the second silicon carbide substrate is < The method for manufacturing a semiconductor substrate according to claim 13, wherein an off angle of the second surface with respect to the {03-38} plane in the 1-100> direction is not less than −3 ° and not more than 5 °.   The angle formed between the off orientation of the first surface and the <11-20> direction of the first silicon carbide substrate is 5 ° or less, and the off orientation of the second surface and the second silicon carbide The method for manufacturing a semiconductor substrate according to claim 12, wherein an angle formed by a <11-20> direction of the substrate is 5 ° or less.

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