JP2011066684A - Solid-state imaging element, driving method thereof, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily performing six-pixel-horizontal-count of pixels having the same color in a solid-state imaging element at a high frame rate. <P>SOLUTION: The solid-state imaging element includes: a plurality of pixels 42 arranged and formed in the shape of a two-dimensional array on a surface part of a semiconductor substrate; a plurality of vertical charge transfer paths 43 formed along a plurality of pixel columns; a line memory 45 having a buffer region for receiving and temporarily holding signal charge from each of the plurality of vertical charge transfer paths 43 and formed along the edges of the plurality of vertical charge transfer paths 46 in a transfer direction; and a horizontal charge transfer path 46 formed adjacently to the line memory 45 to transfer signal charge received from the buffer region of the line memory 45, wherein one of horizontal transfer stages which is connected to the two buffer regions corresponding to two vertical charge transfer paths, and one of horizontal transfer stages connected to the buffer region corresponding to one vertical charge transfer path, are prepared alternately. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device having a structure that can easily add 6 pixels, a driving method thereof, and an imaging apparatus.

  In recent years, CCD-type solid-state imaging devices mounted on digital still cameras have been increased in the number of pixels so that high-definition still images can be taken. However, even with a digital still camera, it is necessary to equip a movie shooting function. Therefore, when shooting a movie, the number of output pixels is reduced to shorten the time required for charge transfer. Earn rates.

  However, in the case of a moving image, each captured image can be obtained only by a signal for a very short time exposure. Therefore, simply reducing the number of output pixels by thinning out pixels results in a dark image. . Therefore, the number of output pixels is reduced by adding pixels so that a bright image can be obtained.

  For example, in the solid-state imaging device described in Patent Document 1 below, a multistage independent electrode structure is provided at the final stage of the vertical charge transfer path, and 4-pixel addition is performed.

JP 2004-180284 A

  In recent years, in order to obtain moving image data, it has become common to add four pixels of the same color and output from a solid-state imaging device. However, the number of pixels has further increased to 12 million pixels (vertical 3000 pixels × horizontal 4000 pixels). ), The number of horizontal pixels is 1000 pixels by adding four pixels, which is too large for VGA (480 pixels × 640 pixels), which is the average size of moving images.

  Therefore, when 6 pixels are added, the number of horizontal pixels is 667 pixels, which is optimal without excess or deficiency with respect to VGA. Also, if the structure of the solid-state imaging device is easy for 6-pixel addition driving, 3-pixel addition is also easy, which is optimal for high-definition video (720 × 1280).

  However, in the conventional solid-state imaging device described in Patent Document 1, for example, a single vertical charge transfer path corresponds to each transfer stage of the horizontal charge transfer path, so a complicated driving procedure must be developed. There is a problem that 6-pixel addition cannot be realized and it is difficult to realize 6-pixel addition without reducing the frame rate.

  An object of the present invention is to provide a solid-state imaging device having a structure capable of easily realizing 6-pixel addition, a driving method thereof, and an imaging device.

  The solid-state imaging device according to the present invention includes a plurality of pixels that are formed in a two-dimensional array on the surface of a semiconductor substrate, each storing signal charges according to the amount of received light, and a plurality of pixel columns that are formed by the pixels. And a plurality of vertical charge transfer paths that transfer the signal charges detected along the pixels, and a buffer area that receives and temporarily holds the signal charges for each of the plurality of vertical charge transfer paths. A line memory formed along a transfer direction end of the vertical charge transfer path, and a horizontal line formed adjacent to the line memory and transferring the signal charge received from the buffer area of the line memory to an output stage. One horizontal transfer stage connected to the two buffer areas corresponding to the two vertical charge transfer paths and the buffer area corresponding to the one vertical charge transfer path. And a horizontal transfer stages one stage, characterized in that it comprises a horizontal charge transfer path provided alternately that.

  In the solid-state imaging device driving method of the present invention, the signal charges of the same color held in every other buffer area of the line memory are transferred to the horizontal charge transfer path, and 6 pixels are added on the horizontal charge transfer path. It is characterized by that.

  An image pickup apparatus according to the present invention includes the solid-state image pickup device described above and an image pickup device driving unit that drives the solid-state image pickup device and performs horizontal six-pixel addition driving of the same color pixels.

  According to the present invention, since the horizontal charge transfer path is provided so that one horizontal transfer stage corresponds to 1.5 vertical charge transfer paths on average, it is possible to easily add 6 horizontal pixels at a high frame rate. It becomes.

It is a functional block block diagram of the imaging device which concerns on one Embodiment of this invention. It is a surface schematic diagram of the CCD type solid-state imaging device shown in FIG. It is a detailed block diagram in the dotted-line rectangular frame III shown in FIG. It is a block diagram of the solid-state image sensor which shows the comparative example with respect to FIG. It is a figure which shows the operation | movement procedure of horizontal 6 pixel addition of the same color pixel in the CCD type solid-state image sensor shown in FIG. FIG. 6 is the same diagram as FIG. 5, and is an explanatory diagram for adding 6 pixels of G signal charge. FIG. 6 is the same diagram as FIG. 5, and is an explanatory diagram for adding 6 pixels of R signal charge. It is a figure which shows the operation | movement procedure of 4 pixel addition in the comparative example shown in FIG. It is a surface schematic diagram of the CCD type solid-state imaging device concerning another embodiment of the present invention.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a functional block diagram of an imaging apparatus (a digital still camera with a moving image shooting function in this example) according to an embodiment of the present invention. The imaging apparatus 20 includes an imaging unit 21, an analog signal processing unit 22 that performs analog processing such as automatic gain adjustment (AGC) and correlated double sampling processing on analog image data output from the imaging unit 21, and analog signal processing. An analog / digital conversion unit (A / D) 23 that converts analog image data output from the unit 22 into digital image data, and an A / D 23 and an analog signal processing unit 22 in accordance with instructions from a system control unit (CPU) 29 described later. , A drive unit (including a timing generator TG) 24 that controls the drive of the imaging unit 21 and a flashlight 25 that emits light in response to an instruction from the CPU 29.

  The image sensor drive unit 24 receives instructions from the CPU 29 such as vertical transfer pulses φV1 to φV3, horizontal transfer pulses φH1 to φH8, read pulses, line memory control pulses φLM1, φLM2, and electronic shutter pulses, which will be described later. Output to.

  The imaging unit 21 collects light from the object field, a diaphragm or a mechanical shutter 21b that condenses the light that has passed through the optical lens system 21a, and a diaphragm that is condensed by the optical lens system 21a. A CCD type solid-state imaging device 35 that receives the received light and outputs captured image data (analog image data).

  The imaging apparatus 20 of the present embodiment further includes a digital signal processing unit 26 that takes in digital image data output from the A / D 23 and performs interpolation processing, white balance correction, RGB / YC conversion processing, and the like, and image data as JPEG format or the like. A compression / decompression processing unit 27 that compresses or reversely decompresses the image data, a liquid crystal display unit 28 that is provided on the back side of the camera and displays a menu screen, a through image, and a captured image, and an overall control of the entire imaging apparatus. A system control unit (CPU) 29, an internal memory 30 such as a frame memory, and a media interface (I / F) unit 31 that performs interface processing between a recording medium 32 that stores JPEG image data and the like. The system controller 29 includes an operation unit 3 for inputting instructions from the user. There has been connected.

  FIG. 2 is a schematic view of the surface of the CCD solid-state imaging device 35 shown in FIG. A plurality of pixels (photodiodes: PD) 42 are arrayed on the surface of the semiconductor substrate 41 in a two-dimensional array form, in the illustrated example, in a square lattice form. On each pixel 42, primary color R (red), G (green), and B (blue) color filters are arranged in a Bayer array.

  A vertical charge transfer path (VCCD) 43 is provided along each of a plurality of pixel columns composed of pixels 42, and each pixel 42 and the vertical charge transfer path 43 are connected by a read gate 44. A line memory (LM) 45 as described in, for example, Japanese Patent Application Laid-Open No. 2009-49353 is provided along the transfer direction end of each vertical charge transfer path 43, and the horizontal charge is parallel to the line memory 45. A transfer path (HCCD) 46 is provided. An amplifier 47 is provided at the output end of the horizontal charge transfer path 46 to output a voltage value signal corresponding to the amount of signal charge transferred as a picked-up image signal.

  The line memory 45 includes a buffer area (memory unit) corresponding to each vertical charge transfer path 43, temporarily holds the signal charges transferred from the corresponding vertical charge transfer path 43, and the image sensor driving unit 24 in FIG. Is controlled so as to transfer the held signal charges to the horizontal charge transfer path 46 by the timing control of the two-phase line buffer control pulses φLM1 and φLM2 output from.

  In this embodiment, the horizontal charge transfer path 46 is constituted by a number of serial transfer stages. In this embodiment, transfer is controlled by eight-phase transfer pulses φH1 to φH8 output from the image sensor driving unit 24.

  Although the terms “horizontal” and “vertical” have been described, this only means “one direction” along the surface of the semiconductor substrate and “a direction substantially perpendicular to the one direction”.

  FIG. 3 is a detailed configuration diagram in the rectangular frame III shown in FIG. 2, and a total of 16 pixels 42 of 4 × 4 on the horizontal charge transfer path 46 side, a vertical charge transfer path (VCCD) 43, 3 is an enlarged view of a main part of a line memory 45 and a horizontal charge transfer path 46. FIG.

  The feature of this embodiment is one transfer stage of the horizontal charge transfer path 46 and the number of vertical charge transfer paths 43 corresponding to this one transfer stage. In the illustrated example, three transfer stages of the horizontal charge transfer path 46 are shown. However, one transfer stage on the left side corresponds to two vertical charge transfer paths 43, and one transfer stage in the middle is vertical. This corresponds to one of the charge transfer paths 43, and one transfer stage on the right side corresponds to two of the vertical charge transfer paths 43, and this is repeated.

  That is, each transfer stage of the horizontal charge transfer path 46 according to this embodiment corresponds to two and one vertical charge transfer path alternately “2” “1” “2” “1”. It is characterized by that.

  As is well known, each transfer stage of the horizontal charge transfer path 46 is a combination of a barrier unit and a storage unit depending on the impurity concentration of the buried channel, and the horizontal transfer between the barrier unit and the storage unit constituting one transfer stage. Transfer pulses φHi (i = 1 to 8) having the same phase are applied to the electrodes.

  In this embodiment, the transfer pulse of the horizontal charge transfer path 46 is driven in eight phases, the transfer pulse φH1 is applied to a certain transfer stage, the transfer pulse φH2 is applied to the next adjacent transfer stage,. The transfer pulse φH8 is applied to the transfer stage, the transfer pulse φH1 is then applied to the adjacent transfer stage, and so on.

  The line memory 45 is configured to apply two-phase drive control pulses φLM1, φLM2. That is, a control pulse is provided for every other memory section constituting the line memory 45 (the basic structure is the same as that of the charge transfer section, and is composed of a buried channel and an electrode film via a gate insulating film). φLM1 is applied, and the control pulse φLM2 is applied every other one.

  FIG. 4 is a diagram showing a comparative example for comparison with FIG. 3, and shows a solid-state imaging device having a structure that can easily add horizontal four pixels of the same color pixels. The difference between the configuration of FIG. 4 and the configuration of FIG. 3 is that in FIG. 4, each transfer stage of the horizontal charge transfer path corresponds to one vertical charge transfer path. It is the same as FIG.

  Since the length of each transfer stage of the horizontal charge transfer path (the length in the horizontal transfer direction) is equal, if the interval between the vertical charge transfer paths in FIG. 3 is equal to the interval between the vertical charge transfer paths in FIG. Each transfer stage length of the horizontal charge transfer path of the solid-state imaging device of this embodiment is 1.5 times that of the comparative example of FIG.

  That is, in the embodiment shown in FIG. 3, it is easy to add six pixels of the same color horizontally by adopting a structure corresponding to three vertical charge transfer paths 43 in two transfer stages of the horizontal charge transfer path 46. .

  FIG. 5 is a diagram showing a driving procedure for performing horizontal 6-pixel addition of the same color pixels in the solid-state imaging device 35 shown in FIG. Hereinafter, transfer and pixel addition will be described with reference to FIGS. 6 and 7 are the same as FIG.

  As shown in the upper part of FIG. 6, the signal charge rows arranged immediately before the line memory of each vertical charge transfer path are arranged with “R1”, “G1”, “R1”, “G1”. G1 is also lined up every other line. In the upper part of FIG. Each of these signal charges is transferred and stored in one buffer area for one vertical charge transfer path. Note that “1” in R1 and G1 indicates that there is one signal charge.

  Even in the line memory 45, every other signal charge R1 is stored, and every other signal charge G1 is stored. Since the line memory 45 is driven by two-phase control pulses φLM1 and φLM2, by applying a control pulse to the line memory electrode at the signal charge G1 storage position, only the signal charge G1 is output from the line memory shown in FIG. Reading is performed on the horizontal charge transfer path 46 in accordance with the arrow. Since three line memory buffer areas correspond to two transfer stages of the horizontal charge transfer path 45, the signal charge G1 is stored in three consecutive horizontal transfer stages, and the next horizontal transfer stage is left open. Are stored in the three horizontal transfer stages.

  The horizontal electrodes of the horizontal transfer stage storing the first three signal charges G1 are H2, H3 and H4, and the horizontal electrodes of the horizontal transfer stage storing the next three signal charges G1 are H6, H7 and H8. Since the horizontal transfer pulse is an 8-phase pulse and can be applied separately, first, the transfer pulse is applied to the horizontal electrodes H3 and H4 to advance step by step, and the transfer pulse is applied to the horizontal electrodes H7 and H8 to step by step. When proceeding, the signal charge under the horizontal electrode H2 becomes 2 charges and becomes G2 (2 indicates 2 charges) (indicated by reference numeral 51), and the signal charge under the horizontal electrode H6 also becomes 2 charges and becomes G2. (Indicated by reference numeral 52).

  Further, at the same time as described above, when the horizontal transfer pulse is applied to the horizontal electrodes H3 and H7 and advanced one step at a time, the signal charges under the electrodes H2 and H6 are combined into three charges, and G3 (3 is the three charges). (Denoted by reference numeral 53). Next, when the signal charge G3 under the electrode H2 is not moved and the signal charge under the electrode H6 is transferred to the position under the electrode H2, the G1 signal charge is mixed by 6 pixels at the position 54, and the horizontal 6 pixels are added. Signal. Thereafter, G6 (6 indicates 6 charges) obtained by adding these 6 pixels is transferred as it is.

  Next, as shown in FIG. 7, horizontal 6-pixel addition of the signal charge R1 is performed. In the upper part of FIG. 7, twelve signal charges R1 arranged in the horizontal direction are marked with a circle. The first six are added and the next six are added. First, only six signal charges R1 of the latter half are read out to the horizontal charge transfer path 46 as indicated by an arrow.

  Then, these four signal charges R1 are mixed at the position indicated by reference numeral 55 on the horizontal charge transfer path in the same manner as the transfer mixing of the signal charges G1 described above, and the signal charge R4 (4 indicates four charges) is mixed. obtain. Next, after these signal charges R4 are transferred to the lower side of the electrode H2, the remaining two signal charges R1 are read out to the horizontal charge transfer path as indicated by the arrows, and transferred for one stage. A signal charge R6 obtained by adding 6 pixels at the position is obtained.

  In the following, 6 pixels are similarly added to the signal charges g1 in the next stage (lower case letter g is distinguished from G1 aligned with R), B1, g1,... To complete the horizontal addition of 6 pixels of the same color, and the amplifier 47 Output from.

  In the description of FIGS. 5 to 7, 6 pixels are finally added. However, by stopping the addition of 3 pixels during the addition and outputting from the amplifier 47, the size of the high-definition moving image can be obtained.

  FIG. 8 is a diagram showing an operation procedure for adding four horizontal pixels of the same color pixel in the solid-state imaging device shown in FIG. 4, and is a diagram for comparison with the embodiment of 6-pixel addition in FIG. The addition method is the same as that described with reference to FIGS. 6 and 7, and will not be described. However, the time until the horizontal 4-pixel addition is completed is the same as that of the present embodiment described with reference to FIGS. 6 and 7. This is equivalent to the horizontal 6 pixel addition.

  However, when adding 6 pixels with the structure of the solid-state imaging device shown in FIG. 4, the more complicated operation procedure shown in FIG. 8 must be devised, and more time is required until the 6-pixel addition is completed. As a result, the frame rate becomes severe.

  FIG. 9 is a configuration diagram of a main part of a CCD solid-state imaging device 60 according to another embodiment of the present invention. In this solid-state imaging device 60, a plurality of pixels 42 are formed in a two-dimensional array on the surface of a semiconductor substrate, and odd-numbered pixel rows are formed with a shift of ½ pixel pitch with respect to even-numbered pixel rows. Thus, a so-called honeycomb pixel array is formed.

  Pixels in even rows are arranged in a square lattice, and RGB color filters are arranged in a Bayer array using the pixels as a group of pixels constituting the A plane. Similarly, the pixels in the odd-numbered rows are also arranged in a square lattice, and RGB color filters are arranged in a Bayer array using this as a pixel group constituting the B surface.

  Then, one vertical charge transfer path 43 is provided for two pixel columns, and the two pixel columns share one vertical charge transfer path. With this configuration, only the signal charge R and the signal charge G are transferred to one vertical charge transfer path 43, and two pixels of the same color as RRGGRRRGG. Only the signal charge G and the signal charge B are transferred to the next one vertical charge transfer path 43, and two consecutive pixels of the same color as GGBBGGGBB.

  Therefore, in this solid-state imaging device 60, two pixels of the same color can be added on the vertical charge transfer path 43.

  Similar to the solid-state image sensor 35 of FIG. 3, the solid-state image sensor 60 is provided with a line memory 45 and a horizontal charge transfer path 46, and corresponds to three vertical charge transfer paths in two horizontal transfer stages.

  Thereby, a total of 12 pixels can be added by adding 2 pixels on the vertical charge transfer path and adding 6 pixels on the horizontal charge transfer path.

  Although only the pixel arrangement and the color filter arrangement in FIGS. 3 and 9 have been described, even in another color filter arrangement, the same color signal charges are arranged every other horizontal direction, and every other remaining one. In the configuration in which the same color signal charges are arranged, the horizontal memory addition and the horizontal charge transfer path shown in FIGS.

  In each of the above-described embodiments, one horizontal transfer stage of the horizontal charge transfer path corresponds to 1.5 vertical charge transfer paths on average to facilitate the horizontal 6-pixel addition of the same color pixels. If one horizontal transfer stage of the charge transfer path is made to correspond to two vertical charge transfer paths, it is easy to add 8 horizontal pixels of the same color. When the number of mounted pixels of the solid-state imaging device is further increased, this horizontal 8-pixel addition becomes effective.

  When two vertical charge transfer paths are associated with one horizontal transfer stage, each of the horizontal electrodes Hi (i = 1 to 8) is two electrodes of line buffer electrodes L1 and L2, as can be seen from the upper diagram of FIG. Corresponding to For this reason, when adding 6 pixels, as shown in FIG. 6, three signal charges G1 are read out and one horizontal electrode is vacant, but a vertical charge transfer path is provided in one horizontal transfer stage. When two are made to correspond to each other, the signal charge G1 is continuously read out without an empty horizontal electrode portion, and the addition of 8 pixels becomes easy.

  As described above, the solid-state imaging device according to the embodiment includes a plurality of pixels that are arranged in a two-dimensional array on the surface of the semiconductor substrate and each store signal charges corresponding to the amount of received light, and the pixels. A plurality of vertical charge transfer paths that are formed along a plurality of pixel columns and transfer the signal charges detected by the pixels, and the signal charges are received and temporarily held in each of the plurality of vertical charge transfer paths. A line memory having a buffer area and formed along the transfer direction ends of the plurality of vertical charge transfer paths; and the signal charges received from the buffer area of the line memory formed adjacent to the line memory. A horizontal charge transfer path for transferring to the output stage, and one horizontal transfer stage connected to the two buffer areas corresponding to the two vertical charge transfer paths and the front corresponding to the one vertical charge transfer path. Characterized in that it comprises a horizontal charge transfer path and the horizontal transfer stage 1 stage alternately provided which is connected to the buffer region.

  In the solid-state imaging device of the embodiment, the line memory is driven in two phases.

  In the solid-state imaging device of the embodiment, the horizontal charge transfer path is driven in eight phases.

  The solid-state imaging device according to the embodiment is characterized in that the plurality of pixels are arrayed in a square lattice pattern on the surface portion of the semiconductor substrate, and a color filter array is Bayer array.

  In the solid-state imaging device according to the embodiment, the odd-numbered pixel rows of the plurality of pixels arranged in a two-dimensional array on the surface portion of the semiconductor substrate are shifted by 1/2 pixel pitch with respect to the even-numbered pixel rows. The color filters are formed in a Bayer array for the pixels in the odd rows and the color filters are also Bayer arrayed in the pixels in the even rows, and one common vertical charge is provided for every two pixel columns of the pixels. A transfer path is provided.

  In the solid-state imaging device driving method according to the embodiment, the signal charges of the same color held in every other buffer area of the line memory are transferred to the horizontal charge transfer path, and 6 pixels are formed on the horizontal charge transfer path. It is characterized by adding.

  In the solid-state imaging device driving method according to the embodiment, the signal charges of two pixels of the same color that are continuous on the vertical charge transfer path are added, and the signals of the same color held in every other buffer region of the line memory are added. A total of 12 pixels are added by transferring charges to the horizontal charge transfer path and adding 6 pixels on the horizontal charge transfer path.

  An imaging apparatus according to the embodiment includes the solid-state imaging device described above and imaging device driving means that drives the solid-state imaging device and performs horizontal six-pixel addition driving of pixels of the same color.

  According to the embodiment described above, horizontal 6-pixel addition is facilitated, and a VGA size moving image can be obtained at a high frame rate.

  In addition, the solid-state imaging device according to the embodiment includes a plurality of pixels that are formed in a two-dimensional array on the surface portion of the semiconductor substrate and each store signal charges corresponding to the amount of received light, and a plurality of pixels configured by the pixels. A plurality of vertical charge transfer paths that are formed along a column and transfer the signal charges detected by the pixels, and a buffer area that receives and temporarily holds the signal charges for each of the plurality of vertical charge transfer paths. A line memory formed along a transfer direction end of the plurality of vertical charge transfer paths, and the signal charge formed adjacent to the line memory and received from the buffer area of the line memory to the output stage. And a horizontal charge transfer path connected to the two buffer regions corresponding to the two vertical charge transfer paths.

  With this configuration, even when the number of mounted pixels of the solid-state imaging device is increased, horizontal 8-pixel addition is facilitated, and a VGA size moving image can be read at a high frame rate.

  The CCD type solid-state imaging device according to the present invention can easily and quickly add 6 pixels, so that a moving image can be obtained without reducing the frame rate, and a digital still camera, a digital video camera, a camera-equipped mobile phone can be obtained. It is useful when applied to camera-equipped electronic devices such as PDAs and notebook computers, and imaging devices such as endoscopes in general.

DESCRIPTION OF SYMBOLS 20 Image pick-up device 21 Image pick-up part 24 Drive part 26 containing an image pick-up element drive means Digital signal processing part (DSP)
29 System Controller (CPU)
35, 60 CCD type solid-state imaging device 42 pixel 43 vertical charge transfer path 44 readout gate 45 line memory 46 horizontal charge transfer path

Claims (9)

  A plurality of pixels arranged in a two-dimensional array on the surface of the semiconductor substrate, each of which accumulates signal charges corresponding to the amount of received light, and a plurality of pixel columns formed by the pixels, and detected by the pixels A plurality of vertical charge transfer paths for transferring the signal charges, and a buffer region for receiving and temporarily holding the signal charges for each of the plurality of vertical charge transfer paths. A line memory formed along an end of the direction, and a horizontal charge transfer path formed adjacent to the line memory for transferring the signal charge received from the buffer area of the line memory to an output stage, the vertical charge transfer path One horizontal transfer stage connected to the two buffer areas corresponding to two charge transfer paths and one horizontal transfer stage connected to the buffer area corresponding to one vertical charge transfer path intersect. Solid-state imaging device and a horizontal charge transfer path provided.   The solid-state imaging device according to claim 1, wherein the line memory is driven in two phases.   The solid-state imaging device according to claim 1 or 2, wherein the horizontal charge transfer path is driven in eight phases.   4. The solid-state imaging device according to claim 1, wherein the plurality of pixels are arrayed in a square lattice pattern on a surface portion of the semiconductor substrate, and a color filter array is Bayer-arrayed. .   4. The solid-state imaging device according to claim 1, wherein odd-numbered pixel rows of a plurality of pixels arranged in a two-dimensional array on a surface portion of a semiconductor substrate are even-numbered pixel rows. The color filters are formed in a Bayer array for odd rows of pixels, and the color filters are also Bayer arrayed for even rows of pixels. A solid-state imaging device in which one shared vertical charge transfer path is provided for each.   6. The solid-state imaging device driving method according to claim 1, wherein the signal charges of the same color held in every other buffer region of the line memory are supplied to the horizontal charge transfer path. A method of driving a solid-state imaging device that transfers and adds 6 pixels on the horizontal charge transfer path.   6. The method of driving a solid-state imaging device according to claim 5, wherein signal charges of two pixels of the same color that are continuous on the vertical charge transfer path are added, and the same color held in every other buffer region of the line memory. A solid-state imaging device driving method that adds a total of 12 pixels by transferring the signal charge to the horizontal charge transfer path and adding 6 pixels on the horizontal charge transfer path.   An image pickup apparatus comprising: the solid-state image pickup device according to any one of claims 1 to 5; and an image pickup device driving unit that drives the solid-state image pickup device and performs horizontal six-pixel addition driving of pixels of the same color.   A plurality of pixels arranged in a two-dimensional array on the surface of the semiconductor substrate, each of which accumulates signal charges corresponding to the amount of received light, and a plurality of pixel columns formed by the pixels, and detected by the pixels A plurality of vertical charge transfer paths for transferring the signal charges, and a buffer region for receiving and temporarily holding the signal charges for each of the plurality of vertical charge transfer paths. A horizontal charge transfer path for transferring the signal charge received from the buffer area of the line memory, which is formed adjacent to the line memory, to the output stage. A solid-state imaging device, wherein one stage includes a horizontal charge transfer path connected to the two buffer regions corresponding to the two vertical charge transfer paths.

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