JP2011066042A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A compressive stress is applied to a channel formation region of a P-channel transistor using a SiGe layer, and a leakage current is reduced.
A semiconductor device includes a source region and a drain region formed on a surface portion of a semiconductor substrate, and a gate electrode formed on a channel formation region sandwiched therebetween by a gate insulating film. Including a P-channel transistor. A recess is formed in the semiconductor substrate 100 on each side of the gate electrode 102, and a recess is formed on the first epitaxial layer 111 made of SiGe, and on the second epitaxial layer 112 made of Si and made thereon. And a third epitaxial layer 113 made of SiGe and sandwiching a channel formation region. The source region and the drain region 122 are formed in the third epitaxial layer 113, and each junction depth is shallower than the depth of the third epitaxial layer 133.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a P-channel transistor having a SiGe epitaxial film in a source / drain region and a manufacturing method thereof.

  The increase in capacity of semiconductor devices in recent years is remarkable. The miniaturization of MOS (Metal Oxide Semiconductor) transistors is also progressing, and the width of the gate electrode is about to be 40 nm or less. In addition, a distortion technique for increasing driving force by applying stress to a channel formation region of a transistor (a region where a channel is formed in a substrate) of a transistor has already been put into practical use in response to the increase in speed.

  According to the strain technique, the band structure of the channel formation region is changed by introducing strain into the channel formation region of the transistor. As a result, the effective mass of carriers in the channel formation region changes, causing a change in band occupancy, and the channel portion mobility changes.

  In order to apply strain to the channel formation region, it is necessary to apply stress to the channel formation region. The direction of stress to be applied differs between NMOS (n-channel MOS) and PMOS (p-channel MOS). Specifically, it is known that when uniaxial stress is applied in the channel direction, it is necessary to apply tensile stress in NMOS and compressive stress in PMOS.

  Among these, as a distortion technique for dramatically increasing the carrier mobility in the PMOS transistor, a lattice larger than silicon so as to be embedded in the source / drain (S / D) regions on both sides of the channel formation region (below the gate electrode) in the substrate. A method of forming a silicon germanium film having a constant by epitaxial growth has been proposed (Non-Patent Document 1).

  According to this method, a compressive stress caused by a lattice constant difference can be applied to the channel formation region below the gate electrode from the side. The compressive stress applied to the channel formation region increases as the concentration of germanium contained in silicon germanium increases.

T. Ghani et. Al., IEDM Tech. Dig., P978-980, 2003 K. Ang et. Al., IEDM Tech. Dig., P1069, 2004

  However, in the MOS transistor having the structure described above, there is an example in which the channel mobility does not increase as expected and the driving power of the transistor does not increase. Furthermore, there is a tendency that the leakage current increases. Therefore, the solution of these points becomes a problem.

  In view of the above, the object of the present invention is to improve channel portion mobility more reliably in a transistor configured to apply a compressive stress to a channel formation region using a SiGe epitaxial layer, A semiconductor device capable of suppressing current and a method for manufacturing the same are provided.

  In order to achieve the above object, the inventors of the present invention have examined the reason why the channel portion mobility is not improved as compared with the expectation and the reason why the leakage current is increased. This will be described below.

  FIG. 6 shows a structure in which a gate electrode 12 with a sidewall 13 is formed on a semiconductor substrate 10 and a silicon germanium (SiGe) film 11 is buried in an S / D region on the side of the gate electrode 12 by epitaxial growth. Show.

  When the SiGe crystal is epitaxially grown on the Si substrate (semiconductor substrate 10), a crystal defect 14 is generated as the strain energy increases (Non-patent Document 2). The SiGe epitaxial film thickness that can be grown without the occurrence of such crystal defects is called the critical film thickness. The critical film thickness decreases as the Ge concentration increases. As a specific example, FIG. 7 shows the relationship between film thickness and lattice relaxation for a SiGe layer having a Ge concentration of about 30 atom%. Since the lattice relaxation becomes large when crystal defects occur, the lattice relaxation suddenly increases when the film thickness exceeds about 80 nm, and it can be understood that the critical film thickness is about 80 nm.

  Further, in order to effectively apply the compressive stress due to the SiGe crystal formed on Si to the channel formation region, the portion that becomes the S / D region of the P channel has a depth that includes at least the side of the channel formation region by etching. A recess is formed, and a SiGe epitaxial layer is formed in the recess. Further, in order to prevent a substrate digging beside the side wall in the subsequent process, the SiGe epitaxial layer is formed on the substrate so as to have a certain height. For this reason, when the recess portion and the portion on the substrate are combined, the thickness of the SiGe epitaxial layer to be grown may be 80 nm or more.

  As described above, when the Ge concentration is 30 atom% or more and the film thickness is 80 nm, crystal defects are generated in the SiGe layer and the stress is relaxed. As a result, there arises a problem that compressive stress cannot be effectively applied to the channel formation region.

Further, at the interface between SiGe and Si on the bottom surface of the recess, there is an interface impurity such as O (oxygen) that cannot be removed by cleaning before epitaxial growth, H ₂ baking during epitaxial growth, or the like. Such interface impurities cause a stacking fault 14 in the SiGe epitaxial layer (see FIG. 6). Since the stacking fault 14 here penetrates the SiGe crystal layer, it also penetrates the S / D junction interface formed in the SiGe crystal, causing junction leakage.

  From the above examination results, the inventors of the present application have conceived that an SiGe epitaxial layer free from stacking faults or the like is formed in a portion sandwiching the channel formation region from both sides to ensure the application of stress. Furthermore, the inventors conceived of suppressing the leakage current by positioning the S / D junction interface in a portion free from crystal defects.

  Specifically, a semiconductor device according to the present invention includes a source region and a drain region formed on a surface portion of a semiconductor substrate, and a gate electrode formed on a channel formation region sandwiched therebetween by a gate insulating film. A recess formed in the semiconductor substrate on each side of the gate electrode, and a recess formed in the first epitaxial layer made of silicon germanium, and a second epitaxial layer made of silicon and formed thereon And a third epitaxial layer made of silicon germanium and sandwiching the channel formation region. The source region and the drain region are formed in the third epitaxial layer, and each junction depth is Is shallower than the depth of the third epitaxial layer.

  According to such a semiconductor device, the channel formation region is compressed by the epitaxial layer formed in the recesses on both sides of the gate electrode, particularly the third epitaxial layer made of silicon germanium (SiGe) and sandwiching the channel formation region. Stress can be applied.

  At this time, with respect to the third epitaxial layer, the occurrence of stacking faults and lattice relaxation is suppressed for reasons described later. Therefore, a compressive stress can be reliably applied to the channel formation region, and the channel portion mobility can be improved. Further, since the junction depth of the source region and the drain region is shallower than the depth of the third epitaxial layer, the S / D junction interface can be made free of crystal defects that cause a leakage current. As a result, leakage current can be reduced.

  The reason why the generation of stacking faults and lattice relaxation is suppressed in the third epitaxial layer is as follows.

  First, crystal defects such as stacking faults are likely to occur in the first epitaxial layer due to interface impurities such as O on the bottom surface of the recess (interface between the semiconductor substrate and the first epitaxial layer). However, by forming the second epitaxial layer made of silicon on the first epitaxial layer, the crystal defects are absorbed in the second epitaxial layer so that no crystal defects exist on the upper surface of the second epitaxial layer. can do. Therefore, generation of crystal defects can be suppressed for the third epitaxial layer formed on the second epitaxial layer.

  In addition, by providing three epitaxial layers in the recess, the thickness of the third epitaxial layer, which is the main part sandwiching the channel formation region, can be suppressed, and the critical film thickness can be reduced. For this reason, the occurrence of lattice relaxation in the third epitaxial layer is suppressed.

The source region and the drain region are preferably formed by introducing a P-type impurity, and the P-type impurity is preferably not introduced into the first epitaxial layer and the second epitaxial layer. The third epitaxial layer preferably includes a layer having a P-type impurity concentration of 1 × 10 ¹⁸ / cm ³ or more.

  In this way, the junction depth of the source region and the drain region can be surely made shallower than the depth of the third epitaxial layer.

The third epitaxial layer has a P-type impurity concentration of 0 / cm ³ to 1 × 10 ¹⁸ / in the range from the interface between the second epitaxial layer and the third epitaxial layer to the junction depth of the source region or the drain region. It is preferable to have a P-type impurity profile that varies to cm ³ .

The S / D junction interface of the source region or the drain region is a surface having an impurity concentration of about 1 × 10 ¹⁸ / cm ³ for forming these regions. Therefore, the source region and the drain region can be reliably arranged in the third epitaxial layer by setting the position where the concentration is to be shallower than the lower surface of the third epitaxial layer.

  The first epitaxial layer preferably contains germanium of 25 atom% or more. The third epitaxial layer preferably contains 30 atom% or more of germanium.

  An epitaxial layer made of silicon germanium should have such a germanium concentration. In particular, the third epitaxial layer should have such a concentration in order to apply compressive stress to the channel formation region.

  The third epitaxial layer is preferably thicker than the first epitaxial layer, and the first epitaxial layer is preferably thicker than the second epitaxial layer.

  Since it is mainly the third epitaxial layer that applies stress to the channel formation region, it is necessary to increase the thickness of this layer. Further, the second epitaxial layer made of silicon only needs to have a film thickness that can absorb stacking faults and the like in the first epitaxial layer. For these reasons, the film thicknesses of the first, second, and third epitaxial layers are preferably in the relationship as described above.

  The first epitaxial layer preferably has a thickness of 10 nm or more. Thereby, it can be set as the silicon germanium layer which covers the bottom face of a recess.

  The second epitaxial layer preferably has a thickness of 5 nm or more and 20 nm or less.

  With such a film thickness, a stacking fault or the like of the first epitaxial layer can be absorbed and a second epitaxial layer having no crystal defect on the upper surface can be obtained. Thereby, it can function as a base for forming a defect-free third epitaxial layer.

  The third epitaxial layer preferably has a film thickness that is equal to or less than the critical film thickness.

  As a result, the third epitaxial layer can be realized as a silicon germanium layer free from stacking faults, and compressive stress can be effectively applied to the channel formation region.

  The third epitaxial layer is preferably formed so as to rise above the upper surface of the semiconductor substrate.

  Thereby, the substrate digging after the third epitaxial layer is formed can be prevented.

  Further, it is preferable that an N-channel transistor is further provided in addition to the P-channel transistor, and the N-channel transistor does not include a region made of silicon germanium.

  That is, a CMOS (complementary MOS) including an N-channel transistor (NMOS) together with a P-channel transistor (PMOS) configured as described above is preferable. In addition, for NMOS, even if compressive stress is applied to the channel formation region, the channel portion mobility does not improve, but rather decreases. Therefore, for NMOS, it is better not to provide a region made of silicon germanium.

  Next, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a P-channel transistor. A step (a), a step (b) of forming a recess in the semiconductor substrate on each side of the gate electrode, a step (c) of forming a first epitaxial layer made of silicon germanium in the recess, and a first epitaxial layer Forming a second epitaxial layer made of silicon on the layer; and forming a third epitaxial layer made of silicon germanium on the second epitaxial layer so as to sandwich a channel formation region below the gate electrode. Step (e), and performing the step (e) while adjusting the amount of P-type impurity introduced, thereby providing a third epitaxial layer. The interstitial layer, the junction depth to form shallow source and drain regions than the depth of the third epitaxial layer.

  If it does in this way, the semiconductor substrate of this indication already explained can be manufactured. That is, a compressive stress can be applied to the channel formation region by the third epitaxial layer made of SiGe in which stacking faults are suppressed, so that the channel portion mobility can be improved, and defects at the S / D junction interface are suppressed. Therefore, a semiconductor substrate in which leakage current is suppressed can be manufactured.

  In addition, it is preferable to perform a process (c) and a process (d) by epitaxial growth, without including a P-type impurity.

Further, in the step (e), by forming the third epitaxial layer while increasing the introduction amount of the P-type impurity in accordance with the growth of the third epitaxial layer, the interface between the second epitaxial layer and the third epitaxial layer is formed. It is preferable to obtain a P-type impurity profile in which the P-type impurity concentration varies from 0 / cm ³ to 1 × 10 ¹⁸ / cm ³ in the range up to the junction depth of the source region or drain region.

  In this case, the first and second epitaxial layers do not contain P-type impurities, and a semiconductor device having a source region and a drain region in which P-type impurities are introduced into the third epitaxial layer can be obtained. .

  The third epitaxial layer preferably contains 30% or more germanium and has a thickness equal to or less than the critical thickness.

  Thereby, since the Ge concentration is relatively high and there is no lattice relaxation, a third epitaxial layer that can reliably apply compressive stress to the channel formation region can be obtained.

  In addition, it is preferable to further include a step of forming a metal silicide on the third epitaxial layer and performing a heat treatment after the step (e) to form a metal silicide.

  In this way, a semiconductor device having a metal silicide layer can be manufactured.

  Further, after step (a) and before step (b), an extension region is formed by a step of forming an offset sidewall covering the side wall of the gate electrode and ion implantation using the gate electrode and the offset sidewall as a mask. Preferably, the method further includes a step and a step of covering the side wall of the offset sidewall and forming a sidewall having the same height as the gate electrode.

  This may be done in order to form a P-channel transistor that further includes offset sidewalls, sidewalls, extension regions, and the like.

  In addition to the P-channel transistor, an N-channel transistor is preferably formed, and the N-channel transistor preferably has no silicon germanium region.

  Thereby, it is possible to realize a PMOS that further includes an N-channel transistor that does not apply compressive stress to the channel formation region.

  Although described as a MOS transistor in the above, it can be applied to a MIS (metal-insulator-semiconductor) transistor.

  According to the semiconductor device of the present invention, stacking faults and the like in the first epitaxial layer made of silicon germanium are absorbed by the second epitaxial layer made of silicon and do not reach the third epitaxial layer. Furthermore, the source region and the drain region are formed to be shallower than the depth of the third epitaxial layer so that there is no defect at the S / D junction interface. As a result, compressive stress is effectively applied to the channel formation region to improve channel portion mobility, and leakage current due to defects at the S / D junction interface can be reduced.

FIG. 1 is a diagram illustrating a cross-section of the main part of an exemplary semiconductor device according to the first embodiment of the present invention. 2A to 2F are diagrams for explaining the manufacturing process of the semiconductor device of FIG. FIG. 3 is a diagram for explaining a cross-section of the main part of an exemplary semiconductor device according to the second embodiment of the present invention. 4A to 4E are diagrams for explaining a manufacturing process of the semiconductor device of FIG. FIGS. 5A to 5D are diagrams for explaining manufacturing steps of the semiconductor device of FIG. 3 following FIG. FIG. 6 is a diagram illustrating an example of stacking faults in the silicon germanium layer embedded in the semiconductor substrate on the side of the gate electrode. FIG. 7 is a diagram showing the film thickness dependence of lattice relaxation for a silicon germanium layer containing 30 atom% germanium.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the materials and dimensions of each component, the conditions for various treatments, etc. are only examples, and are not limited to the description.

(First embodiment)
FIG. 1 is a diagram schematically illustrating a cross-sectional structure of a PMOS transistor included in the exemplary semiconductor device 120 according to the first embodiment.

As shown in FIG. 1, the semiconductor device 120 is formed using an N-type semiconductor substrate 100. A gate electrode 102 made of polysilicon is formed on a semiconductor substrate 100 with a gate insulating film 101 made of SiO ₂ interposed therebetween. A metal silicide layer 121 is formed on the gate electrode 102.

An offset sidewall 104 made of SiO ₂ or the like is formed so as to cover the side wall of the gate electrode 102. In addition, extension regions 105 are formed in the semiconductor substrate 100 on both sides of the gate electrode 102. Further, a first sidewall 106 having an L-shaped cross section and made of SiO ₂ is formed so as to cover the sidewall of the offset sidewall 104 and the extension region 105, and the first sidewall 106 is A second sidewall 107 made of SiN is formed.

  Further, on both sides of the gate electrode 102, the semiconductor substrate 100 is provided with a recess by etching or the like, and three epitaxial layers are laminated on the recess.

  More specifically, first, a first epitaxial layer 111 having a thickness of at least 10 nm is formed so as to cover the bottom surface of the recess. This is made of silicon germanium (SiGe) having a germanium concentration of 25 atom% or more, and is not doped with a P-type impurity such as B.

  A second epitaxial layer 112 having a thickness of 5 nm or more and 20 nm or less is formed on the first epitaxial layer 111. This is made of silicon not containing germanium, and is not doped with P-type impurities such as B.

  On the second epitaxial layer 112, a third epitaxial layer 113 having a thickness of about 50 nm is formed. This is made of silicon germanium having a germanium concentration of 30 atom% or more.

In the third epitaxial layer 113, a P-type impurity such as B is doped to form S / D (source / drain) regions 122 sandwiching a channel formation region below the gate electrode 102 (on both sides of the gate electrode 102). A source region is formed in one of the third epitaxial layers 113, and a drain region is formed in the other). Here, the interface between the second epitaxial layer 112 and the third epitaxial layer 113 contains no P-type impurities. The concentration of the P-type impurity gradually increases from the interface toward the shallow side of the third epitaxial layer 113, and at the top, for example, a concentration of about 1 × 10 ²³ / cm ³ .

In general, a position where the impurity concentration is about 1 × 10 ¹⁸ / cm ³ is defined as an S / D junction interface. For this reason, in the configuration of the present embodiment, the S / D junction interface is above the interface between the second epitaxial layer 112 and the third epitaxial layer 113 and is located in the third epitaxial layer 113. However, it is also possible to consider other density positions as the interface.

  A metal silicide layer 121 is formed on the S / D region 122 and the gate electrode 102.

  According to the above configuration, the compressive stress can be applied to the channel formation region by the epitaxial layer made of SiGe embedded in the recesses on both sides of the gate electrode 102, particularly the third epitaxial layer 113. Here, the generation of stacking faults and lattice relaxation is suppressed for the third epitaxial layer 113 for reasons described later. For this reason, a compressive stress can be reliably applied to the channel formation region, and the channel portion mobility can be improved. Further, since the junction depth of the S / D region 122 (the depth of the S / D junction interface) is shallower than the depth of the third epitaxial layer 113, the S / D junction interface has a stacking fault that causes a leakage current. It is located in the area where there is no etc. Therefore, the leakage current is reduced.

FIG. 1 illustrates a profile of a P-type impurity introduced to configure the S / D region 122 in accordance with the structure of the semiconductor device 120. As shown in the drawing, the P-type impurity concentration is 0 at the interface depth D1 between the second epitaxial layer 112 and the third epitaxial layer 113. The depth D2 of the S / D junction interface where the P-type impurity concentration is about 1 × 10 ¹⁸ / cm ³ is at a position shallower than D1. The P-type impurity concentration further increases from the depth D2 toward the top of the third epitaxial layer 113.

  Next, the reason why the generation of stacking faults and lattice relaxation is suppressed in the third epitaxial layer 113 will be described.

  First, crystal defects such as stacking faults are likely to occur in the first epitaxial layer 111 due to interface impurities (for example, oxygen) on the bottom surface of the recess (interface between the semiconductor substrate 100 and the first epitaxial layer 111). However, the crystal defects can be absorbed by forming the second epitaxial layer 112 made of silicon on the first epitaxial layer 111. That is, even if there is a crystal defect in the first epitaxial layer 111, the upper surface of the second epitaxial layer 112 having a certain thickness is a surface having no defect. Therefore, the third epitaxial layer 113 formed on the second epitaxial layer 112 can avoid the influence of crystal defects in the first epitaxial layer 111.

  In addition, by providing three epitaxial layers in the recess, the thickness of the third epitaxial layer 113 which is a main portion sandwiching the channel formation region can be suppressed, and the thickness can be reduced to a critical thickness or less. For this reason, the occurrence of lattice relaxation in the third epitaxial layer is suppressed. In this example, since the germanium concentration is 30 atom%, the critical film thickness is about 80 nm, and the third epitaxial layer 113 is thinner than this.

  Next, a method for manufacturing the semiconductor device 120 will be described with reference to FIGS. 2A to 2F which are cross-sectional views schematically showing the process.

First, the process of FIG. Here, a gate insulating film 101 made of, for example, SiO ₂ is formed on the semiconductor substrate 100. A polysilicon film and a SiO ₂ film are sequentially laminated thereon, a mask (not shown) is formed, and the gate electrode 102 and the SiO ₂ film 103 thereon are formed by etching.

Next, an SiO ² film is further formed to cover the semiconductor substrate 100, the side surface of the gate electrode 102 and the SiO ₂ film 103, and etched back to form an offset sidewall 104 on the side wall of the gate electrode 102.

  Next, ion implantation is performed using the gate electrode 102, the offset sidewall 104, and the like as a mask, and extension regions 105 are formed near the surface of the semiconductor substrate 100 on both sides of the gate electrode 102.

The gate insulating film 101 may be formed of a high dielectric material such as HfSiO instead of SiO ₂ . Further, the gate electrode 102 may have a laminated structure of a metal such as TiN and polysilicon instead of the single layer structure made of polysilicon.

Subsequently, the process of FIG. 2B is performed. First, a SiO ₂ film is formed so as to cover the gate electrode 102 via the offset sidewall 104 and the SiO ₂ film 103, and a silicon nitride film is further formed so as to cover the SiO ₂ film. Next, dry etching is performed to form a first sidewall 106 having an L-shaped cross section covering the sidewall of the gate electrode 102 and the extension region 105, and a second sidewall 107 covering the top.

Subsequently, the process of FIG. Here, the epitaxial cover film 108 is formed so as to cover the semiconductor substrate 100, the second sidewall 107, the SiO ₂ film 103, and the like. Epitaxial cover film 108, the film density than the SiO ₂ film 103 on the gate electrode 102 is low, to form a SiO ₂ film can be formed, for example, by a low temperature of 400 ° C. or less.

  Subsequently, the process of FIG. 2D is performed. Here, a resist 109 having a gate electrode 102 and regions on both sides thereof is formed on the epitaxial cover film 108. Next, the epitaxial cover film 108 in the opening is removed using the resist 109 as a mask. As a result, the portion of the semiconductor substrate 100 in which the epitaxial layer made of SiGe is embedded is exposed.

  Subsequently, the process of FIG. Here, after removing the resist 109, the epitaxial cover film 108 is used as a mask, and either or both of dry etching and wet etching are used to provide the semiconductor substrate 100 with a recess 110 having a depth of 60 nm or more, for example.

  Subsequently, the process of FIG. Here, three epitaxial layers are sequentially formed in the recess 110.

  First, a first epitaxial layer 111 made of SiGe containing germanium of 25 atom% or more is formed so as to cover the bottom of the recess. This is formed at a film thickness of 10 nm or more by epitaxial growth in a hydrogen atmosphere at 650 ° C. or lower. At this time, doping of P-type impurities such as B is not performed.

More specific film forming conditions include, for example, a temperature of 650 ° C., a hydrogen atmosphere (10 Torr (1.33 × 10 ³ Pa)), a gas flow rate DCS / GeH ₄ / HCl / H ₂ = 20/16/35/10000 sccm. (Sccm represents ml / min at 0 ° C. and 1 atm). Hydrogen is a carrier gas. Thereby, the first epitaxial layer 111 made of silicon germanium having a germanium concentration of 25 atom% can be formed.

Next, a second epitaxial layer 112 made of silicon and not containing germanium is formed on the first epitaxial layer 111 continuously. This film is formed to a thickness necessary for absorbing crystal defects generated in the first epitaxial layer 111 and preventing the crystal defects from appearing on the upper surface. As an example of this embodiment, the film thickness is 5 nm or more and 20 nm or less. Epitaxial growth is used for film formation, and P-type impurities such as B are not doped. As an example of film formation conditions, the temperature is 650 ° C., the hydrogen atmosphere (10 Torr (1.33 × 10 ³ Pa)), and the gas flow rate is SiH ₄ / HCl / H ₂ = 30/35/10000 sccm.

Thereafter, a third epitaxial layer 113 made of SiGe containing germanium of 30 atm% or more is formed on the second epitaxial layer 112 further continuously. This is formed at least on both sides of the channel formation region below the gate electrode 102. In addition, the occurrence of lattice relaxation is avoided by setting the critical film thickness or less. As an example of the film forming conditions, the temperature is 650 ° C., the hydrogen atmosphere (10 Torr (1.33 × 10 ³ Pa)), and the gas flow rate is DCS / GeH ₄ / HCl / H ₂ = 30/24/60/10000 sccm.

The third epitaxial layer 113 is doped with a P-type impurity such as B. The concentration profile of P-type impurities such as B is 0 immediately above the second epitaxial layer 112 and 1 × 10 ¹⁸ / cm at the S / D junction interface depth set in the third epitaxial layer 113. ³ and the concentration profile is set to about 1 × 10 ²³ / cm ³ at the top of the third epitaxial layer 113. Here, the depth of the S / D junction interface is set in a region having a depth of 30 nm to 50 nm from the upper surface of the semiconductor substrate 100.

Such a concentration profile can be realized by adjusting the flow rate of B ₂ H ₆ when the third epitaxial layer 113 is epitaxially grown. As a specific example, B ₂ H ₆ is further used as a material gas when the third epitaxial layer 113 is formed under the above-described film formation conditions. At the start of film formation, the B ₂ H ₆ flow rate is set to 0, and the B ₂ H ₆ flow rate is increased as the film formation proceeds. When the film formation proceeds to the set S / D junction interface depth, the flow rate of B ₂ H ₆ is adjusted to 100 sccm, and thereafter 160 sccm.

  In this way, three epitaxial layers are formed on the recesses 110 provided on the semiconductor substrate 100 on both sides of the gate electrode 102.

  Note that the third epitaxial layer 113 may be formed on the semiconductor substrate 100 so as to rise to a height of, for example, about 20 nm to 30 nm. In a later process, the buried epitaxial layer may be scraped, and the substrate may be dug next to the sidewall. Therefore, it is conceivable that the third epitaxial layer 113 is formed so as to rise above the semiconductor substrate 100 in advance so that the substrate is not dug even if the epitaxial layer is shaved.

Thereafter, the epitaxial cover film 108 and the SiO ₂ film 103 on the gate electrode 102 are removed. Further, after forming a metal film (for example, NiPt having a thickness of 10 nm), a metal silicide layer 121 is formed on the gate electrode 102 and the S / D region 122 as shown in FIG.

  As described above, the exemplary semiconductor device 120 of this embodiment is manufactured. Its features and the like are as already described.

  In the above, the germanium concentration of the first epitaxial layer 111 is 25 atom%, and the germanium concentration of the third epitaxial layer 113 is 30 atom%. However, this is not restrictive. A higher compressive stress can be generated as the germanium concentration is increased, but the critical film thickness is reduced, and it is necessary to reduce the thickness in order to avoid lattice relaxation. Therefore, the germanium concentration, the film thickness, and the like may be set in accordance with the size of the PMOS transistor to be formed, required performance, and the like. At this time, it is necessary that the thickness of the third epitaxial layer does not exceed the critical thickness.

(Second Embodiment)
FIG. 3 is a diagram illustrating an exemplary semiconductor device 130 according to the second embodiment.

  The semiconductor device 130 is formed using the semiconductor substrate 100. The surface of the semiconductor substrate 100 is partitioned by a shallow trench 114, and a PMOS transistor and a CMOS transistor are formed to constitute a CMOS transistor.

  Here, the PMOS transistor has the same structure as that described in the first embodiment. That is, three epitaxial layers are embedded in the semiconductor substrate 100 on both sides of the gate electrode 102 that is formed through the gate insulating film 101 and includes the offset sidewall 104, the first sidewall 106, and the second sidewall 107. In this structure, the S / D region 122 is provided in the third epitaxial layer 113.

  As a result, the same characteristics as described in the first embodiment are realized in the PMOS transistor. That is, compressive stress is applied to the channel formation region by the third epitaxial layer 113, and the channel portion mobility is improved. At this time, crystal defects and the like in the first epitaxial layer 111 are absorbed by the second epitaxial layer 112 made of silicon, and the generation of stacking faults and lattice relaxation is suppressed in the third epitaxial layer 113. From this, it is possible to reliably apply the compressive stress. Furthermore, since the S / D junction interface is located in a portion having no crystal defect, a leak current due to the crystal defect can be avoided, and the leak current is reduced.

  On the other hand, the NMOS transistor does not include an epitaxial layer and has a structure having an S / D region 115 formed by doping the semiconductor substrate 100 with impurities. The gate electrode 102, the sidewall, and the like have the same configuration as that of the PMOS transistor.

  In the case of an NMOS transistor, applying a compressive stress to the channel formation region does not contribute to an improvement in channel portion mobility, but rather decreases it. Therefore, the NMOS transistor is not structured to embed an epitaxial layer made of SiGe, and the S / D region 115 is preferably formed by doping the semiconductor substrate 100 with impurities.

In both the PMOS transistor and the NMOS transistor, the gate electrode 102 is made of, for example, polysilicon, and is formed on the semiconductor substrate 100 via the gate insulating film 101 made of, for example, an SiO ₂ film. However, also in this embodiment, the gate insulating film 101 may be formed of a high dielectric such as HfSiO. The gate electrode 102 may have a stacked structure of a metal such as TiN and polysilicon.

  Next, a method for manufacturing the semiconductor device 130 will be described with reference to FIGS. 4A to 4E and FIGS. 5A to 5D which are cross-sectional views schematically showing the process.

The process shown in FIG. 4A will be described. First, a shallow trench 114 is formed on the semiconductor substrate 100 by a conventional technique as an element isolation region that partitions a surface portion. Thereafter, a gate electrode 102 is formed in each region of the semiconductor substrate 100 where a PMOS transistor and an NMOS transistor are formed (hereinafter referred to as a PMOS region and an NMOS region) via a gate insulating film 101, and an SiO ₂ film is formed thereon. 103 is formed. In addition, an offset sidewall 104 that covers the side surface of the gate electrode 102 is formed. Thereafter, extension regions 105 are formed in the semiconductor substrate 100 on both sides of the gate electrode 102 by ion implantation using the gate electrode 102, the offset sidewall 104, and the like as a mask. These are the same steps as described with reference to FIG. 2A in the first embodiment.

Subsequently, the process of FIG. 4B is performed. Here, in both the PMOS region and the NMOS region, a first side wall 106 made of, for example, a SiO ₂ film and having an L-shaped cross section is formed so as to cover the side wall of the gate electrode 102 via the offset side wall 104. Further, a second sidewall 107 made of a silicon nitride film is formed thereon. This is the same process as described in the first embodiment with reference to FIG.

Then, the process of FIG.4 (c) is performed. First, the epitaxial cover film 108 is formed so as to cover the semiconductor substrate 100, the second sidewall 107, the SiO ₂ film 103, and the like in both the PMOS region and the NMOS region. This film density than the SiO ₂ film 103 on the gate electrode 102 is low, to form a SiO ₂ film can be formed, for example, by a low temperature of 400 ° C. or less.

  Next, a resist 131 is formed on the epitaxial cover film 108 so that the sidewalls in the PMOS region, the gate electrode 102, and the regions where the S / D regions 122 on both sides thereof are formed are opened. Further, using the resist 131 as a mask, the epitaxial cover film 108 at the opening is removed, and the PMOS region is exposed.

  Subsequently, the process of FIG. 4D is performed. After removing the resist 131, a recess 110 is formed in the semiconductor substrate 100 on both sides of the gate electrode 102 in the PMOS region using the epitaxial cover film 108 as a mask. For example, one or both of dry etching and wet etching is used, and the depth is 60 nm.

Then, the process of FIG.4 (e) is performed. Here, in the recess 110 formed in the PMOS region, a first epitaxial layer 111 made of SiGe containing 25 atomic percent or more of germanium, a second epitaxial layer 112 made of silicon, and a third epitaxial layer made of SiGe containing 30 atomic percent or more of germanium. Layer 113 is formed sequentially. Here, the first epitaxial layer 111 and the second epitaxial layer 112 are not doped with a P-type impurity such as B. The third epitaxial layer 113 is doped with a P-type impurity such as B to form an S / D region 122. At this time, the impurity concentration is 0 immediately above the second epitaxial layer 112, 1 × 10 ¹⁸ / cm ³ at the S / D junction interface depth set in the third epitaxial layer 113, and 1 at the top of the third epitaxial layer 113. The concentration profile is set to about × 10 ²³ / cm ³ .

  In this way, the compressive stress is applied to the channel formation region below the gate electrode 102, and the third epitaxial layer 113 including the S / D region 122 having the S / D junction interface depth in the portion having no crystal defect, can do.

  More specifically, this is the same as described in the first embodiment with reference to FIG.

  Subsequently, the process of FIG. First, a resist 131 is formed so as to cover the PMOS region and open on the regions where the sidewalls in the NMOS region, the gate electrode 102, and the S / D regions 115 on both sides thereof are formed. Next, the portion of the epitaxial cover film 108 exposed in the opening of the resist 131 is removed, and ion implantation and annealing are performed using each sidewall, the gate electrode 102, and the like as a mask. As a result, the S / D region 115 is formed outside the extension region 125 in the semiconductor substrate 100 in the NMOS region. The annealing condition is, for example, spike annealing at 1025 ° C.

Subsequently, the process of FIG. 5B is performed. Here, the resist 132 is removed, and the SiO ₂ film 103 on the epitaxial cover film 108 and the gate electrode 102 is further removed.

  Subsequently, the process of FIG. 5C is performed. Here, the metal film 116 is formed so as to cover the third epitaxial layer 113 in which the S / D region 122 is formed, the gate electrode 102 and the semiconductor substrate 100 in which the S / D region 115 is formed. This is, for example, a 10 nm thick NiPt film.

  Subsequently, the process of FIG. Here, heat treatment is performed to form a metal silicide layer 121 on the gate electrode 102, the S / D region 122, and the S / D region 115.

  As described above, the semiconductor device 130 having the CMOS transistor is manufactured. Its features and the like are as already described.

  In the above description, MOS transistors have been described as examples. However, the present invention is not limited to MOS transistors, and can be applied to MIS transistors.

  The present invention relates to a PMOS transistor that uses a silicon germanium layer as a source / drain region, a semiconductor having a fine MIS transistor that can improve channel portion mobility and reduce leakage current, and has a gate width of, for example, 40 nm or less. It is also useful as a device and its manufacturing method.

100 Semiconductor substrate 101 Gate insulating film 102 Gate electrode 103 SiO ₂ film 104 Offset sidewall 105 Extension region 106 First sidewall 107 Second sidewall 108 Epitaxial cover film 109 Resist 110 Recess 111 First epitaxial layer 112 Second epitaxial Layer 113 Third epitaxial layer 114 Shallow trench 115 S / D region 116 Metal film 120 Semiconductor device 121 Metal silicide layer 122 S / D region 125 Extension region 130 Semiconductor device 131 Resist 132 Resist

Claims (18)

A p-channel transistor including a source region and a drain region formed on the surface portion of the semiconductor substrate, and a gate electrode formed on the channel formation region sandwiched between the gate electrode and the gate electrode;
A recess is formed in the semiconductor substrate on each side of the gate electrode,
The recess includes a first epitaxial layer made of silicon germanium, a second epitaxial layer made thereon and made of silicon, and a third epitaxial layer made thereon and made of silicon germanium and sandwiching the channel formation region And
The semiconductor device is characterized in that the source region and the drain region are formed in the third epitaxial layer, and each junction depth is shallower than the depth of the third epitaxial layer. In claim 1,
The source region and the drain region are formed by introducing a P-type impurity,
The semiconductor device, wherein the P-type impurity is not introduced into the first epitaxial layer and the second epitaxial layer. In claim 1 or 2,
The third epitaxial layer has a P-type impurity concentration of 0 / cm ³ to 1 × in the range from the interface between the second epitaxial layer and the third epitaxial layer to the junction depth of the source region or the drain region. A semiconductor device having a P-type impurity profile that changes to 10 ¹⁸ / cm ³ . In any one of Claims 1-3,
The semiconductor device according to claim 1, wherein the first epitaxial layer contains germanium of 25 atom% or more. In any one of Claims 1-4,
The semiconductor device, wherein the third epitaxial layer contains germanium of 30 atom% or more. In any one of Claims 1-5,
The third epitaxial layer is thicker than the first epitaxial layer,
The semiconductor device according to claim 1, wherein the first epitaxial layer is thicker than the second epitaxial layer. In any one of Claims 1-6,
The semiconductor device according to claim 1, wherein the first epitaxial layer has a thickness of 10 nm or more. In any one of Claims 1-7,
The second epitaxial layer has a film thickness of 5 nm or more and 20 nm or less. In any one of Claims 1-8,
The semiconductor device, wherein the third epitaxial layer has a film thickness equal to or less than a critical film thickness. In any one of Claims 1-9,
The third epitaxial layer is formed so as to rise above the upper surface of the semiconductor substrate. In any one of Claims 1-10,
In addition to the P-channel transistor, an N-channel transistor is further provided.
The semiconductor device according to claim 1, wherein the N-channel transistor does not include a region made of silicon germanium. In a method for manufacturing a semiconductor device including a P-channel transistor,
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
Forming a recess in the semiconductor substrate on each side of the gate electrode (b);
Forming a first epitaxial layer made of silicon germanium in the recess (c);
Forming a second epitaxial layer made of silicon on the first epitaxial layer (d);
A step (e) of forming a third epitaxial layer made of silicon germanium on the second epitaxial layer so as to sandwich a channel formation region below the gate electrode;
By performing the step (e) while adjusting the introduction amount of the P-type impurity, a source region and a drain region having a junction depth shallower than the depth of the third epitaxial layer are formed in the third epitaxial layer. A method for manufacturing a semiconductor device. In claim 12,
The method of manufacturing a semiconductor device, wherein the step (c) and the step (d) are performed by epitaxial growth without including a P-type impurity. In claim 12 or 13,
In the step (e), by forming the third epitaxial layer while increasing the amount of introduction of P-type impurities in accordance with the growth of the third epitaxial layer, the second epitaxial layer and the third epitaxial layer are formed. A P-type impurity profile is obtained in which the P-type impurity concentration varies from 0 / cm ³ to 1 × 10 ¹⁸ / cm ³ in the range from the interface to the junction depth of the source region or the drain region. A method for manufacturing a semiconductor device. In any one of Claims 12-14,
The third epitaxial layer contains 30% or more of germanium and has a film thickness equal to or less than a critical film thickness. In any one of Claims 12-15,
A method of manufacturing a semiconductor device, further comprising a step of forming a metal silicide on the third epitaxial layer and performing a heat treatment after the step (e) to form a metal silicide. In any one of Claims 12-16,
After the step (a) and before the step (b),
Forming an offset sidewall covering the sidewall of the gate electrode;
Forming an extension region by ion implantation using the gate electrode and the offset sidewall as a mask;
And a step of covering the side wall of the offset side wall and forming a side wall having the same height as the gate electrode. In any one of Claims 12-17,
Forming an N-channel transistor in addition to the P-channel transistor;
The method of manufacturing a semiconductor device, wherein the N-channel transistor has a structure not including a silicon germanium region.

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