JP2011065587A - Processing system and testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce communication traffic in a processing system in which command data generated by a plurality of control parts in parallel are processed by an operation part. <P>SOLUTION: The processing system processes the command data generated in parallel, and includes: the plurality of control parts respectively generating the command data; the operation part operating in response to the given command data; a header information storage part storing header information indicating which control part generates the command data, that is to be transmitted to the operation part; and an interface part which transmits the respective command data generated by the plurality of control parts by eliminating header information stored in the header information storage part, to the operation part, adds the header information stored in the header information storage part to operation result data received from the operation part, and transmits to the control parts. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a processing system and a test apparatus.

  As a test apparatus for testing a device under test such as a semiconductor chip, an apparatus that executes a plurality of processes in parallel is known (see, for example, Patent Document 1). In addition, a device in which a plurality of CPUs generate instructions in parallel and a plurality of operation units operate in parallel according to these instructions is also conceivable. In this case, a plurality of CPUs and a plurality of operation units may be connected via a common interface unit.

JP 2000-20479 A

  The common interface unit includes a common buffer for storing instructions received from a plurality of CPUs, a plurality of individual buffers corresponding to a plurality of operation units, and a distribution unit that sequentially reads the instructions stored in the common buffer and distributes them to the individual buffers. And a communication controller that transmits a command stored in the individual buffer to a corresponding operation unit. Note that the communication controller performs a predetermined time-out process when there is no reply from the operation unit within a predetermined period after transmitting the command to the operation unit.

  The time-out process indicates, for example, a process for retransmitting the instruction or a process for shifting to the instruction next to the instruction. Since each communication controller has a time-out function, when an abnormality occurs in communication between each communication controller and the operation unit or in the operation unit itself, the communication controller operates while repeating the time-out process. For this reason, instructions accumulate in the corresponding individual buffers.

  When an instruction is stored in the individual buffer, the instruction cannot be moved from the common buffer to the individual buffer, and the instruction is stored in the common buffer. As a result, an instruction for an operating unit of a system different from the system in which an abnormality has occurred cannot be written to the common buffer, and the operating unit having no abnormality is also affected.

  In addition, the operation result of the operation unit for a predetermined command is transmitted to the CPU that generated the command. For this reason, header information used to transmit the operation result data to the CPU is attached to the command data and the operation result data. However, if the header information is attached to these data for transmission, the amount of communication increases. In particular, when the operation unit and the communication controller are connected by relatively low-speed serial communication, the influence of the increase in the communication amount becomes significant.

  In order to solve the above-mentioned problem, in the first aspect of the present invention, there is provided a processing system for processing instruction data generated in parallel, each of which includes a plurality of control units for generating instruction data and a given instruction. An operation unit that operates according to data, a header information storage unit that stores header information indicating which control unit is generated in command data to be transmitted to the operation unit, and a plurality of control units From each generated instruction data, the header information stored in the header information storage unit is excluded and transmitted to the operation unit, and the header information stored in the header information storage unit is added to the operation result data received from the operation unit, A processing system including an interface unit that transmits to a control unit, and a test apparatus including the processing system are provided.

  The above summary of the invention does not enumerate all necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

It is a figure showing an example of composition of processing system 100 concerning an embodiment. It is a figure which shows the operation example of the processing system 100 shown in FIG. It is a figure which shows the operation example of the processing system 100 shown in FIG. 3 is a diagram illustrating a configuration example of a distribution unit 36. FIG. It is a figure which shows the structural example of the processing system 100 which concerns on other embodiment. It is a figure which shows the operation example of the processing system 100 demonstrated in relation to FIG. FIG. 6 is a diagram illustrating another configuration example of a distribution unit 36. FIG. 5 is a diagram showing a configuration example of a test apparatus 200 according to another embodiment together with a device under test 300.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a diagram illustrating a configuration example of a processing system 100 according to the embodiment. The processing system 100 is a system that processes instruction data generated in parallel, and includes a control system 10, a data transmission unit 20, an interface unit 30, and a plurality of operation units 50.

  The control system 10 generates a plurality of instruction data in parallel. For example, the control system 10 is provided with a plurality of threads for sequentially specifying instruction data to be generated. The control system 10 includes a plurality of control units 12. The plurality of control units 12 are provided corresponding to the plurality of threads, and each process a corresponding thread. The control unit 12 may be a CPU that generates instruction data corresponding to a thread. The control unit 12 generates command data to which header information indicating which control unit 12 generated the command data and which operation unit 50 should be supplied is attached.

  Each control unit 12 may receive operation result data of the operation unit 50 for the command data. Each control unit 12 may perform a predetermined process on the received operation result data and transmit the data to the thread supplier.

  The data transmission unit 20 transmits data between the control system 10 and the interface unit 30. For example, the data transmission unit 20 receives command data for each operation unit 50 from the control system 10 and transmits the command data to the interface unit 30. Further, the data transmission unit 20 receives the operation result data in each operation unit 50 from the interface unit 30 and transmits it to the control system 10.

  As an example, the data transmission unit 20 may be a transmission device that satisfies the PCI Express standard. The data transmission unit 20 in this example transmits read request command data for reading data in the memory included in the operation unit 50 to the interface unit 30 and then receives operation result data for the read request command data within a predetermined period. If there is no such request, the read request command data may be retransmitted to the interface unit 30.

  In addition, the communication speed of the data transmission unit 20 is preferably faster than the communication speed between the interface unit 30 and the operation unit 50. That is, the communication amount per unit time of the data transmission unit 20 may be larger than the communication amount per unit time between the interface unit 30 and the plurality of operation units 50.

  The interface unit 30 is provided between the data transmission unit 20 and the plurality of operation units 50, and processes data transmitted between the data transmission unit 20 and the plurality of operation units 50. The interface unit 30 includes a common controller 32, a common buffer 34, a distribution unit 36, a plurality of individual buffers 38, and a plurality of individual controllers 40.

  The common controller 32 controls communication between the data transmission unit 20 and the interface unit 30. For example, the common controller 32 may convert the signal received from the data transmission unit 20 into a signal according to the specification of the interface unit 30, and the signal transmitted from the interface unit 30 to the data transmission unit 20 You may convert into the signal according to a specification. The common controller 32 may be a PCI express controller.

  The common buffer 34 is provided between the plurality of operation units 50 and the data transmission unit 20 and stores data to be transmitted between the plurality of operation units 50 and the data transmission unit 20. The common buffer 34 may have an area for storing data transmitted from the plurality of operation units 50 to the data transmission unit 20 and an area for storing data transmitted from the data transmission unit 20 to the plurality of operation units 50.

  The common buffer 34 receives command data for the plurality of operation units 50 from the data transmission unit 20 and stores them in a common area. The common buffer 34 preferably has an area capable of storing at least instruction data equal to or larger than the number of operation units 50.

  The distribution unit 36 is provided between the common buffer 34 and the plurality of individual buffers 38, and transfers data between the common buffer 34 and the plurality of individual buffers 38. For example, the allocating unit 36 sequentially reads the instruction data stored in the common buffer 34 and sequentially distributes and writes the read instruction data to the corresponding individual buffer 38. The allocating unit 36 may preferentially read out instruction data whose time has elapsed since the common buffer 34 was stored.

  The allocating unit 36 may write the instruction data in the individual buffer 38 corresponding to the operation unit 50 specified by the header information of the instruction data. Further, the allocating unit 36 deletes the instruction data that has been written to the individual buffer 38 from the common buffer 34.

  The plurality of individual buffers 38 are provided between the distribution unit 36 and the individual controller 40 in one-to-one correspondence with the plurality of operation units 50. Each individual buffer 38 stores the command data distributed by the distribution unit 36 and sequentially transmits it to the corresponding operation unit 50 via the corresponding individual controller 40. For example, the individual buffer 38 may be a FIFO memory that outputs previously stored data.

  Each individual buffer 38 has an area in which a plurality of instruction data can be stored. Each individual buffer 38 is preferably capable of storing at least instruction data equal to or greater than the number of control units 12.

  The plurality of individual controllers 40 are provided between the individual buffer 38 and the operation unit 50 in a one-to-one correspondence with the plurality of operation units 50. Each individual controller 40 controls communication between the interface unit 30 and the operation unit 50. For example, the individual controller 40 may convert a signal received from the operation unit 50 into a signal according to the specification of the interface unit 30, and a signal transmitted from the interface unit 30 to the operation unit 50 according to the specification of the operation unit 50. May be converted into a signal.

  Communication between the interface unit 30 and each operation unit 50 may be relatively low-speed serial communication. In this case, each individual controller 40 may be a serial communication controller.

  The plurality of operation units 50 operate in accordance with the command data given thereto. For example, each operation unit 50 outputs data at the address specified by the given read request command data, and writes the data specified by the command data at the address specified by the given write request command data. You may have a memory.

  In addition, the operation unit 50 transmits operation result data corresponding to the given command data to the interface unit 30. For example, for the read request command data, operation result data including data read from the memory may be transmitted. In response to the write request command data, operation result data indicating that data writing to the memory has ended may be transmitted. The operation unit 50 may transmit information specifying any of the control units 12 included in the header information of the received instruction data in the header information of the operation result data.

  Each individual controller 40 writes the operation result data received from the corresponding operation unit 50 in the corresponding individual buffer 38. Each individual buffer 38 may independently have an area for storing instruction data and an area for storing operation result data.

  The distribution unit 36 reads the operation result data stored in each individual buffer 38 and writes it in the common buffer 34. At this time, the read operation result data is deleted from the individual buffer 38.

  The common buffer 34 transmits the stored operation result data to the control system 10 via the common controller 32 and the data transmission unit 20. The data transmission unit 20 transmits the operation result data to the control unit 12 specified by the header information of the operation result data. With the above configuration, a plurality of instructions generated in parallel can be processed in parallel via the common interface unit 30.

  FIG. 2 is a diagram illustrating an operation example of the processing system 100 illustrated in FIG. 1. In this example, the operation of the processing system 100 will be described using two operation units 50. If an abnormality occurs in one operation unit 50-A or an abnormality occurs in communication between the operation unit 50-A and the individual buffer 38-A, the instruction data A stored in the individual buffer 38-A is not executed. To accumulate.

  When the instruction data is accumulated and there is no free space in the individual buffer 38-A, the distribution unit 36 cannot write the instruction data A to the individual buffer 38-A. Therefore, the instruction data A for the operation unit 50 -A is stored in the common buffer 34. As a result, there is no free space in the common buffer 34, and the instruction data B for the operation unit 50-B having no abnormality cannot be stored in the common buffer 34, which affects access to the operation unit 50-B. .

  FIG. 3 is a diagram illustrating an operation example of the processing system 100 illustrated in FIG. 1. The distribution unit 36 detects an abnormal state in which command data cannot be transmitted to any of the operation units 50. As shown in FIG. 2, the distribution unit 36 of this example determines that an abnormal state occurs when new instruction data cannot be written in any of the individual buffers 38. In the abnormal state, as described with reference to FIG. 2, the instruction data cannot be deleted from the common buffer 34 and the instruction data is accumulated in the common buffer 34.

  When the distribution unit 36 of this example detects an abnormal state, the distribution unit 36 performs a process according to the instruction data in place of the operation unit 50 in the abnormal state, and deletes the instruction data from the common buffer 34. At this time, the allocating unit 36 does not perform an operation of writing the instruction data in the individual buffer 38. For example, when the distribution unit 36 cannot transmit read request command data to any of the operation units 50, the data transmission unit transmits the pseudo result data including predetermined dummy data as read data via the common buffer 34 or the like. 20 is transmitted.

  The allocating unit 36 may attach at least a part of the header information of the instruction data to the pseudo result data. For example, the allocating unit 36 indicates the header information indicating which pseudo-result data is the result data for the command data to which operation unit 50 and which is the result data to be transmitted to the control unit 12. May be attached to the pseudo result data.

  Further, when the write request command data cannot be transmitted to any of the operation units 50, the allocating unit 36 may delete the command data from the common buffer 34 and read the next command data from the common buffer 34. Also at this time, the distribution unit 36 stops the operation of writing the instruction data in the individual buffer 38.

  According to the processing system 100 of this example, instead of the operation unit 50 in which the abnormal state is detected, the allocating unit 36 processes the command data to the operation unit 50, so that any one of the operation units 50 is in an abnormal state. Even in this case, accumulation of instruction data in the common buffer 34 can be prevented. For this reason, the influence on the other operation | movement part 50 can be excluded.

  Also, in standards such as PCI Express, the data transmission unit 20 receives predetermined operation data such as read request instruction data to the common buffer 34 and then receives operation result data for the instruction data within a predetermined period. If not, the command data may be retransmitted to the common buffer 34. For this reason, when any one of the operation units 50 is in an abnormal state, it is assumed that retransmission of the read request command data to the operation unit 50 is repeatedly performed. On the other hand, according to the processing system 100 of the present example, since the allocating unit 36 transmits the pseudo result data to the data transmitting unit 20, it is possible to prevent the read request command data from being repeatedly retransmitted.

  FIG. 4 is a diagram illustrating a configuration example of the distribution unit 36. The distribution unit 36 of this example includes a distribution processing unit 52, a data processing unit 58, an individual transmission unit 56, a data reception unit 60, and a common transmission unit 62. The data processing unit 58 includes an abnormality determination unit 54 and a pseudo operation unit 72.

  The distribution processing unit 52 refers to the header information of the instruction data read from the common buffer 34 and determines which individual buffer 38 should be written with the instruction data. The abnormality determination unit 54 detects an abnormal state of the individual buffer 38 and the operation unit 50 based on whether or not the instruction data can be written in the individual buffer 38 to which each instruction data is distributed.

  The abnormality determination unit 54 may detect an abnormal state depending on whether or not the individual transmission unit 56 can write the command data in the individual buffer 38. The individual transmission unit 56 writes the received command data in the corresponding individual buffer 38. At this time, when the instruction data cannot be written to the individual buffer 38, the individual transmission unit 56 notifies the abnormality determination unit 54 that the individual buffer 38 and the corresponding operation unit 50 are in an abnormal state.

  The abnormality determination unit 54 transmits the instruction data that could not be written to the individual buffer 38 to the pseudo operation unit 72. The pseudo operation unit 72 performs processing according to the type of the instruction data. As described above, for the read request command data, the pseudo operation unit 72 generates pseudo result data in which at least a part of the header information of the read request command data is added to predetermined dummy data. Further, the pseudo operation unit 72 may generate pseudo result data for pseudo notification of the completion of the write operation in the operation unit 50 for the write request command data, without generating the pseudo result data. Good.

  The data receiving unit 60 receives operation result data in the normal operation unit 50 via the individual buffer 38. The common transmission unit 62 transmits the pseudo result data received from the pseudo operation unit 72 and the operation result data received from the data reception unit 60 to the data transmission unit 20 via the common buffer 34. With such a configuration, the distribution unit 36 can operate in place of the operation unit 50 and the individual buffer 38 that have been determined to be in an abnormal state, and transmits instruction data to the normal operation unit 50 and the individual buffer 38. Can do.

  Further, when the new instruction data cannot be written in any of the individual buffers 38, the abnormality determination unit 54 may transmit the instruction data to be written in the individual buffer 38 to the pseudo operation unit 72 thereafter. Further, when the new instruction data cannot be written in any of the individual buffers 38, the abnormality determination unit 54 does not transmit the instruction data to be written in the individual buffer 38 to the individual transmission unit 56 after that, The writing operation to the individual buffer 38 may be stopped.

  As a result, when the new operation data cannot be written in any of the individual buffers 38, the pseudo operation unit 72 operates the operation unit corresponding to the individual buffer 38 for the instruction data to be written to the individual buffer 38 thereafter. Process on behalf of 50. That is, for the individual buffer 38 and the operation unit 50 in which an abnormality is detected once, the abnormal state is not determined for the subsequent instruction data, so that the data can be processed efficiently.

  If the command data cannot be transmitted to any of the operating units 50, the data processing unit 58 notifies the data transmitting unit 20 that an abnormality has occurred in the transmission of the command data to the operating unit 50. Is preferred. As a result, it is possible to determine whether the result data transmitted to the data transmission unit 20 is the data generated in a pseudo manner by the distribution unit 36 or the data actually generated by the operation unit 50. For example, the pseudo operation unit 72 may attach information indicating that the data is pseudo result data to the header information of the pseudo result data. Further, the pseudo operation unit 72 may delete the header information of the pseudo result data and attach information indicating that the data is the pseudo result data.

  FIG. 5 is a diagram illustrating a configuration example of a processing system 100 according to another embodiment. The processing system 100 of this example further includes a plurality of header information storage units 64 in addition to the configuration of the processing system 100 described with reference to FIGS. 1 to 4. Other configurations may be the same as the processing system 100 described in connection with FIGS.

  The plurality of header information storage units 64 are provided in one-to-one correspondence with the plurality of operation units 50. That is, the processing system 100 includes a plurality of combinations of the operation unit 50 and the header information storage unit 64 in parallel. Each header information storage unit 64 may store header information indicating which control unit 12 generated data in command data to be transmitted to the operation unit 50. That is, the header information storage unit 64 may store header information indicating to which control unit 12 the operation result data corresponding to the command data should be transmitted.

  The interface unit 30 of this example excludes the header information stored in the header information storage unit 64 from each command data generated by the plurality of control units 12 and transmits the data to the operation unit 50. More specifically, the allocating unit 36 stores header information in the header information storage unit 64 among the instruction data read from the common buffer 34, and stores data other than the header information in the individual buffer 38.

  Further, the interface unit 30 attaches the header information stored in the corresponding header information storage unit 64 to the operation result data received from the operation unit 50 and transmits the result to the control unit 12. More specifically, the distribution unit 36 may read the header information from the corresponding header information storage unit 64 when the predetermined operation result data is read from the individual buffer 38. The predetermined operation result data may be operation result data for read request command data, for example. The allocating unit 36 transmits the read header information to the common buffer 34 attached to the operation result data.

  Through such processing, the amount of communication between the interface unit 30 and the operation unit 50 can be reduced, and the operation result data can be accurately transmitted to the control unit 12 that issued the instruction data. it can. As described above, since data is transmitted between the operation unit 50 and the interface unit 30 by relatively low-speed serial communication, the header information specifying the control unit 12 compresses the communication band.

  According to the processing system 100 of this example, the communication band in the serial communication can be efficiently used. Further, since the header information storage unit 64 is provided for each operation unit 50, the header information once separated into the header information storage unit 64 can be attached to the corresponding operation result data.

  When each control unit 12 generates predetermined command data such as read request command data, each control unit 12 operates on the condition that no other command data is generated until operation result data of the operation unit 50 for the command data is received. You can do it. Each operation unit 50 preferably outputs corresponding operation result data in the order in which the instruction data is received. By operating the control unit 12 and the operation unit 50 under such conditions, the once separated header information can be accurately attached to the corresponding operation result data.

  The header information storage unit 64 may store header information for predetermined instruction data, and may not store header information for other instruction data. For example, the header information storage unit 64 may store header information for command data that should receive operation result data from the operation unit 50, and may not store header information for command data that does not receive operation result data from the operation unit 50. .

  More specifically, the header information storage unit 64 does not need to store header information for read request command data and does not store header information for write request command data. In any case, the allocating unit 36 may write the instruction data excluding the header information into the individual buffer 38.

  In this case, when the distribution unit 36 reads predetermined operation result data (for example, operation result data for the read request command data) from the individual buffer 38, the distribution unit 36 reads the header information from the header information storage unit 64 and performs the operation It may be attached to the result data. The operation unit 50 may output identification data identifying whether the operation result data is the operation result data for which type of instruction data attached to the operation result data. For example, the operation unit 50 may output the operation result data for the read request instruction data with identification data indicating that it corresponds to the read request instruction data.

  The allocating unit 36 determines whether the operation result data read from the individual buffer 38 is predetermined command data to which header information is to be attached. Based on the identification data attached to the operation result data read from the individual buffer 38, the distribution unit 36 determines whether to attach the header information stored in the header information storage unit 64 to the operation result data. It may be determined. For example, the distribution unit 36 reads out the header information from the header information storage unit 64 and attaches it to the operation result data when the identification data attached to the operation result data indicates that it corresponds to the read request command data. You can do it.

  FIG. 6 is a diagram illustrating an operation example of the processing system 100 described with reference to FIG. As described with reference to FIG. 5, the distribution unit 36 receives the instruction data generated by the control unit 12 and attached with header information. The distribution unit 36 separates the header information from the instruction data and stores it in the header information storage unit 64. The allocating unit 36 may store header information of a predetermined type of instruction data such as read request instruction data in the header information storage unit 64. The allocating unit 36 stores the instruction data excluding the header information in the individual buffer 38 corresponding to the instruction data.

  The individual buffer 38 transmits the stored instruction data to the operation unit 50. The operation unit 50 operates according to the received command data and transmits the operation result data to the individual buffer 38. Here, in the serial communication between the individual buffer 38 and the operation unit 50, data may be transmitted with a predetermined serial communication header information attached. The serial communication header information may be removed by the distribution unit 36.

  The individual buffer 38 transmits the operation result data received from the operation unit 50 to the distribution unit 36. The allocating unit 36 attaches the header information stored in the header information storage unit 64 to the received operation result data, and transmits it to the control unit 12 via the common buffer 34 or the like. Here, the distribution unit 36 may attach the header information stored in the header information storage unit 64 when the received operation result data is operation result data for a predetermined type of instruction data.

  The header information storage unit 64 may store a plurality of header information corresponding to the number of control units 12. For example, the header information storage unit 64 may store the same number of header information as the number of control units 12. As described above, when each control unit 12 generates a predetermined type of instruction data such as read request instruction data, it does not generate the next instruction data until it receives operation result data for the instruction data. Therefore, each header information storage unit 64 has an area in which the same number of header information as the number of control units 12 can be stored, so that all necessary header information can be stored.

  The header information storage unit 64 may be a FIFO type memory that sequentially outputs the header information stored previously. That is, the distribution unit 36 reads the header information in the order stored in the header information storage unit 64 and attaches the header information to the operation result data received from the operation unit 50 in order. Since each operation unit 50 sequentially processes the instruction data in the order received, by making the header information storage unit 64 FIFO type, it is possible to attach header information to each operation result data with high accuracy. .

  FIG. 7 is a diagram illustrating another configuration example of the distribution unit 36. The distribution unit 36 of this example includes a distribution processing unit 52, a data processing unit 58, an individual transmission unit 56, a header transmission / reception unit 66, a data reception unit 60, and a common transmission unit 62. Further, the data processing unit 58 of this example includes a data separation unit 68 and a data combination unit 70.

  The distribution processing unit 52 refers to the header information of the instruction data read from the common buffer 34 and determines which individual buffer 38 should be written with the instruction data. The data separation unit 68 receives the instruction data distributed by the distribution processing unit 52 and separates the header information.

  The data separation unit 68 removes the header information from the received command data and writes it to the individual buffer 38 via the individual transmission unit 56. In addition, the data separation unit 68 stores the separated header information in the header information storage unit 64 via the header transmission / reception unit 66. As described above, the data separation unit 68 may transmit header information to the header transmission / reception unit 66 for a predetermined type of instruction data.

  The data receiving unit 60 receives operation result data in the operation unit 50 via the individual buffer 38. The data combining unit 70 attaches the header information received from the header transmitting / receiving unit 66 to the operation result data received from the data receiving unit 60 and transmits the operation result data to the common transmitting unit 62.

  As described above, when the received operation result data is operation result data for a predetermined type of instruction data, the data combining unit 70 reads the header information via the header transmission / reception unit 66 and converts the header information into the operation result data. You may attach it. If the received operation result data is not operation result data corresponding to a predetermined type of instruction data, the data combining unit 70 transmits the operation result data to the common transmission unit 62 without adding header information to the operation result data. It's okay. Further, when the received operation result data is not the operation result data corresponding to the predetermined type of instruction data, the data combining unit 70 does not need to transmit the operation result data to the common transmission unit 62.

  The common transmission unit 62 transmits the operation result data received from the data combining unit 70 to the data transmission unit 20 via the common buffer 34 and the like. The data transmission unit 20 transmits the operation result data to the control unit 12 specified by the header information attached to the operation result data. With such a configuration, the operation result data can be transmitted to the control unit 12 that issued the command data while reducing the amount of communication between the interface unit 30 and the operation unit 50.

  The allocating unit 36 may further include the functional blocks described in relation to FIG. In this case, the abnormality determination unit 54 described with reference to FIG. 4 may be provided between the distribution processing unit 52 and the data separation unit 68. The abnormality determination unit 54 transmits command data for the operation unit 50 that is not in an abnormal state to the data separation unit 68.

  The pseudo operation unit 72 is provided between the abnormality determination unit 54 and the common transmission unit 62. That is, the common transmission unit 62 receives result data from both the pseudo operation unit 72 and the data combining unit 70. With such a configuration, an abnormality in one of the operation units 50 does not affect access to the other operation units 50, and the command data is reduced while reducing the communication amount between the interface unit 30 and the operation unit 50. The operation result data can be transmitted to the control unit 12 of the issue source.

  FIG. 8 is a diagram illustrating a configuration example of a test apparatus 200 according to another embodiment together with a device under test 300. The test apparatus 200 is an apparatus for testing a plurality of devices under test 300 such as semiconductor chips in parallel, and includes a control device 210, a test unit 220, a determination unit 230, a processing system 100, and a fail memory 240.

  The control device 210 may include the control system 10 in the processing system 100 described with reference to FIGS. 1 to 7. Further, the fail memory 240 may be included in the operation unit 50 in the processing system 100 described with reference to FIGS. 1 to 7.

  The control device 210 controls the test unit 220, the determination unit 230, the processing system 100, and the fail memory 240. The test unit 220 inputs a test signal for controlling the device under test 300 to a predetermined state to the device under test 300. The test unit 220 may be provided for each device under test 300.

  The determination unit 230 determines pass / fail of the device under test 300. For example, the determination unit 230 determines pass / fail of the device under test 300 based on whether the logical pattern of the response signal output from the device under test 300 in accordance with the test signal matches a predetermined expected value pattern. Good. More specifically, the device under test 300 may include a memory under test, and the test unit 220 may generate a test signal for writing and reading predetermined data to each address of the memory under test.

  The determination unit 230 compares the read data with the expected value data for each address of the memory under test to determine pass / fail. The control device 210 may write the determination result in the determination unit 230 into the fail memory 240 via the processing system 100. A fail memory 240 is provided for each device under test 300. For example, the fail memory 240 may have substantially the same address space as the memory under test. The fail memory 240 may store pass / fail of the corresponding address of the memory under test at each address. The fail memory 240 may be a fail address memory that stores address information determined to be defective.

  Further, the control device 210 may read the fail information written in the fail memory 240 and analyze the test result. Each control unit 12 of the control device 210 executes the writing and reading of the fail information by issuing the write request command data and the read request command data described with reference to FIGS. You can do it. With such a configuration, reading and writing of fail information can be performed efficiently and accurately.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 ... Control system, 12 ... Control part, 20 ... Data transmission part, 30 ... Interface part, 32 ... Common controller, 34 ... Common buffer, 36 ... Distribution part 38 ... Individual buffer, 40 ... Individual controller, 50 ... Operation unit, 52 ... Distribution processing unit, 54 ... Abnormality determination unit, 56 ... Individual transmission unit, 58 ... Data processing unit 60 ... Data reception unit 62 ... Common transmission unit 64 ... Header information storage unit 66 ... Header transmission / reception unit 68 ... Data separation unit 70 ... Data combining unit, 72... Simulated operation unit, 100... Processing system, 200... Testing device, 210. .Fail memory, 300 ... Device under test

Claims (8)

A processing system for processing instruction data generated in parallel,
A plurality of control units each generating the instruction data;
An operation unit that operates according to the given instruction data;
In the command data to be transmitted to the operation unit, a header information storage unit that stores header information indicating which control unit in the plurality of control units is generated;
The header information is transmitted to the operation unit by excluding the header information stored in the header information storage unit from the command data generated by the plurality of control units, and the header information is received in the operation result data received from the operation unit. A processing system comprising: an interface unit that adds the header information stored in the storage unit and transmits the header information to the control unit. The processing system according to claim 1, wherein a communication speed from the control unit to the interface unit is faster than a communication speed from the interface unit to the operation unit. 3. The process according to claim 2, wherein each of the plurality of control units does not generate the other instruction data when receiving predetermined operation data until receiving the operation result data of the operation unit for the instruction data. system. The header information storage unit stores the header information for the predetermined instruction data;
The operation unit attaches predetermined identification data to the operation result data for the predetermined command data and transmits the operation result data to the interface unit,
The interface unit adds the header information stored by the header information storage unit to the operation result data when the predetermined identification data is attached to the operation result data received from the operation unit, The processing system according to claim 3, wherein the processing system is transmitted to the control unit. The processing system according to claim 3, wherein the header information storage unit has an area in which the header information corresponding to the number of the control units can be stored. The operation unit outputs the operation result data corresponding to the order in which the instruction data is received,
The processing system according to claim 5, wherein the interface unit reads the header information in the order stored in the header information storage unit, and sequentially adds the header information to the operation result data received from the operation unit. The processing system according to any one of claims 1 to 6, wherein a plurality of combinations of the operation unit and the header information storage unit are provided in parallel. A test apparatus for testing a device under test,
The processing system according to any one of claims 1 to 7, wherein the instruction data used for testing the device under test is generated and processed in parallel.
A test apparatus comprising: a determination unit that determines whether the device under test is good or bad.

Images