JP2011061325A - Voltage-controlled oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage-controlled oscillation circuit capable of extracting a signal synchronized with a frequency of half-integer multiple of an injected signal, and being advantageous to a broadband operation. <P>SOLUTION: The voltage-controlled oscillation circuit is a ring oscillator type voltage controlled oscillation circuit, and has a plurality of unit cells (UC1-UC4). A differential signal of mutually opposite phase is inputted into each of the plurality of unit cells. A load resistance value in each of the plurality of unit cells is controlled by an external voltage (Vtune) to control a delay of the differential signal. Each of the plurality of unit cells has variable load circuits (Bu1 and Bu2) at a control terminal. The external voltage is applied to the variable load circuits. At least one (UC1) of the plurality of the unit cells has a switch (SW1) which is short-circuited between output terminals according to an input signal put from an input terminal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a voltage controlled oscillation circuit.

  In an oscillation circuit of a wireless communication circuit, a circuit using the resonance characteristics of an inductor (L) and a capacitor (C) is often used. By setting the Q value of the LC circuit high, it is possible to realize excellent performance with high frequency accuracy and low phase noise. In recent years, a configuration using an LC resonance circuit on an integrated circuit is often used.

  On the other hand, as the integrated circuit technology is miniaturized, the transistor circuit portion is reduced in area, whereas in the LC resonant circuit portion, the constant is determined, so the area cannot be reduced and the chip cost is limited. It is in a situation. Further, even in an LC resonance type circuit, for example, when a process of less than 0.1 μm is applied, it has become difficult to satisfy the phase noise specification of the system. For this reason, a ring-type oscillation circuit is attracting attention as a circuit technology that can replace the conventional oscillation circuit using an LC resonance circuit. Yes. For example, the following research results for improving the phase noise characteristics by injecting a synchronization signal have recently been reported.

  However, in the currently reported configuration, synchronization can be achieved only in a frequency band that is an integral multiple of the injection signal, and it is disadvantageous for wideband operation.

Kyoya Takano, et al. “4.8GHz CMOS Frequency Multiplier with Subharmonic Pulse-Injection Locking”, Proceeding of IEEE Asian Solid-State Circuits Conference, pp.336-339, 2007.

  The present invention provides a voltage-controlled oscillation circuit that can extract a signal synchronized at a frequency that is a half-integer multiple of an injection signal and is advantageous for wideband operation.

  A voltage-controlled oscillation circuit according to an aspect of the present invention includes a plurality of unit cells to which differential signals having opposite phases are input, and controls load resistance values in the plurality of unit cells by an external voltage. A ring oscillator type voltage controlled oscillation circuit for controlling a delay amount of the differential signal, wherein each of the unit cells includes a variable load circuit to which the external voltage is applied to a control terminal. At least one includes a switch that short-circuits between output terminals by an input signal injected from the input terminal.

  According to the present invention, it is possible to obtain a voltage-controlled oscillation circuit that can extract a signal synchronized at a frequency that is a half-integer multiple of the injection signal and that is advantageous for wideband operation.

1 is a block diagram showing an example of the overall configuration of a voltage controlled oscillation circuit according to an outline of the present invention. The timing chart figure which shows the oscillation operation of the voltage control oscillation circuit which relates to the summary of this invention. 1 is a block diagram showing a configuration example of a voltage controlled oscillation circuit according to a first embodiment of the present invention. The equivalent circuit diagram which shows the unit cell which the voltage controlled oscillation circuit which concerns on 1st Embodiment has. FIG. 3 is an equivalent circuit diagram illustrating a bias generation circuit included in the voltage controlled oscillation circuit according to the first embodiment. The figure which shows the example of the oscillation frequency control of the voltage control oscillation circuit which concerns on 1st Embodiment. FIG. 3 is a layout diagram illustrating an example of a chip of a prototype circuit of the voltage controlled oscillation circuit according to the first embodiment. The figure which shows the oscillating operation (in the case of injection signal 80MHz) of the voltage controlled oscillation circuit which concerns on 1st Embodiment. The figure which shows the oscillating operation (in the case of injection signal 200MHz) of the voltage controlled oscillation circuit which concerns on 1st Embodiment. The figure which shows the oscillating operation (in the case of the injection signal 800MHz) of the voltage controlled oscillation circuit which concerns on 1st Embodiment. The figure which shows the improvement effect of the phase noise characteristic of the voltage controlled oscillation circuit which concerns on 1st Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

[Overview]
The outline of the voltage controlled oscillation circuit of the present invention will be described with reference to FIGS.
<Example of overall configuration>
First, an overall configuration example of the voltage controlled oscillation circuit according to the outline will be described with reference to FIG.
As shown in the figure, the voltage controlled oscillation circuit according to this example is a ring oscillator type (hereinafter referred to as a ring type) oscillation circuit (Ring VCO), and includes an injection signal pulse input terminal (Injection) and an output terminal (Output). , And an oscillation frequency tuning pin (Frequency Tuning).

  An injection signal with a low phase noise having a pulse frequency fref is injected into the injection signal pulse input terminal (Injection) from, for example, a pulse generation circuit or the like (not shown).

  From the output terminal (Output), take out the signal of low phase noise that is synchronized with the half-integer multiple frequency (for example, fo = fref × 1.5) in addition to the general integer multiple of the repetition frequency fref of the injection pulse signal. Can do.

  A tuning voltage Vtune as an external voltage is applied to the tuning terminal (Frequency Tuning). By controlling this tuning voltage Vtune, it is possible to control the load resistance of the inverter circuit of the unit cell in the ring-type voltage controlled oscillation circuit (Ring VCO), and the delay time varies depending on the load resistance value and the time constant of the load capacitance. The oscillation frequency can be varied over a wide band.

<Oscillation operation>
Next, an example of the oscillation operation of the voltage controlled oscillation circuit according to the outline will be described with reference to FIG.
As shown by the solid line in (a), the output terminal (Output) has a frequency fo, and when an injection pulse signal is injected with respect to a free oscillation signal (Free running), the phase shifts and the injection pulse An output signal fo synchronized with the signal is oscillated.

(B) shows an example of a change in the phase shift amount of the output signal when the phase of the injection pulse is shifted.
(C) shows an example of an operation waveform of a free oscillation signal (Free running).
(D) shows a waveform example of the injection pulse signal when the output frequency fo is an integral multiple (× 1 time, fo = fref) of the frequency fref of the injection pulse signal (injected pulse).

  In (e), the waveform example of the injection pulse signal when the output frequency fo is a half integer multiple (× 1.5 times, fo = 1.5 × fref) of the frequency fref of the injection pulse signal (injected pulse). Is shown.

<Effect>
According to the above configuration and oscillation operation, at least the following effects (I) and (II) can be obtained.
(I) A signal with low phase noise synchronized with a frequency that is an integral multiple and a half integer multiple of the repetition frequency of the injection pulse signal can be extracted. Therefore, it is possible to obtain twice the frequency resolution as compared with the integer multiple circuit. For example, for the repetition frequency fref of the injected pulse signal (injected pulse) in FIG. 2D, a low phase noise signal synchronized with a frequency (fo = fref) that is an integral multiple (× 1) is extracted. In addition, for the repetition frequency fref of the injected pulse signal (injected pulse) in FIG. 2 (e), a low phase synchronized with a frequency (fo = 1.5 × fref) of a half integer multiple (× 1.5 times) It has been shown that noise signals can be extracted.

  In addition, since it can operate not only in integer multiples but also in half integer multiples, a higher injection locking signal can be used, and phase noise can be kept lower compared to integer multiple operation circuits having the same frequency resolution. There is also an advantage of being able to.

  (II) By controlling the frequency tuning terminal voltage Vtune, it is possible to obtain a signal output in an integer multiple and half integer multiple frequency band within a wide frequency range. Details will be described later.

  Therefore, it is possible to obtain a voltage-controlled oscillation circuit that can extract a signal synchronized at a frequency that is a half-integer multiple of the injection signal and is advantageous for wideband operation.

[First Embodiment (an example of a ring-type voltage controlled oscillation circuit)]
Next, the voltage controlled oscillation circuit according to the first embodiment will be described with reference to FIGS. This embodiment relates to an injection locked broadband low phase noise ring voltage controlled oscillator circuit. In this description, detailed description of portions overlapping with the above description is omitted.

<1. Configuration example>
1-1. Configuration Example of Ring-Type Voltage Control Oscillation Circuit First, a configuration example of the voltage control oscillation circuit according to the first embodiment will be described with reference to FIG.
As shown in the figure, the voltage-controlled oscillation circuit according to this example includes a bias generation circuit 11 and four-stage unit cells UC1 to UC4 (differential circuits) to which differential signals having opposite phases are input. This is a ring oscillator type voltage controlled oscillation circuit that controls the amount of delay of the differential signal by controlling the voltage applied to the four unit cells UC1 to UC4 by (Vtune).

  The pulse generation circuit 12 generates an injection pulse signal of the input voltage Vinj, and the generated injection pulse signal is given to an injection signal pulse input terminal (Injection).

  The bias generation circuit 11 generates a bias control voltage Vc applied to the four unit cells UC1 to UC4 from an external voltage (hereinafter referred to as tuning voltage) Vtune applied from the outside.

  Each of the unit cells UC1 to UC4 is provided with a tuning voltage Vtune and a control voltage Vc at a control terminal, and differential signals having opposite phases are input to each other, and four stages are connected in a ring shape. It is a configuration. Of the four unit cells UC1 to UC4, one unit cell UC1 has a switch SW1, and an injection signal (Vinj) is injected through the switch SW1. Therefore, the injection locking operation can be stabilized.

  The injection signal (Vinj) is input from an injection signal pulse input terminal (Injection). When injected, when the pulse signal is at “H (High)” level, the output terminals (I1, / I1) of the unit cell (differential circuit) UC1 are short-circuited by the switch SW1 to efficiently input the signal. To do. In this way, by the injection circuit configuration in which the output terminals (I1, / I1) are short-circuited by the switch SW1, synchronization by injection locking of a half integer multiple (l / 2 (l = 2, 3, 4,...)) Is performed. Is possible.

1-2. Configuration Example of Unit Cell (UC1) Next, a configuration example of the unit cell according to the first embodiment will be described with reference to FIG. Here, unit cell UC1 is taken as an example.
As shown in the figure, the unit cell UC1 includes inverter circuits IN1 and IN2 that constitute variable load circuits Bu1 and Bu2, transistors Tr1 and Tr2 that operate in triode, transistors P31 and P32, a switch SW1, and transistors N51, N52, and N60.

  The inverter circuits IN1, IN2 are configured by transistors P11 to N12. One end of the current path of the p-type transistors P11 and P12 is connected to the internal power supply voltage Vdd. One end of the current path of the n-type transistors N11 and N12 is connected to the other end of the current path of the transistors P11 and P12, the other end of the current path is connected to the ground power supply voltage, and the control terminals (gate terminals) are transistors P11 and P12. And a tuning voltage Vtune are applied in common.

  The transistors Tr1 and Tr2 that operate as triodes are configured as p-type transistors P21 and P22. One end of the current path of the transistors P21 and P22 is connected to the internal power supply voltage Vdd, the other end is connected to the outputs of the inverter circuits IN1 and IN2, and the control terminal (gate terminal) is connected to the ground power supply voltage to perform triode operation. Realized.

  One end of the current path of the transistors P31 and P32 is connected to the internal power supply voltage Vdd, the other end is connected to the outputs of the inverter circuits IN1 and IN2, and the control terminal is connected to cross the other end of the other current path. .

  The switch SW1 is composed of n-type transistors N41 and N42. One end and the other end of the current paths of the transistors N41 and N42 are connected to the output terminals (I1, / I1), and the input voltage Vinj is applied to the control terminal (gate terminal) from the input terminal (Injection).

  One end of the current path of the transistor pair N51 and N52 constituting the differential amplifier is connected to one end and the other end of the switch SW1, and the control terminal (gate terminal) is connected to the output terminals (I1, / I1).

One end of the current path of the transistor N60 is connected to the other end of the current paths of the transistors N51 and N52, the other end of the current path is connected to the ground power supply voltage, and a control voltage Vc is applied to the control terminal (gate terminal).
The configuration of the other unit cells UC2 to UC4 is the same as that of the unit cell UC1 except for the switch SW1.

1-3. Configuration Example of Bias Generation Circuit 11 Next, a configuration example of the bias generation circuit according to the first embodiment will be described with reference to FIG. As illustrated, the bias generation circuit includes an inverter circuit IN21 and transistors P72, P73, P81, and N81.
The inverter circuit IN21 is composed of transistors P71 and N71. One end of the current path of the p-type transistor P71 is connected to the internal power supply voltage Vdd. One end of the current path of the n-type transistor N71 is connected to the other end of the current path of the transistor P71, the other end of the current path is connected to the ground power supply voltage, and a control terminal (gate terminal) is a control terminal of the transistors P71 and N72 ( The tuning voltage Vtune is applied in common with the gate terminal.

  One end of the current path of the p-type transistor P72 is connected to the internal power supply voltage Vdd, and a voltage Vdd / 2 that is half the internal power supply voltage is applied to the control terminal (gate terminal). One end of the current path of the p-type transistor P73 is connected to the other end of the transistor P72, and a voltage Vdd / 2 is applied to the control terminal (gate terminal).

  One end of the current path of the transistor P81 is connected to the internal power supply voltage Vdd, the other end is connected to the output of the inverter IN21, and a ground power supply voltage is applied to the control terminal (gate terminal). One end of the current path of the transistor N81 is connected to the other end of the current path of the transistor P73, the other end is connected to the ground power supply voltage, and the output of the inverter IN21 is connected to the control terminal (gate terminal) to the unit cells UC1 to UC4. A control voltage Vc is output.

<2. Operation>
2-1. Example of Oscillation Frequency Control Using Tuning Voltage Vtune Next, oscillation frequency control using the tuning voltage Vtune according to the first embodiment will be described with reference to FIG. FIG. 6 shows the relationship between the output frequency (Oscillation Freq.) At the output terminals (here, Q2, / Q2) and the tuning voltage Vtune.

  The solid line FV in the figure is a characteristic line when the bias control voltage Vc is fixed at 0.85 V (With fixed voltage of 0.85 V), and the solid line RV is bias control via the circuit shown in FIG. 5 by the tuning voltage Vtune. This is a characteristic line when the voltage Vc is changed (With replica bias).

As shown in the figure, it can be seen that the oscillation frequency can be greatly changed by changing the tuning voltage Vtune from 0V to 1.8V. The characteristic by the solid line FV is obtained by controlling the load resistance values of Bu1 and Bu2 in the circuit diagram of FIG. 4 by the Vtune control terminal voltage. When the Vtune voltage is low, the load resistance value is reduced to enable oscillation at a high frequency, and as the Vtune voltage is increased, the load resistance value is increased and the oscillation frequency is decreased.
The characteristic of the solid line RV enables oscillation to a lower frequency region by simultaneously changing the bias voltage Vc through the bias generation circuit shown in FIG. 5 in order to realize a wider band operation. In the circuit of FIG. 5, since the bias terminal voltage Vc is also reduced when the Vtune control terminal voltage is lowered, the current of the differential pair circuit of the transistors N51 and N52 in FIG. By keeping it low, a higher load resistance value can be set. For this reason, in this configuration, wide-band oscillation operation is enabled by simultaneously controlling the load resistance value by Vtune and the bias voltage Vc.

2-2. Oscillation operation
Next, the oscillation operation of the voltage controlled oscillation circuit according to the first embodiment will be described with reference to FIGS. The inventor of the present application prototyped and evaluated a chip as shown in FIG. 7 using a 180 nm CMOS process, and obtained the following results. The voltage controlled oscillation circuit according to the present example is arranged in a portion denoted by “Core” in the drawing. Note that buffer circuits (Buffers) for the following measurement are arranged in the portions denoted by (BF1, BF2) in the figure.

Injection signal: 80 MHz
The oscillation frequency (Free running) of the ring type voltage oscillation circuit when the reference signal indicated by the broken line in FIG. 8 is not input is about 1.0 GHz to 2.2 GHz, and an 80 MHz signal is supplied to the ring type voltage oscillation circuit. The oscillation frequency in the case of injecting is indicated by a solid line. As shown in the figure, it can be seen that an output signal synchronized with the frequency of a half integer multiple (for example, 80M × 24, 80M × 23.5, 80M × 23, 80M × 22,...) Is obtained.

Injection signal: 200 MHz
The oscillation frequency (Free running) of the ring type voltage oscillation circuit when the reference signal indicated by the broken line in FIG. 9 is not input is about 1.0 GHz to 2.2 GHz, and a 200 MHz signal is supplied to the ring type voltage oscillation circuit. The oscillation frequency in the case of injecting is indicated by a solid line. As shown in the figure, it is understood that an output signal synchronized with a frequency of a half integer multiple (for example, 200M × 10, 200M × 9.5, 200M × 9, 200M × 8.5,...) Is obtained.

Injection signal: 800MHz
The oscillation frequency (Free running) of the ring type voltage oscillation circuit when the reference signal indicated by the broken line in FIG. 10 is not input is about 1.0 GHz to 2.2 GHz, and an 800 MHz signal is supplied to the ring type voltage oscillation circuit. The oscillation frequency in the case of injecting is indicated by a solid line. As shown in the figure, it can be seen that an output signal synchronized with a frequency of a half integer multiple (for example, 800M × 2.5, 800M × 2, 800M × 1.5...) Is obtained.
Thus, according to the ring-type voltage oscillation circuit according to this example, a signal synchronized with a half-integer multiple frequency can be extracted.

2-3. Improvement effect of phase noise characteristics
Next, the effect of improving the phase noise characteristics of the voltage controlled oscillation circuit according to the first embodiment will be described with reference to FIG. FIG. 11 shows the results of evaluating the phase noise characteristics when 40 MHz and 80 MHz pulse signals are injected.

As shown in the figure, the phase noise at 1 MHz detuning is −100 dBc / Hz when there is no injection signal. However, by injecting a pulse signal (fref) with good phase noise characteristics into the switch SW1, when a 40 MHz signal with a pulse width of 250 ps is input, an 80 MHz signal with -121 dBc / Hz and a pulse width of 250 ps is injected. From time to time, it can be seen that significant phase noise characteristics of -127 dBc / Hz and 20 dB or more can be improved. As described above, the circuit configuration in which the pulse signal is injected into the switch SW1 succeeds in reducing the phase noise of the ring oscillator type voltage controlled oscillation circuit which is said to have essentially large phase noise characteristics.
<3. Effect>
According to the voltage controlled oscillation circuit of this embodiment, at least the following effects (1) to (4) can be obtained.
(1) A signal synchronized with a frequency that is a half integer multiple of the injection signal can be taken out, and is advantageous for wideband operation.

The voltage controlled oscillation circuit according to this example includes a plurality of unit cells (UC1 to UC4) to which differential signals having opposite phases are input, and the load resistance values in the plurality of unit cells are determined by an external voltage (Vtune). This is a ring oscillator type voltage controlled oscillation circuit that controls the delay amount of the differential signal by controlling. further,
Each of the unit cells UC1 to UC4 includes variable load circuits Bu1 and Bu2 to which an external voltage Vtune is applied to a control terminal, and at least one of the plurality of unit cells (UC1) is output by an input signal Vinj injected from the input terminal. A switch SW1 for short-circuiting between the terminals (I1, / I1) is provided.
As described above, at least one of the plurality of unit cells (UC1) includes the switch SW1 in which the output terminals (I1, / I1) are short-circuited by the input signal Vinj injected from the input terminal. Therefore, when the input signal (Vinj) injected is, for example, at the “H (High)” level, the output terminals (I1, / I1) of the unit cell UC1 are short-circuited by the switch SW1, and the signal is input efficiently. In other words, it is possible to obtain an output signal in injection locking of a half integer multiple (l / 2 (l = 2, 3, 4,...)) (For example, FIGS. 8 to 10).
In addition, each of the unit cells UC1 to UC4 includes variable load circuits Bu1 and Bu2 that are supplied with an external voltage Vtune at their control terminals. Therefore, the load resistance value in the plurality of unit cells (UC1 to UC4) can be controlled by the external voltage (Vtune), and the delay amount of the differential signal can be controlled. For example, as shown in FIG. 6, the variable resistances of the unit cells UC1 to UC4 in the voltage controlled oscillation circuit (VCO) can be controlled by controlling the tuning voltage Vtune from a fixed value by a predetermined value. Therefore, the delay time at the output terminals (Q2, / Q2) of the voltage controlled oscillation circuit can be changed to vary the oscillation frequency over a wide band.
As described above, according to the configuration and operation of the voltage controlled oscillation circuit according to this example, it is possible to extract a signal synchronized at a frequency that is a half integer multiple of the injection signal, and it is advantageous for wideband operation.

(2) It is advantageous for miniaturization and reduction of manufacturing cost.
As described above, the voltage controlled oscillation circuit according to the present example is a ring oscillator type, and is not an LC resonance type voltage controlled oscillation circuit using the resonance characteristics of the inductor (L) and the capacitance (C). Here, in the LC resonance type voltage controlled oscillation circuit, since the constant of the LC resonance circuit unit is determined, the area cannot be reduced, and the chip cost is limited.
However, in this example, since it is a ring oscillator type, the inductor (L) and the capacitance (C) are unnecessary, which is advantageous for miniaturization and reduction of manufacturing cost. For example, in the fine CMOS technology region of less than 0.1 μm, it is considered that there is a high possibility of replacing the LC resonance type voltage controlled oscillation circuit.

(3) Phase noise characteristics can be reduced.
In this example, the phase noise of the ring oscillator type voltage controlled oscillation circuit, which is said to have essentially high phase noise characteristics, can be reduced by the circuit configuration in which the pulse signal is injected into the switch SW1.
For example, as shown in FIG. 11, when a 40 MHz signal with a pulse width of 250 ps is input by injecting a pulse signal into the switch SW1, an 80 MHz signal with -121 dBc / Hz and a pulse width of 250 ps is injected. From time to time, it can be seen that significant phase noise characteristics of -127 dBc / Hz and 20 dB or more can be improved.

(4) Application to other conversion circuits such as a frequency multiplier is easy.
By mounting the voltage controlled oscillation circuit according to this example, it is advantageous in that application to a frequency multiplication circuit, a frequency conversion circuit, a frequency synthesizer circuit, and the like is easy.

  The present invention has been described above using the outline and the first embodiment. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention at the stage of implementation. It is possible. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When at least one of the effects is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

DESCRIPTION OF SYMBOLS 11 ... Bias generation circuit, 12 ... Pulse generation circuit, unit cell (differential circuit) ... UC1-UC4, SW1 ... Switch, external voltage ... Vtune, control voltage ... Vc, Bu1, Bu2 ... Variable load circuit, In1, In2 ... Inverter circuit, Tr1, Tr2 ... Triode operation transistor.

Claims (6)

A ring oscillator having a plurality of unit cells to which differential signals having opposite phases to each other are input, and controlling a load resistance value in the plurality of unit cells by an external voltage, thereby controlling a delay amount of the differential signals. Type voltage controlled oscillator circuit,
Each of the unit cells includes a variable load circuit to which the external voltage is applied to a control terminal,
At least one of the plurality of unit cells includes a switch in which an output terminal is short-circuited by an input signal injected from an input terminal. The voltage controlled oscillation circuit according to claim 1, further comprising a bias generation circuit that generates a bias voltage to be applied to the plurality of unit cells from the external voltage. The variable load circuit includes an inverter circuit to which the external voltage is applied to a control terminal, and a transistor that performs a triode operation in which one end of a current path is connected to a first power supply voltage and the other end is connected to an output of the inverter circuit. The voltage controlled oscillation circuit according to claim 1, further comprising: The plurality of unit cells further include a first transistor in which one end of a current path is connected to a second power supply voltage, the other end is connected to a transistor pair constituting a differential amplifier, and the bias voltage is applied to a control terminal. The voltage controlled oscillation circuit according to claim 2 or 3, wherein 5. The switch according to claim 1, wherein the switch oscillates an output signal in a half-integer multiple injection locked state by a circuit configuration in which the output terminals are short-circuited when the input signal is at the “first” level. Any one of the voltage controlled oscillation circuits. 6. The switch according to claim 5, wherein the switch includes second and third transistors in which one end and the other end of a current path are connected to the output terminal, and an input voltage from the input terminal is applied to a control terminal. Voltage controlled oscillator circuit.

Images