JP2011055164A - Configuration device, configuration method and configuration program - Google Patents

Abstract

A configuration device capable of efficiently configuring a logic circuit is provided.
Formal configuration data 112 comprising test configuration data 111 for constructing a test logic circuit in each of a plurality of FPGAs included in an FPGA unit 200 and a plurality of formal device data 112a. A data holding unit 110 that holds a logic circuit, a configuration control unit 120 that builds a logic circuit in a plurality of FPGAs, and an input / output characteristic between a plurality of FPGAs in which an electronic circuit is built using test device data. A configuration selection unit 130 for extracting specific device data from the test device data, and the configuration control unit 120 uses a plurality of formal device data 112a associated with the extracted test device data 111a to Logic circuit in FPGA It is built.
[Selection] Figure 1

Description

  The present invention relates to a configuration device, a configuration method, and a configuration program for configuring a logic circuit in, for example, an FPGA (Field Programmable Gate Array).

  Conventionally, when optimizing input / output characteristics between two FPGAs connected to each other, a logic circuit for a product is constructed for each FPGA by configuration, and an actual signal waveform is measured. The output characteristics were confirmed. For this reason, when the input / output characteristics are unsatisfactory, the configuration data has been corrected. However, since the configuration data correction work is manually performed on the computer, data to be deleted may remain or data to be deleted may be deleted. As a result, even if configuration is performed using the modified configuration data, appropriate input / output characteristics cannot be obtained, and as a result, efficient configuration cannot be performed.

As a conventional configuration apparatus, there is a technique for changing a termination voltage applied to a termination resistor in an FPGA according to the output level of the FPGA (for example, see Patent Document 1).
JP 2006-337387 A

  The present invention provides a configuration device, a configuration method, and a configuration program capable of efficiently configuring a logic circuit.

  The configuration device disclosed in the present application constructs a logic circuit on a trial basis using test configuration data for the test for building a logic circuit on an electronic component and a formal corresponding uniquely for the test. Select the best formal configuration data.

  According to the present invention, it is possible to efficiently configure a logic circuit.

1 is a block diagram of a configuration device according to a first embodiment. 1 is a block diagram of an FPGA in which a test logic circuit according to a first embodiment is constructed. Schematic diagram of the correspondence table according to the first embodiment Configuration flowchart according to the first embodiment Explanatory drawing which shows the waveform figure of the test signal confirmed by the test signal confirmation part of the configuration apparatus which concerns on 1st Embodiment, and a test signal example Block diagram of a configuration device according to the second embodiment Explanatory drawing of the test result of the configuration apparatus which concerns on 2nd Embodiment Explanatory drawing of the board of the circuit configuration apparatus which concerns on 2nd Embodiment Block diagram of a circuit configuration device according to the second embodiment Block diagram of the configuration control unit of the circuit configuration device according to the third embodiment Explanatory drawing of the configuration of the circuit configuration apparatus according to the third embodiment

(First embodiment)
The configuration device according to the first embodiment will be described below with reference to FIGS.
1 is a block diagram of a configuration apparatus according to the first embodiment, FIG. 2 is a block diagram of an FPGA in which a test logic circuit according to the first embodiment is constructed, and FIG. 3 is a block diagram of the first embodiment. It is the schematic of such a correspondence table.

As shown in FIG. 1, the configuration apparatus 100 according to the present embodiment configures a plurality of FPGAs included in the FPGA unit 200. Each FPGA included in the FPGA unit 200 is mounted on the substrate 210, and is connected to another FPGA through wiring (not shown) formed on the substrate 210, as will be described later.
The configuration device 100 includes a data holding unit 110, a configuration control unit 120, and a configuration data selection unit 130.

  The data holding unit 110 includes a plurality of test configuration data 111 for constructing a test logic circuit in the FPGA and a plurality of formal configuration data 112 for constructing a formal logic circuit in the FPGA. Hold.

  The test logic circuit is a logic circuit constructed to confirm input / output characteristics between two FPGAs connected to each other before constructing a formal logic circuit in the FPGA. The official logic circuit is a logic circuit built in the FPGA when the FPGA is used in a product or the like.

  The number of test configuration data 111 and the number of formal configuration data 112 are the same, and are associated one-to-one with each other by a characteristic table (correspondence table) described later. In the present embodiment, as shown in FIG. 1, the number of test configuration data 111 and the number of formal configuration data 112 is three each, but it is naturally limited to three. is not.

  Each of the test configuration data 111 includes a plurality of test device data 111 a for individually configuring a plurality of FPGAs included in the FPGA unit 200. As a result, when the configuration using the arbitrary test configuration data 111 is performed, a plurality of FPGAs included in the FPGA unit 200 are simultaneously configured by the respective test device data 111a.

  Each of the formal configuration data 112 includes a plurality of formal device data 112 a for individually configuring a plurality of FPGAs included in the FPGA unit 200. As a result, when configuration is performed using arbitrary formal configuration data 112, a plurality of FPGAs included in the FPGA unit 200 are simultaneously configured by the respective formal device data 112a.

  FIG. 2 is a block diagram of the FPGA in which the test logic circuit according to the first embodiment is constructed. In FIG. 2, the symbol d indicates the drive capability set on the output side of the test signal generation unit 200a, and the symbol r indicates the termination resistor set on the input side of the test signal confirmation unit 200b.

  As shown in FIG. 2, the FPGA in which the test logic circuit is constructed has a buffer for changing the driving capability on the output side of the test signal generation unit 200a, and on the input side of the test signal confirmation unit 200b. , Has a buffer for changing the termination resistance. Although a buffer is used here, it is not limited as long as it is a termination resistor.

  FIG. 3 is a schematic diagram of a correspondence table according to the first embodiment. Although not shown, this correspondence table is arranged in the data holding unit 110. FIG. 3 shows a set of test configuration data 111 and formal configuration data 112 that are associated with each other. The parentheses (d, r) in the figure indicate the drive capability and termination resistance of the logic circuit constructed in each FPGA as (drive capability, termination resistance).

  As shown in FIG. 3, in the test configuration data 111 and the formal configuration data 112 that are associated with each other, the driving capability and termination resistance of the logic circuit constructed in the FPGA by each test device data 111a, The drive capability and termination resistance of the logic circuit constructed in the FPGA by each formal device data 112a have the same value.

  Therefore, both when the configuration is performed with the arbitrary test configuration data 111 and when the configuration with the formal configuration data 112 corresponding thereto is performed, the drive capability and termination of the logic circuit constructed in each FPGA The resistance has the same value.

  By the way, the input / output characteristics between two FPGAs connected to each other are determined by the driving capability of the output-side FPGA and the termination resistance of the input-side FPGA. Therefore, the input / output characteristics between the two FPGAs connected to each other are the same both when the configuration using the test configuration data 111 is performed and when the configuration using the corresponding formal configuration data 112 is performed. Should be.

  Therefore, if the test configuration data 111 that can obtain the optimum input / output characteristics can be specified, the optimum input / output characteristics can be obtained even in the formal logic circuit by using the corresponding formal configuration data 112. Will be.

  The configuration control unit 120 reads the test configuration data 111 from the data holding unit 110, and simultaneously configures a plurality of FPGAs based on the test device data 111a of the read test configuration data 111.

  The configuration control unit 120 reads the formal configuration data 112 from the data holding unit 110, and configures a plurality of FPGAs simultaneously based on the formal device data 112a of the read formal configuration data 112.

  When the configuration using the test configuration data 111 is performed, the test signal generation unit 200a and the test signal confirmation unit 200b are constructed in the FPGA. The test signal generation unit 200a and the test signal confirmation unit 200b are separate circuit areas included in the test logic circuit.

  The FPGA test signal generation unit 200a is connected to another FPGA test signal confirmation unit 200b through wiring (not shown) formed on the substrate 210, for example. By chaining such connections between FPGAs, all the FPGAs are connected in a loop as shown by the arrows in FIG.

  The test signal generation unit 200 a generates a test signal based on, for example, a clock signal input from the outside, and outputs the test signal to another FPGA through the wiring of the substrate 210. For example, a pulse signal may be used as the test signal. The test signal confirmation unit 200b receives the test signal output from the test signal generation unit 200a, and digitizes the input / output characteristics between the two FPGAs connected to each other based on the waveform of the test signal. The input / output characteristics digitized by the test signal generation unit 200b are output to the configuration data selection unit 130.

  The configuration data selection unit 130 determines the optimum input / output characteristic from the plurality of input / output characteristics input from the test signal confirmation units 200b of the plurality of FPGAs, and obtains the optimum input / output characteristic. Identification data 111 is specified. Further, the configuration data selection unit 130 uses the characteristic table to determine the formal configuration data 112 associated with the test configuration data 111 from which the optimum input / output characteristics can be obtained. Data 112 is output to the configuration control unit 120.

Next, the configuration according to the present embodiment will be described with reference to FIG.
FIG. 4 is a flowchart of the configuration according to the first embodiment. As shown in FIG. 4, the data holding unit 110 stores a plurality of test configuration data 111 and a plurality of formal configuration data 112 in advance.

  First, when the configuration device 100 is activated (step S1), the configuration control unit 120 reads the test configuration data 111 that has not been tested from the data holding unit 110 (step S2). The configuration control unit 120 performs configuration on all the FPGAs included in the FPGA unit 200 based on the read test configuration data 111 (step S3). Thereby, a test signal generation unit 200a and a test signal confirmation unit 200b as logic circuits are constructed in all the FPGAs included in the FPGA unit 200.

  Next, the test signal generation unit 200a of each FPGA included in the FPGA unit 200 generates a test signal such as a pulse waveform based on a clock input from the outside, and the test signal is formed on the substrate 210. It outputs to wiring (not shown) (step S4). The test signal confirming unit 200b of each FPGA included in the FPGA unit 200 receives the test signal output from the test signal generating unit 200a, and inputs between the two FPGAs connected to each other based on the waveform of the test signal. The output characteristics are digitized, and the digitized input / output characteristics are output to the configuration data selection unit 130 (step S5). Thus, the input / output characteristic test using one test configuration data 111 is completed.

  When the test of the input / output characteristics using one test configuration data 111 is completed, the configuration control unit 120 tests the input / output characteristics using all the test configuration data 111 held in the data holding unit 110. It is confirmed whether or not is completed (step S6). Here, when there is test configuration data 111 that has not been tested, the configuration control unit 120 repeats the processing from step S2 to step S5.

  On the other hand, when there is no test configuration data 111 that has not been tested, the configuration data selection unit 130 determines an optimal input / output characteristic from a plurality of input / output characteristics input from the test signal confirmation unit 200b of each FPGA. Then, the test configuration data 111 from which the optimum input / output characteristics are obtained is specified, and the test configuration data 111 is output to the configuration control unit 120 (step S7). Note that an identification number may be assigned to the test configuration data, and the identification number may be output to the configuration control unit 120.

  Next, the configuration control unit 120 refers to the correspondence table to determine the formal configuration data 112 associated with the test configuration data 111 input from the configuration data selection unit 130, and the data holding unit 110. The formal configuration data 112 is extracted from the configuration data, and the configuration using the formal configuration data is performed (step S8). As described above, a formal logic circuit is constructed in each FPGA included in the FPGA unit 200.

  Next, digitization of input / output characteristics by the test signal confirmation unit 200b will be described with reference to FIG. FIG. 5A is a waveform diagram of a test signal confirmed by the test signal confirmation unit 200b according to the first embodiment. Here, a pulse signal is adopted as the test signal.

  As shown in FIG. 5A, the test signal input from the test signal generation unit 200a to the test signal confirmation unit 200b has various waveforms A, B, and C according to input / output characteristics. The test signal confirmation unit 200b of each FPGA detects the length of the H (High) section of the waveform of the test signal. The configuration data selection unit 130 compares the lengths of a plurality of H sections input from the test signal confirmation unit 200b, and when the H section is the longest, that is, the rising edge of the test signal waveform is the sharpest. In this case, the input / output characteristics between the FPGAs connected to each other are determined to be optimal.

  In the present embodiment, a pulse signal is used as the test signal. However, for example, a PN (Positive-Negative) pattern as shown in FIG. 5B may be used. When the PN pattern is used, the test signal confirmation unit 200b detects the aperture ratio of the test signal waveform. The aperture ratio is the ratio (H / L ratio) between the H (High) section and the L (Low) section in the waveform of the test signal. The configuration data selection unit 130 determines that the input / output characteristics between the FPGAs connected to each other are optimal when the aperture ratio is closest to 50% based on the plurality of aperture ratios input from the test signal confirmation unit 100b. To do.

  Similarly, for example, specific data as shown in FIG. 5C may be used. When using specific data, the received data and the expected value are collated, and a waveform that is an intermediate value of the IO characteristic when the received data matches the expected value is selected. Note that the three types of methods described above may be combined. For example, the final value may be determined by measuring a waveform having an aperture ratio closest to 50% in the vicinity of a value obtained by measuring specific data.

  According to the present embodiment, the test configuration data 111 and the formal configuration data 112 are prepared separately, and after performing the configuration using the test configuration data 111, optimal input / output characteristics can be obtained. The configuration is performed using the formal configuration data 112 corresponding to the test configuration data 111. For this reason, it is not necessary to rewrite the configuration data actually used, which has been conventionally performed, and as a result, a formal logic circuit can be efficiently constructed in the FPGA.

Also, in the above, a plurality of FPGAs included in the FPGA unit 200 are n, and even when the minimum number of FPGAs is two (n = 2), a sufficiently optimal logic circuit is constructed by following the above procedure. be able to.
Note that the hardware configuration of the configuration apparatus 100 according to the present embodiment includes a CPU, a memory, a storage device, an input device, and a bus connecting the above-described units.

(Second Embodiment)
Hereinafter, a configuration device according to the second embodiment will be described with reference to FIGS.
FIG. 6 is a block diagram of a configuration device according to the second embodiment, FIG. 7 is an explanatory diagram of test results of the configuration device according to the second embodiment, and FIG. 8 is a circuit configuration according to the second embodiment. The explanatory view of the board of an installation device is shown. FIG. 9 is a block diagram of a circuit configuration device according to the second embodiment.

  In FIG. 6, the configuration apparatus according to this embodiment includes a data holding unit 110, a configuration control unit 120, a configuration data selection unit 130, and an FPGA unit 200, as in the first embodiment. . Furthermore, in this embodiment, it is the structure provided with the suitability determination part 140 and the warning notification part 150. FIG. The suitability determination unit 140 determines the suitability of the configuration data using a threshold value with respect to the input / output characteristics determined by the configuration data selection unit 130. Further, the warning notification unit 150 notifies the user of a warning in the case of non-conforming configuration data based on the suitability determination unit 140.

Hereinafter, the operation of the configuration device according to the present embodiment based on the above configuration will be described with respect to the portions added to the first embodiment.
As shown in FIG. 4 describing the first embodiment, the configuration data selection unit 130 performs an optimum test when a test is performed using all the test configuration data in S7. Specify and output configuration data for

  In S7, the suitability determination unit 140 determines the suitability of the configuration data using a threshold value with respect to the input / output characteristics determined by the configuration data selection unit 130. For example, as shown in FIG. 5B, the suitability determination unit 140 has an aperture ratio (H / L ratio) of 10% or less or 90 when the test signal is a PN (positive-negative) pattern. It is also possible to determine a waveform that is at least% as an incompatible waveform.

  Further, the warning notification unit 150 notifies the user of a warning for the formal configuration data corresponding to the test configuration data from which the incompatible waveform is obtained based on the compatibility determination unit 140. . As shown in FIG. 7 (a), this warning notification can also be implemented by displaying a list of test configuration data together with the set drive capability and termination resistance on the terminal screen and displaying the test results. . As shown in FIG. 5B, this warning notification can also extract and display test results relating only to test configuration data for which an incompatible waveform was obtained.

  As described above, the user can recognize incompatible configuration data by this warning notification, and when the user re-creates the configuration data, the creation accuracy can be improved.

  In the above embodiment, the FPGA may include n connected FPGAs on one substrate 210 as shown in FIG. Further, as shown in FIG. 4B, the FPGA includes n-connected FPGAs per board in a plurality of boards (boards), for example, three boards 210A, 210B, and 210C, which are respectively separate boards. It can also be included in the base. The plurality of substrates is not limited to these three substrates and can be applied to two or more substrates.

  As described above, when a plurality of substrates 210 including n-connected FPGAs are provided, tests on a plurality of substrates (boards) can be performed collectively, and the test execution efficiency is improved by increasing the time efficiency of the test. be able to. In addition, since the configuration control unit 120 and the configuration data selection unit 130 are shared with each board, it is not necessary to mount each board, and the component mounting area in the board can be reduced. The scale can be reduced.

  Further, in the present embodiment, the configuration data selection unit 130 measures the input / output characteristics between the FPGA1, FPGA2,..., FPGAAn. The input / output characteristics at can also be measured. As described above, the connection between the substrates 210A, 210B, and 210C can be set to an optimum combination based on the measured input / output characteristics.

  In the present embodiment, the conformity determination unit 140 and the warning notification unit 150 are used to display only the non-conforming test configuration data to the user. The display unit 160 can also be used. As shown in FIG. 7A, the display unit 160 omits the selection of the test configuration data from which the non-conforming waveform is obtained by the suitability determining unit 140, and all the test configuration data related to the test configuration data. Display test results for. In this case, the user can recognize all the results of the test configuration data, and the accuracy of the test configuration data recreated by the user can be further improved.

In the present embodiment, a reset unit 170 that resets (stops) the inside of the board can be provided when the warning notification unit 150 notifies the warning. In this case, misuse of non-conforming configuration data can be prevented, and configuration data that reliably reflects the test execution result can be used.
(Third embodiment)
Hereinafter, a configuration device according to the third embodiment will be described with reference to FIGS. 10 and 11.

  FIG. 10 is a block diagram of a configuration device according to the third embodiment, and FIG. 11 is an explanatory diagram of the configuration of the configuration device according to the third embodiment.

  The configuration apparatus according to the present embodiment includes a data holding unit 110, a configuration control unit 120, a configuration data selection unit 130, and an FPGA unit 200, as in the first embodiment. Furthermore, in the present embodiment, as shown in FIG. 10A, the configuration control unit 120 includes a circuit extraction unit 121, a circuit analysis unit 122, a line characteristic specifying unit 123, and an impedance allocation unit 124. Prepare.

  As shown in FIG. 10B, the circuit extraction unit 121 extracts a set of FPGAs (FPGAs 1 and 2, FPGAs 2 and 3, and FPGAs (n−1) and n) that are directly connected to each other. The circuit analysis unit 122 analyzes the impedance between the FPGAs 1 and 2 (or FPGAs 2 and 3, FPGAs (n−1) and n) extracted by the circuit extraction unit 121. The resistance component that can be inserted into the is detected.

  As illustrated in FIG. 9, the circuit analysis unit 122 detects a connection form (topology) including a resistance component between the FPGAs 1 and 2. For example, the circuit analysis unit 122 detects a resistance component R1 inserted in series between the FPGAs 1 and 2 as shown in FIG. 9A, or as shown in FIG. In some cases, the resistance component R2 pulled up to the interface voltage is detected as a termination resistor. The circuit analysis unit 122 may detect the resistance component R1 and the resistance component R2 connected in series between the FPGAs 1 and 2, for example, as shown in FIG.

  In addition, the line characteristic specifying unit 123 extracts the circuits of the extracted FPGAs 1 and 2 (or FPGAs 2 and 3, FPGA (n−1) and n) based on the impedance analyzed by the circuit analysis unit 122. Specify the characteristics (line characteristics) related to the relay bus. In addition, the impedance allocating unit 124 uses either or one of the FPGAs 1 and 2 (or FPGAs 2 and 3, FPGA (n−1) and n) based on the line characteristics specified by the line characteristic specifying unit 123. The impedance analyzed by the circuit analysis unit 122 is assigned.

  For example, when the resistance component R1 in FIG. 11A is present, the impedance allocation unit 124 can allocate the resistance component R1 to the FPGA 2. Further, the impedance assigning unit 124 can assign the resistance component R2 to the FPGA 2, for example, when the resistance component R2 in FIG. In addition, for example, when the resistance components R1 and R2 in FIG. 5C exist, the impedance allocation unit 124 can allocate the resistance component R1 to the FPGA 1 and allocate the resistance component R2 to the FPGA2.

  The configuration control unit 120 considers, when selecting the configuration data for testing, the setting based on the optimum combination of current values that can realize the driving capability and the termination resistance in a pseudo manner for each FPGA by assigning the resistance component. can do. This configuration data selection unit 130 further improves test accuracy by preferentially adopting test configuration data that has obtained a test result close to the resistance component allocated to the impedance allocation unit 124 during testing. Can be made.

In the above description, the impedance is related to the resistance component. However, the impedance is not limited to this, and the impedance component may be a capacitance component or an inductor component.
In the above description, the circuit extraction unit 121 extracts FPGAs 1 and 2 (or FPGAs 2 and 3, FPGAs (n−1) and n). However, the circuit extraction unit 121 is not limited to this sequential order. For example, the FPGA 2 It is also possible to extract in a distant order, such as.

Hereinafter, the operation of the configuration device according to the present embodiment based on the above configuration will be described with respect to the portions added to the first embodiment.
As shown in FIG. 4 describing the first embodiment, the data holding unit 110 receives and holds a test signal and configuration data in S1. Here, the circuit extraction unit 121 extracts FPGAs directly connected to each other from the FPGA unit 200 with respect to generation of configuration data.

  The circuit analyzing unit 122 analyzes the FPGA extracted based on the circuit extracting unit 121 with respect to impedance. The line characteristic specifying unit 123 specifies the line characteristic between the extracted FPGAs based on the impedance analyzed by the circuit analysis unit 122. As described above, the configuration control unit 120 determines the optimum impedance according to the correlation of the FPGAs directly connected to each other and generates the test configuration data, and the accuracy according to the connection state of the FPGA. Can support a high level of test execution.

  In addition, although this embodiment was taken as the form added to 1st Embodiment, it is also possible to add to 2nd Embodiment. When added to the second embodiment, test configuration data is generated by determining the optimum impedance in accordance with the correlation of FPGAs adjacent to a plurality of boards, thereby shortening the test execution time. However, the test quality is improved and the test efficiency can be increased.

DESCRIPTION OF SYMBOLS 100 Configuration apparatus 110 Data holding part 111 Test configuration data 111a Test device data 112 Formal configuration data 112a Formal device data 120 Configuration control part 121 Circuit extraction part 122 Circuit analysis part 123 Line characteristic specification part 124 Impedance Allocation unit 130 Configuration data selection unit 140 Conformity determination unit 150 Warning notification unit 160 Display unit 170 Reset unit 200 FPGA unit 200a Test signal generation unit 200b Test signal confirmation unit 210, 210A, 210B, 210C

Claims (6)

In a configuration device for constructing a logic circuit in a plurality of electronic components connected to each other,
Corresponding to a plurality of test configuration data for constructing a test logic circuit in one of the plurality of electronic components and another electronic component, and the plurality of test configuration data Holding means for holding a plurality of formal configuration data for constructing a formal logic circuit in the one electronic component and the other electronic component;
Control means for constructing a logic circuit in the one electronic component and the other electronic component according to test configuration data or formal configuration data held in the holding means;
Measuring means for measuring input / output characteristics between the one electronic component and the other electronic component in which an electronic circuit is constructed by the test configuration data;
Extraction means for extracting specific test configuration data from the plurality of test configuration data based on the measurement result of the measurement means;
The control means constructs a logic circuit in the one electronic component and the other electronic component based on formal configuration data associated with the test configuration data extracted by the extracting means. Configuration device.
The configuration device according to claim 1,
Conformity determination means for determining the conformity of the formal configuration data using a threshold for the input / output characteristics measured by the measurement means;
In the case of the formal configuration data determined to be non-conforming based on the conformity determining means, a warning notification means for notifying a warning is provided.
In the configuration device according to claim 1 or claim 2,
When there is one or more boards in which a plurality of the electronic components are interconnected,
The holding means holds a plurality of test data and a plurality of formal configuration data for measuring the operation of the electronic component for each one or a plurality of boards,
The control means constructs a logic circuit for each of the plurality of electronic components for each board by a plurality of test configuration data or formal configuration data corresponding to the control target board held in the holding means,
The measuring means measures input / output characteristics between the plurality of electronic components in which an electronic circuit is constructed by the test configuration data;
The extraction means extracts specific test configuration data from the plurality of test configuration data based on the measurement result of the measurement means,
The configuration device, wherein the control means constructs a logic circuit in the plurality of electronic components based on formal configuration data associated with the test configuration data extracted by the extraction means.
The configuration device according to claim 1, wherein:
The control means is
A circuit extraction unit for extracting a plurality of electronic components directly connected to each other;
A circuit analysis unit for analyzing the electronic component extracted based on the circuit extraction unit with respect to impedance including at least a resistance component;
Based on the impedance analyzed by the circuit analysis unit, a line characteristic specifying unit that specifies line characteristics between the extracted electronic components,
A configuration apparatus comprising: an impedance allocating unit that allocates the impedance analyzed by the circuit analyzing unit to both or one of the extracted electronic components based on the line characteristic specified by the line characteristic specifying unit.
In a configuration device that constructs a logic circuit in a plurality of electronic components connected to each other,
Corresponding to a plurality of test configuration data for constructing a test logic circuit in one of the plurality of electronic components and another electronic component, and the plurality of test configuration data A holding step for holding a plurality of formal configuration data for constructing a formal logic circuit in the one electronic component and the other electronic component;
A control step of constructing a logic circuit in the one electronic component and the other electronic component by the test configuration data or the formal configuration data held in the holding step;
A measuring step of measuring input / output characteristics between the one electronic component and the other electronic component in which an electronic circuit is constructed by the test configuration data;
An extraction step for extracting specific test configuration data from the plurality of test configuration data based on the measurement result of the measurement step;
The control step constructs a logic circuit in the one electronic component and the other electronic component by the formal configuration data associated with the test configuration data extracted in the extraction step. Yes Configuration method.
In a configuration device that constructs a logic circuit in a plurality of electronic components connected to each other,
Corresponding to a plurality of test configuration data for constructing a test logic circuit in one of the plurality of electronic components and another electronic component, and the plurality of test configuration data Holding means for holding a plurality of formal configuration data for constructing a formal logic circuit in the one electronic component and the other electronic component;
Control means for constructing a logic circuit in the one electronic component and the other electronic component based on test configuration data or formal configuration data held in the holding means,
Measuring means for measuring input / output characteristics between the one electronic component and the other electronic component in which an electronic circuit is constructed by the test configuration data;
Based on the measurement results of the measurement means, the computer functions as an extraction means for extracting specific test configuration data from the plurality of test configuration data,
The control means configures a computer to construct a logic circuit in the one electronic component and the other electronic component based on the formal configuration data associated with the test configuration data extracted by the extracting means. A configuration program to function.

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