JP2011053895A - Data communication apparatus - Google Patents

Abstract

A request source in which a request command and a response to the request command are separated and a worst-case value of a transfer rate needs to be guaranteed in a bus that can issue request commands one after another without waiting for a response to the request command. In contrast, a data communication device that achieves a high guaranteed value is provided.
In a data communication apparatus that performs data transfer via an interface using a spirit transaction protocol, a memory access request is issued in advance of DMAC setting information, and a preceding read access is performed by normal and abnormal termination of the target DMAC. Invalidate the data.
[Selection] Figure 2

Description

  The present invention relates to a data communication apparatus for controlling data transfer through an interface using a spirit transaction protocol.

  Conventional parallel buses such as the PCI bus have the problem that it is difficult to increase the speed due to the synchronization of multiple data bits and the occurrence of crosstalk. The serial method is advantageous for these problems. It is easier to speed up than parallel buses.

  Apart from this, in new buses such as PCI Express, the request command and the response to it are separated, and the request command can be issued one after another without waiting for the response to the request command. It is already known that the usage efficiency can be improved.

  PCI Express is often used in PCs (Personal Computers) and the like, but recently it has begun to be used as an interface between devices in image processing apparatuses such as digital copiers and multi-function peripherals (MFPs). .

  However, a new bus such as PCI Express has a problem that the guaranteed value cannot be increased for a request source that needs to guarantee the worst value of the transfer rate. An example of the request source is a DMAC (Direct Memory Access Controller) for input / output of video output data, and an abnormal image is generated if the transfer rate per unit time cannot be maintained.

  In other words, in a new bus such as PCI Express, a buffer (for holding request commands) is used in order to effectively use the characteristic that request commands can be issued one after another without waiting for a response to the request command. A queue) and issued request commands are temporarily stored in this queue.

  With this configuration, a high request command issue rate can be achieved for PCI Express and the like, but the request source side does not always issue requests at this rate. Even with a high priority DMAC, an address that can be calculated by simple increase / decrease from the read / write access request that is already required and the address data for the processing that is currently executing the processing. To issue a request for.

  For this reason, bus arbitration is performed in a state where a request from a request source having a high priority is not participating.

  At this time, a large number of requests from a request source having a low priority are permitted, loaded in the queue, and waiting for execution.

  Thereafter, a request from a high priority request source is issued, permission is granted for the request, and it is loaded into the queue. However, for this access execution, it is necessary to wait for the execution that has been queued before, and the guaranteed value is taken into account for the execution time of the request that has been queued due to unintentional bus arbitration. It is necessary to. Therefore, there is a problem that the guaranteed value cannot be increased.

  As a conventional example related to the present invention, there is Patent Document 1 (Japanese Patent Laid-Open No. 2007-249816). The invention of Patent Document 1 can perform priority arbitration while maintaining consistency between the arbiter setting and the actual traffic priority even when a transaction layer transmission buffer is interposed. It has a statistical information generation means, and realizes it by changing the arbitration table in real time according to the result.

  However, the invention of Patent Document 1 adjusts the arbiter using statistical information of actual packet data, the accuracy is unknown, and a request source that needs to guarantee the worst value of the transfer rate. On the other hand, it is not easy to set guaranteed values.

  The present invention has been made in view of the above circumstances, and a request command and a response to the request command are separated, and transfer is performed in a bus that can issue request commands one after another without waiting for a response to the request command. An object of the present invention is to provide a data communication apparatus that achieves a high guaranteed value for a request source that needs to guarantee the worst value of a rate.

  In order to achieve this object, the data communication device of the present invention issues a memory access request in advance of the DMAC setting information in a data communication device that transfers data via an interface using a spirit transaction protocol. In this case, the previous read access data is invalidated due to normal and abnormal termination of the target DMAC.

  The data communication apparatus according to the present invention is characterized in that the preceding read access is not executed until another DMAC write is performed on the preceding read target DMAC in the preceding read target address area.

  The data communication apparatus according to the present invention is characterized in that a memory dividing method for holding data that has undergone preceding read access is programmable.

  In the data communication apparatus of the present invention, the write access from the DMAC is not executed until another DMAC is performed on the target address area.

  The data communication apparatus according to the present invention is characterized in that arbitration is performed by a round robin method as an arbiter arbitration method.

  In the data communication apparatus of the present invention, when permission is not given to the request source because there is no access request from the request source, the access request source from the DMAC having a dependency relation to the access request of the request source It is characterized by giving permission.

  According to the present invention, a request command and a response to the request command are separated, and it is necessary to guarantee the worst value of the transfer rate in a bus that can issue request commands one after another without waiting for a response to the request command. A high guaranteed value can be achieved for a given source.

1 is a conceptual diagram illustrating a configuration example of a multifunction peripheral (MFP) according to an embodiment of the present invention. It is a block diagram which shows the structural example of the controller ASIC part which concerns on one Embodiment of this invention. It is a block diagram which shows the internal structure of the endpoint of PCI Express concerning one Embodiment of this invention. It is a figure which shows about transfer of the interlock type bus | bath employ | adopted with the PCI bus. It is a figure which shows the transfer of a spirit transaction type bus | bath employ | adopted as PCI Express. It is a figure which shows the mode of the conventional transfer in a spirit transaction type bus | bath. It is a block diagram which shows the structure of the prefetch control circuit which concerns on one Embodiment of this invention. It is a figure which shows the flow of data in the case of providing the prefetch control circuit which concerns on one Embodiment of this invention. It is a figure which shows the detail of each part (Target DMAC parameter register, Current DMAC parameter register, Request parameter register, Request buffer, Buffer memory management register) in the prefetch control circuit concerning one Embodiment of this invention. It is a flowchart which shows the operation example of the request parameter register which concerns on one Embodiment of this invention. It is a figure which shows the mode of transfer when the prefetch control circuit which concerns on one Embodiment of this invention is used. 6 is a flowchart showing an operation of DMA cooperation of the prefetch control circuit according to the embodiment of the present invention. It is a figure which shows the mode of arbitration of the arbiter which concerns on one Embodiment of this invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments (embodiments) for carrying out the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a conceptual diagram showing a configuration of a multifunction peripheral (MFP) which is an embodiment of an image processing apparatus of the present invention. As shown in FIG. 1, the image processing apparatus according to the present embodiment includes a scanner unit 101 that reads a document, a plotter unit 102 that outputs a print, and an engine control ASIC (Application Specific Integrated Circuit) that controls the scanner unit 101 and the plotter unit 102. ) 103, a controller ASIC (Application Specific Integrated Circuit) 104 for controlling the entire MFP, a CPU (Central Processing Unit) 105 for controlling the entire MFP, a program, data, image data, etc. for operating the CPU 105 Memory 106, PCI Express 107 which is an interface between the engine control ASIC 103 and the controller ASIC 104, PCI Express 108 which is an interface between the controller ASIC 104 and the CPU 105, and SSTL 1 which is an interface between the CPU 105 and the memory 106 Equipped with a 8. The memory 106 is controlled by a memory controller built in the CPU 105 and is interfaced with the SSTL standard.

  FIG. 2 shows a configuration example of a portion of the controller ASIC 104 (one embodiment of the data communication apparatus of the present invention) in FIG.

  Reference numeral 201 denotes a PCI Express root complex. The root complex of PCI Express is positioned at the highest level in the I / O hierarchy of the system, and the end is the engine control ASIC 103 in FIG.

  On the other hand, 202 is a PCI Express endpoint. The PCI Express endpoint is located at the end of the PCI Express I / O structure. The PCI Express root complex for this is the CPU 105 in FIG. As a result, the controller ASIC 104 interfaces with the engine control ASIC 103 and the CPU 105.

  Reference numerals 203 to 206 denote video output controllers for controlling the output of print data, and there are four channels from 0 to 3. These have the read DMACs 207 to 210 and read data from the memory outside the controller ASIC.

  Reference numeral 211 denotes a video input controller that controls data read by the scanner. The scanner data from the engine control ASIC 103 is received via the PCI Express route complex 201 via the PCI Express 228. The video input controller 211 has a write DMAC 212 and writes data to a memory outside the controller ASIC 104.

  Reference numerals 213 to 216 denote controller units 0 to 3 such as a decompressor for compressed data. Each controller unit 0 to 3 has a read DMAC 217 to 220 for reading original data from a memory outside the controller ASIC 104 and processed data. Have write DMACs 221 to 224 for writing to the memory outside the controller ASIC 104.

  Reference numeral 226 denotes an arbiter that arbitrates a memory access request outside the controller ASIC 104 from the read / write DMAC. The arbitration method is round robin.

  Reference numeral 225 denotes a prefetch control circuit that detects memory access that will be required in the future from the setting information set in the DMAC, and reads the memory in advance. Also for a write request, control is performed so that write access is not executed until another DMAC is performed on the target address area.

  A selector 227 selects data to be output to the engine control ASIC 103 by the PCI Express route complex 201.

  FIG. 3 is a block diagram showing an internal configuration of the PCI Express endpoint 202 shown in FIG. As shown in FIG. 3, the PCI Express endpoint 202 can be divided into three layers: Transaction Layer, Data Link Layer, and Physical MAC Layer.

  The Transaction Layer has a transmission buffer and a reception buffer so that request commands and data can be temporarily stored. For this reason, the transmission buffer and reception buffer effects have the effect of increasing the transfer efficiency, but conversely, the guaranteed value cannot be increased for the request source that needs to guarantee the worst value of the transfer rate. was there.

  FIG. 4 shows the transfer of the interlock type bus adopted in the PCI bus or the like. After issuing a read request, the next request command cannot be issued until the corresponding read data is received.

  On the other hand, FIG. 5 shows the transfer of a spirit transaction type bus adopted in PCI Express or the like. Here, the next request command can be issued without waiting for a response to the read request. For this reason, even if the read latency is the same, the transfer rate of the spirit transaction type bus can be increased.

  FIG. 6 shows a state of the conventional transfer in the spirit transaction type bus. Requests are issued from the request sources A, B, and C at time t0. Here, A and B are request sources having a high priority and C is a request source having a low priority. The arbiter grants permission to the request from A, and loads the request R_A0 from A (the 0th read request from A) in the buffer of the accepted command.

  At time t1, the arbiter grants permission for the request from B, and loads the request R_B0 (the 0th read request from B) from B in the buffer of the accepted command. At this time, R_A0 loaded in the buffer is transferred to the transmission channel on the transmission side.

  At time t2, the arbiter grants permission to the request from A, and loads the request R_A1 (first read request from A) from A in the buffer of the accepted command. No permission is given to C due to the priority of the arbiter. At this time, R_B0 loaded in the buffer is transferred to the transmission channel on the transmission side. At this time, the read data corresponding to the R_A0 request is transferred to the receiving side transmission path. However, because of the transfer data amount, the time required to transfer the read data is longer than the transfer of the read command, which is represented by the difference in size in FIG.

  If transfer is performed in this way, the number of read commands that can be issued in an incomplete state with respect to the read command issued by itself is limited (two in FIG. 6). However, a state that cannot be issued occurs. The request from A can be issued when the read data for R_A0 is returned at t4 (even at t8, it can be issued when the read data for R_A1 is returned).

  The same applies to B. In this state, both A and B cannot be issued even if a request is issued, and the request from C is permitted in this gap. When the request from C is a write request, since the command and write data are sent on the transmission line on the transmission side, the transfer takes a long time, and after the transmission is completed, the next permitted command is transmitted on the transmission side transmission line. Therefore, even if the request source has a high priority, the read latency becomes long.

  From the above, this embodiment is provided with the prefetch control circuit 225 shown in FIG. FIG. 7 is a block diagram showing the structure of the prefetch control circuit.

  As shown in FIG. 7, the prefetch control circuit 225 includes a target DMAC parameter register, a request parameter register, a buffer memory management register, a current DMAC parameter register, a request buffer, a prefetch control circuit overall control, a buffer memory controller, and a buffer memory. Configured.

  FIG. 8 is a diagram showing a data flow when a prefetch control circuit is provided. The data flow described with reference to FIG. 8 shows how the DMAC in the controller ASIC 104 reads the descriptor (DMAC execution parameter) and data existing in the memory 106 and executes the process in FIG. Show. Hereinafter, a description will be given with reference to FIG.

  The exec is a start register flag that exists for each DMAC, and starts when 1 and ends when 0.

  param (dmac) indicates the status of the parameter register in dmac, and the broken line indicates that the parameter register contents are invalid.

  req (dmac) indicates the status of a memory access request from dmac.

  r_desc indicates a read request for descriptor contents existing in the memory, and r_L0_0 indicates a read request for the 0th data of line 0 existing in the memory. Similarly, r_L0_1 is a read request for the first data of line 0 existing in the memory.

  data (dmac) indicates read data in response to the read request for req (dmac) described above, and a dedicated data line is provided between the prefetch control circuit and dmac.

  Here, in order to simplify the description, an example is shown in which all memory access requests are read requests. When writing is required, a data line different from this may be provided.

  desc means descriptor data (response data to r_desc), and d_L0_0 means read data of the 0th data on line 0 (response data to r_L0_0).

  param (pr) indicates the state of the parameter register of the prefetch control circuit, and the broken line indicates that the parameter register contents are invalid.

  req (pr) indicates the state of the memory access request from the prefetch control circuit. r_L0_0 indicates a read request for the 0th data of line 0 existing in the memory.

  Basically, a read request for the same address is made ahead of a read request from dmac.

  data (pr) indicates read data corresponding to the read request of req (pr) described above.

  buff (pr) is a buffer that holds the read data received by the data (pr) described above. In response to a read request from dmac, the data in the buffer is transferred to dmac, and the data is transferred. Delete from the buffer.

  When exec reaches 0, all data held in the buffer is discarded.

  In the following, the operation will be described with time in FIG.

  At t1, exec is set to 1 (software setting by the CPU).

  req (dmac) indicates r_desc, and dmac issues a descriptor read request.

  This is input to the prefetch control circuit, and the prefetch control circuit indicates r_desc in data (pr) and issues a descriptor read request.

  At t2, the data read from the memory is put on data (pr) and input to the prefetch control circuit.

  This data is also input to dmac, and is set in the prefetch control circuit and each parameter register of dmac at t3.

  In FIG. 8, this is indicated by the location where param (dmac) and param (pr) change from the invalid state to the confirmed state at the timing of t3.

  At t4, based on the set parameter information, both dmac and the prefetch control circuit request the first data (0th data on line 0) used by the DMAC.

  At t5, both dmac and the prefetch control circuit request the next data (first data on line 0) used by the DMAC.

  The read request data from the dmac is only input to the prefetch control circuit, and the prefetch control circuit receives the response data for the read request from the prefetch control circuit and passes this to the dmac. answer.

  At t6, read data from the memory is input to the prefetch control circuit (response data for r_L0_0, d_L0_0).

  At t7, d_L0_0 existing in the data line of data (pr) is input to the buffer of the prefetch control circuit.

  At t8, the d_L0_0 data input to the buffer of the prefetch control circuit is put on data (dmac) and transferred to dmac.

  In this way, read request data from dmac is passed to dmac via the prefetch control circuit.

  The same applies to the timing from t9 to t11.

  At t9, read data from the memory is input to the prefetch control circuit (response data for r_L0_1, d_L0_1).

  At t10, d_L0_1 present in the data line of data (pr) is input to the buffer of the prefetch control circuit.

  At t11, d_L0_1 data input to the buffer of the prefetch control circuit is put on data (dmac) and transferred to dmac.

  At t12, since the data received by dmac has been consumed to some extent, a new read request is made for subsequent data. r_L0_2 is indicated in req (dmac).

  At t13, since the read data requested at t12 is present in the buffer of the prefetch control circuit, it is transferred from here to dmac.

  Similarly, at t14 and t15, since the data requested by dmac to be read exists in the buffer of the prefetch control circuit, it is transferred to dmac from here.

  At t16, 0 is set to exec (forced termination) by the CPU, so the data in the buffer of the prefetch control circuit is cleared.

  FIG. 9 shows details of each part of the prefetch control circuit shown in FIG. 7, that is, a target DMAC parameter register, a current DMAC parameter register, a request parameter register, a request buffer, and a buffer memory management register.

  The target DAMC parameter register holds the same DMAC parameters as those set in the DMAC that are targets of prefetch control.

  Specifically, in the present embodiment, SA: start address read from the memory, MW: memory width (memory width up to the next line during two-dimensional transfer), IW: image line width, LC: number of processing lines . Having this parameter enables DMA transfer.

  The current DMAC parameter register is used by the prefetch control circuit to hold parameters that are being prefetched, and is used to update the value each time a prefetch is requested and to calculate the next requested address and size. The

  In this embodiment, C_SA: current start address, C_MW: memory width (memory width up to the next line during two-dimensional transfer), C_IW: image line width, C_LC: current number of remaining processing lines, L_SA: current Holds the start address for this line.

  The request parameter register holds a request start address, a request size, and an ID for managing IDs calculated for each DMAC.

  The request buffer buffers the permitted request, and holds information for associating with the request content by the ID when the read response is returned.

  In the present embodiment, ID, R_SA: request start address, and R_IW: request size information are held.

  The read response data is associated with the request based on the ID information, managed by the buffer memory management register for each DMAC, and held in the buffer memory.

  The configuration of the buffer memory management register in this embodiment will be described below with reference to FIG.

  Buf_SA: Controls how the buffer memory is used, and holds the buffer memory use start address for the DMAC.

  Buf_EA: Controls how the buffer memory is used, and holds the buffer memory use end address for the DMAC.

  Buf_SA and Buf_EA can be set from the CPU.

  Data_SA: Indicates the start address where valid data for the DMAC is stored in the buffer memory.

  Data_EA: An end address at which valid data for the DMAC is stored in the buffer memory.

  In some cases, Data_EA <Data_SA. In this case, it means that valid data is stored from Data_SA to Buf_EA, and the subsequent data is stored from Buf_SA to Data_EA.

  PH_SA0: A value that is meaningful for two-dimensional DMAC, and holds the start address of the 0th line of data stored in the buffer memory (not the address of the buffer memory but the address requested by the DMAC).

  SIZE0: Holds a value indicating how much data is stored in the buffer memory from the start address of the line with respect to the start address indicated by PH_SA0.

  PH_SA1: A value that is meaningful for two-dimensional DMAC, and holds the start address of the first line of data stored in the buffer memory (not the address of the buffer memory but the address requested by the DMAC).

  SIZE0: Holds a value indicating how much data is stored in the buffer memory from the start address of the line with respect to the start address indicated by PH_SA1.

  Note that PH_SA1 and SIZE1 are not always valid values, and are only present when two lines of data are held in the buffer memory.

  FIG. 10 shows a method of generating R_SA (request start address), R_IW (request size) and ID in the request parameter register of FIG. In FIG. 8, exec is set to 1, descriptor reading is performed, and the prefetch control circuit generates a request for the prefetch control circuit to execute the prefetch of the DMAC after the parameter register setting of the prefetch control circuit is completed.

  First, the ID is initialized with 0 (S1).

  Next, the target DMAC parameter register value of the current value is set to C_SA (current value of start address), C_MW (current value of memory width), C_IW (current value of image width), C_LC (current number of remaining processing lines) , L_SA (start address for the current line) is set (S2).

  If C_LC (current number of remaining processing lines) is 0 (S3 / YES), the process ends and the process proceeds to END.

  If C_LC is not 0 (S3 / NO), C_SA is substituted into R_SA as a request start address (S4).

  Next, it is checked whether C_IW (current number of remaining processed image lines) is smaller than 257 (S5).

  If C_IW is smaller than 257 (S5 / YES), C_IW is assigned to R_IW, IW is assigned to C_IW, C_LC-1 is assigned to C_LC, L_SA + MW is assigned to C_SA, and C_SA is assigned to L_SA (S6).

  If C_IW is greater than or equal to 257 (S5 / NO), the size is set to 256 (S8).

  Next, the ID is incremented (S7), and the process returns to S3.

  By performing such processing, a request start address, a request access size, and an ID corresponding thereto can be generated.

  FIG. 11 is a diagram showing a state of transfer in the present embodiment.

  As described above, in FIG. 6 in the conventional example, a request cannot be issued because the number of read commands that can be issued in an incomplete state with respect to the read command issued by itself is limited (two in FIG. 6). As a result, a low priority request (especially a write request) entered the gap, and the execution of a high priority request issued thereafter was delayed.

  However, in FIG. 11 in the present embodiment, a pre-read control circuit is provided, which can hold a large amount of read data, and a necessary amount of data is read in advance. Requests are unwillingly granted and high priority requests are not waited significantly. Of course, if access to a request with a high priority is not required, a request is issued for a request with a low priority. In this case, when it becomes necessary to access the high priority sequential request source again, in the read latency of the first read data, the delay amount may increase as in the case where the present invention is not applied. However, in this case, since the reading is performed in advance, there is a time margin (the read data is not used immediately, but is used after consuming the previously read data. The effect of this is not a problem.

  FIG. 12 is a flowchart showing a processing operation of DMA cooperation. There are two types of DMA linkage, when the target DMAC performs reading and writing. When the target DMAC performs reading, it waits for the DMAC to be linked to write valid data to the read data, and issues a read request. On the other hand, when the target DMAC performs the write, the DMAC to be linked issues a write request after waiting for the read area to be already read.

  As shown in FIG. 12, the determination is made by comparing the address with the cooperation target DMAC. If the DMA linkage is not valid (S11 / NO), the access request is issued as it is (S14).

  On the other hand, when the DMA linkage is valid (S11 / YES), it is divided into a read request (S12 / YES) and a write request (S12 / NO).

  When the request is a read request (S12 / YES), the operation is as follows. That is, if the address of the read request is within the address range already written by the write side DMAC (S13 / YES), the access request is issued, and if not (S13 / NO), the process ends.

  Similarly, the case of a write request (S12 / NO) is as follows. That is, if the address of the write request is within the address range that has been read by the read side DMAC (S15 / YES), the access request is issued; otherwise (S15 / NO), the process ends.

  Note that the DMA linkage processing is processing of the prefetch control circuit, and whether the request is actually requested from the PCI Express arbiter after the request start address, the requested access size, and the ID corresponding thereto are generated as shown in FIG. Used to determine if.

  FIG. 13 shows a state of arbitration of the arbiter (round robin method). By using this arbiter, when DMAC linkage is performed, access is optimally executed. Hereinafter, a description will be given with reference to FIG.

  The priority order in the state of t1 is shown. E / F indicates E or F, and switches between E and F in order of priority.

  At t1, the request is from above, or the request itself is not issued, but it is checked whether the linked DMAC has issued the request, and permission is granted to the first that satisfies that condition .

  In the example of t1, permission is given to B, and the priority order at t2 is changed with B being the highest priority order.

  In t3, no request is issued for G, H, and C, but J as a cooperation destination DMAC of C is an example in which a request is issued.

  In this case, as in the case where J is permitted and C is permitted, I / J is set to the highest priority and switched (see t4).

  By switching as described above, the processing efficiency of the request source that cannot issue a request due to the waiting process of the DMAC at the cooperation destination is improved.

  As described above, according to the present embodiment, the request command such as PCI Express and the response to the request command are separated, and the request command is issued one after another without waiting for the response to the request command. In a possible bus, a high guaranteed value can be achieved for a request source that needs to guarantee the worst value of the transfer rate.

  Conventionally, a conventional arbitration method optimal for a PCI bus or the like is used as it is even in a bus in which a request command and a response to the request command are separated like PCI Express.

  As with PCI Express, bus arbitration is performed without waiting for a response in a bus in which a request command and a response to the request are separated. Therefore, a low priority is provided with a gap between requests from a high-priority request source. Since a large number of requests from the request sources with the ranks are granted and are queued for processing, the execution for the request sources with the high priority that has been granted thereafter is delayed.

  In particular, the fluctuation range of the delay time is large, and a sufficiently large value is set so as to cover even the worst case, and the device is designed using the value. For this reason, a high transfer rate cannot be realized for a request source having a high priority.

  Therefore, in this embodiment, an environment that can be arbitrated systematically is constructed, and arbitration is performed as expected under that environment. Therefore, the transfer that the bus has for the request source that needs to guarantee the worst value. Capabilities can be allocated without waste, and a high guaranteed value can be achieved.

  As mentioned above, although embodiment of this invention was described, it is not limited to the said embodiment, A various deformation | transformation is possible in the range which does not deviate from the summary.

  For example, the operation in the above-described embodiment can be executed by hardware, software, or a combined configuration of both.

  When executing processing by software, a program in which a processing sequence is recorded may be installed and executed in a memory in a computer incorporated in dedicated hardware. Or you may install and run a program in the general purpose computer which can perform various processes.

  For example, the program can be recorded in advance on a hard disk or a ROM (Read Only Memory) as a recording medium. Alternatively, the program is temporarily or permanently stored on a removable recording medium such as a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto optical) disc, a DVD (Digital Versatile Disc), a magnetic disc, or a semiconductor memory. It can be stored (recorded). Such a removable recording medium can be provided as so-called package software.

  The program may be wirelessly transferred from the download site to the computer in addition to being installed on the computer from the removable recording medium as described above. Or you may wire-transfer to a computer via networks, such as LAN (Local Area Network) and the internet. The computer can receive the transferred program and install it on a recording medium such as a built-in hard disk.

  In addition to being executed in time series in accordance with the processing operations described in the above embodiment, the processing capability of the apparatus that executes the processing, or a configuration to execute in parallel or individually as necessary Is also possible.

  The present invention relates to an apparatus / device, system for transferring data using a bus that can issue request commands one after another without waiting for a response to the request command, in which the request command and the response to the request command are separated. Applicable to methods, programs, etc.

101 Scanner unit 102 Plotter unit 103 Engine control ASIC
104 Controller ASIC
105 CPU
106 Memory 107 PCI Express
108 PCI Express
109 SSTL
201 PCI Express root complex 202 PCI Express endpoint 203-206 Video output controller 207-210 Read DMAC
211 Video input controller 212 Light DMAC
213 to 216 Controller unit 217 to 220 Read DMAC
221-224 Light DMAC
225 prefetch control circuit 226 arbiter 227 selector 228 PCI Express

JP 2007-249816 A

Claims (6)

In a data communication device that performs data transfer via an interface that uses a spirit transaction protocol,
A data communication apparatus that issues a memory access request in advance of setting information of a DMAC and invalidates data that was previously read-accessed due to normal and abnormal termination of the target DMAC.   2. The data communication apparatus according to claim 1, wherein the preceding read access is not executed until a different DMAC write is performed on the preceding read target DMAC in the preceding read target address area.   3. The data communication apparatus according to claim 1, wherein a method for dividing a memory for holding data that has undergone preceding read access is programmable.   The data according to any one of claims 1 to 3, wherein the write access from the DMAC is not executed until another DMAC is performed on the target address area. Communication device.   5. The data communication apparatus according to claim 1, wherein arbitration is performed by a round robin method as an arbitration method of the arbiter.   If permission is not granted to the request source because there is no access request from the request source, permission is granted to the access request source from the dependent DMAC for the access request of the request source. The data communication device according to claim 1, wherein:

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